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Prefs/hds_user/v2009.2/templates/registered_views/Vunit_Verilog.psl

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+DESCRIPTION_START
+This is the default template used for the creation of PSL Vunit (Verilog) files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// PSL Vunit(Verilog Syntax)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
+
+vunit %(view) ([%(unit)])
+{
+    default clock = ClockName;
+    
+}