Initial commit

Prefs/hds_user/v2009.2/templates/verilog_module/module.v

@@ -0,0 +1,18 @@
+FILE_NAMING_RULE: %(module_name).v
+DESCRIPTION_START
+This is the default template used for the creation of Verilog Module files.
+Template supplied by Mentor Graphics.
+DESCRIPTION_END
+//
+// Verilog Module %(library).%(unit)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// using Mentor Graphics HDL Designer(TM) %(version)
+//
+%(moduleBody)
+// ### Please start your Verilog code here ### 
+
+endmodule

Prefs/hds_user/v2009.2/templates/verilog_module/module_migrated.v

@@ -0,0 +1,22 @@
+FILE_NAMING_RULE: %(module_name).v
+DESCRIPTION_START
+Template for the creation of Verilog Module files.
+This template was migrated from header preferences created in a
+previous version of HDL Designer.
+DESCRIPTION_END
+// 
+//
+// Module %(library).%(unit).%(view)
+//
+// Created:
+//          by - %(user).%(group) (%(host))
+//          at - %(time) %(date)
+//
+// Generated by Mentor Graphics' HDL Designer(TM) %(version)
+//
+// 
+%(moduleBody)
+// 
+// ### Please start your Verilog code here ### 
+
+endmodule