diff --git a/doc/examples.typ b/doc/examples.typ
index d968bf9..e033343 100644
--- a/doc/examples.typ
+++ b/doc/examples.typ
@@ -115,6 +115,46 @@ gates.gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
 gates.gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
 ```, vertical: true)
 
+#let iec-gate-and = example(```
+gates.iec-gate-and(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-and(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-nand = example(```
+gates.iec-gate-nand(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-nand(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-or = example(```
+gates.iec-gate-or(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-or(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-nor = example(```
+gates.iec-gate-nor(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-nor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-xor = example(```
+gates.iec-gate-xor(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-xor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-xnor = example(```
+gates.iec-gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-buf = example(```
+gates.iec-gate-buf(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-buf(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-not = example(```
+gates.iec-gate-not(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-not(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
 #let group = example(```
 element.group(
   id: "g1", name: "Group 1", stroke: (dash: "dashed"),
diff --git a/gallery/test7.pdf b/gallery/test7.pdf
new file mode 100644
index 0000000..e1a8507
Binary files /dev/null and b/gallery/test7.pdf differ
diff --git a/gallery/test7.png b/gallery/test7.png
new file mode 100644
index 0000000..345e5a5
Binary files /dev/null and b/gallery/test7.png differ
diff --git a/gallery/test7.typ b/gallery/test7.typ
new file mode 100644
index 0000000..94a70e3
--- /dev/null
+++ b/gallery/test7.typ
@@ -0,0 +1,98 @@
+#import "@preview/cetz:0.3.2": draw
+#import "../src/lib.typ": circuit, element, util, wire
+
+#set page(width: auto, height: auto, margin: .5cm)
+
+#circuit({
+  element.iec-gate-buf(
+    x: 0,
+    y: 0,
+    w: 2,
+    h: 2,
+    id: "iec-buf",
+    inputs: 1,
+  )
+  wire.stub("iec-buf-port-in0", "west")
+
+  element.iec-gate-not(
+    x: 3,
+    y: 0,
+    w: 2,
+    h: 2,
+    id: "iec-not",
+    inputs: 1,
+  )
+  wire.stub("iec-not-port-in0", "west")
+
+  element.iec-gate-and(
+    id: "iec-and",
+    x: 0,
+    y: -3,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-and-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-nand(
+    id: "iec-nand",
+    x: 3,
+    y: -3,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-nand-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-or(
+    id: "iec-or",
+    x: 0,
+    y: -6,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-or-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-nor(
+    id: "iec-nor",
+    x: 3,
+    y: -6,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-nor-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-xor(
+    id: "iec-xor",
+    x: 0,
+    y: -9,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-xor-port-in" + str(i), "west")
+  }
+
+  element.iec-gate-xnor(
+    id: "iec-nxor",
+    x: 3,
+    y: -9,
+    w: 2,
+    h: 2,
+    inputs: 2,
+  )
+  for i in range(2) {
+    wire.stub("iec-nxor-port-in" + str(i), "west")
+  }
+})
\ No newline at end of file
diff --git a/manual.pdf b/manual.pdf
index 8d1abf7..f193a3b 100644
Binary files a/manual.pdf and b/manual.pdf differ
diff --git a/manual.typ b/manual.typ
index 7a327d6..b6bde05 100644
--- a/manual.typ
+++ b/manual.typ
@@ -195,7 +195,12 @@ If you have installed Circuiteria directly in your project, import #link("src/li
   read("src/elements/logic/and.typ") + "\n" +
   read("src/elements/logic/buf.typ") + "\n" +
   read("src/elements/logic/or.typ") + "\n" +
-  read("src/elements/logic/xor.typ"),
+  read("src/elements/logic/xor.typ") + "\n" +
+  read("src/elements/logic/iec_gate.typ") + "\n" +
+  read("src/elements/logic/iec_and.typ") + "\n" +
+  read("src/elements/logic/iec_buf.typ") + "\n" +
+  read("src/elements/logic/iec_or.typ") + "\n" +
+  read("src/elements/logic/iec_xor.typ"),
   name: "gates",
   old-syntax: true,
   scope: (
diff --git a/src/element.typ b/src/element.typ
index 3bf0e17..89c3032 100644
--- a/src/element.typ
+++ b/src/element.typ
@@ -11,5 +11,10 @@
 #import "elements/logic/or.typ": gate-or, gate-nor
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
 #import "elements/logic/buf.typ": gate-buf, gate-not
+#import "elements/logic/iec_gate.typ": iec-gate
+#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
+#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
+#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
+#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor
 
 #import "elements/group.typ": group
\ No newline at end of file
diff --git a/src/elements/logic/iec_and.typ b/src/elements/logic/iec_and.typ
new file mode 100644
index 0000000..ef4beab
--- /dev/null
+++ b/src/elements/logic/iec_and.typ
@@ -0,0 +1,70 @@
+#import "@preview/cetz:0.3.2": draw
+// #import "iec_gate.typ" as iec-gate
+#import "iec_gate.typ" as iec-gate
+
+
+/// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-and
+#let iec-gate-and(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  ),
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: $amp$,
+  )
+
+}
+
+/// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-nand
+#let iec-gate-nand(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  ),
+) = {
+  iec-gate-and(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
+    debug: debug,
+  )
+}
\ No newline at end of file
diff --git a/src/elements/logic/iec_buf.typ b/src/elements/logic/iec_buf.typ
new file mode 100644
index 0000000..a327f08
--- /dev/null
+++ b/src/elements/logic/iec_buf.typ
@@ -0,0 +1,68 @@
+#import "@preview/cetz:0.3.2": draw
+#import "iec_gate.typ" as iec-gate
+
+
+/// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()`
+///
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-buf
+#let iec-gate-buf(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false,
+  ),
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: "1",
+  )
+}
+
+/// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-not
+#let iec-gate-not(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false,
+  ),
+) = {
+  iec-gate-buf(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" { inverted + ("out",) } else { inverted },
+    debug: debug,
+  )
+}
diff --git a/src/elements/logic/iec_gate.typ b/src/elements/logic/iec_gate.typ
new file mode 100644
index 0000000..9a3b3fd
--- /dev/null
+++ b/src/elements/logic/iec_gate.typ
@@ -0,0 +1,125 @@
+#import "@preview/cetz:0.3.2": draw, coordinate
+#import "../ports.typ": add-ports, add-port
+#import "../element.typ"
+
+#let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = {
+  let shapes = draw.rect(
+    inset: 0.5em,
+    fill: fill,
+    stroke: stroke,
+    name: id,
+    bl, tr
+  )
+  shapes += draw.content(
+    id + ".center",
+    [*$ symbol $*]
+  )
+  return (shapes, tl, tr, br, bl)
+}
+
+/// Draws a logic gate. This function is also available as `element.iec-gate()`
+///
+/// - draw-shape (function): see #doc-ref("element.elmt")
+/// - x (number, dictionary): see #doc-ref("element.elmt")
+/// - y (number, dictionary): see #doc-ref("element.elmt")
+/// - w (number): see #doc-ref("element.elmt")
+/// - h (number): see #doc-ref("element.elmt")
+/// - inputs (int): The number of inputs
+/// - fill (none, color): see #doc-ref("element.elmt")
+/// - stroke (stroke): see #doc-ref("element.elmt")
+/// - id (str): see #doc-ref("element.elmt")
+/// - inverted (str, array): Either "all" or an array of port ids to display as inverted
+/// - inverted-radius (number): The radius of inverted ports dot
+/// - debug (dictionary): see #doc-ref("element.elmt")
+/// - symbol (str): The symbol to display at the center of the gate
+#let iec-gate(
+  draw-shape: default-draw-shape,
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  inverted-radius: 0.1,
+  debug: (
+    ports: false
+  ),
+  symbol: "",
+) = draw.get-ctx(ctx => {
+  let width = w
+  let height = h
+
+  let x = x
+  let y = y
+  if x == none { panic("Parameter x must be set") }
+  if y == none { panic("Parameter y must be set") }
+  if w == none { panic("Parameter w must be set") }
+  if h == none { panic("Parameter h must be set") }
+
+  if (type(x) == dictionary) {
+    let offset = x.rel
+    let to = x.to
+    let (ctx, to-pos) = coordinate.resolve(ctx, (rel: (offset, 0), to: to))
+    x = to-pos.at(0)
+  }
+  
+  if (type(y) == dictionary) {
+    let from = y.from
+    let to = y.to
+    
+    let dy
+    if to == "out" {
+      dy = height / 2
+    } else {
+      dy = height * (i + 0.5) / inputs
+    }
+    
+    let (ctx, from-pos) = coordinate.resolve(ctx, from)
+    y = from-pos.at(1) + dy - height
+  }
+
+  let tl = (x, y + height)
+  let tr = (x + width, y + height)
+  let br = (x + width, y)
+  let bl = (x, y)
+
+  // Workaround because CeTZ needs to have all draw functions in the body
+  let func = {}
+  (func, tl, tr, br, bl) = draw-shape(id, tl, tr, br, bl, fill, stroke, symbol)
+  func
+
+  let space = 100% / inputs
+  for i in range(inputs) {
+    let pct = (i + 0.5) * space
+    let port-pos = (tl, pct, bl)
+    let port-name = "in" + str(i)
+    if inverted == "all" or port-name in inverted {
+      draw.circle(
+        port-pos,
+        radius: inverted-radius,
+        anchor: "east",
+        stroke: stroke
+      )
+      port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
+    }
+    add-port(
+      id, "west",
+      (id: port-name), port-pos,
+      debug: debug.ports
+    )
+  }
+
+  let out-pos = id + ".east"
+  if inverted == "all" or "out" in inverted {
+    draw.circle(out-pos, radius: inverted-radius, anchor: "west", stroke: stroke)
+    out-pos = (rel: (2 * inverted-radius, 0), to: out-pos)
+  }
+  add-port(
+    id, "east",
+    (id: "out"), out-pos,
+    debug: debug.ports
+  )
+})
\ No newline at end of file
diff --git a/src/elements/logic/iec_or.typ b/src/elements/logic/iec_or.typ
new file mode 100644
index 0000000..98ac673
--- /dev/null
+++ b/src/elements/logic/iec_or.typ
@@ -0,0 +1,67 @@
+#import "@preview/cetz:0.3.2": draw
+#import "iec_gate.typ" as iec-gate
+
+/// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-or
+#let iec-gate-or(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: $>= 1$,
+  )
+}
+
+/// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-nor
+#let iec-gate-nor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate-or(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
+    debug: debug
+  )
+}
\ No newline at end of file
diff --git a/src/elements/logic/iec_xor.typ b/src/elements/logic/iec_xor.typ
new file mode 100644
index 0000000..efbbf83
--- /dev/null
+++ b/src/elements/logic/iec_xor.typ
@@ -0,0 +1,67 @@
+#import "@preview/cetz:0.3.2": draw
+#import "iec_gate.typ" as iec-gate
+
+/// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-xor
+#let iec-gate-xor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: $= 1$,
+  )
+}
+
+/// Draws an IEC-XNOR gate. This function is also available as `element.iec-gate-xnor()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.iec-gate-xnor
+#let iec-gate-xnor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate-xor(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
+    debug: debug
+  )
+}
\ No newline at end of file
diff --git a/src/gates.typ b/src/gates.typ
index 85ba178..616cc57 100644
--- a/src/gates.typ
+++ b/src/gates.typ
@@ -2,4 +2,9 @@
 #import "elements/logic/and.typ": gate-and, gate-nand
 #import "elements/logic/or.typ": gate-or, gate-nor
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
-#import "elements/logic/buf.typ": gate-buf, gate-not
\ No newline at end of file
+#import "elements/logic/buf.typ": gate-buf, gate-not
+#import "elements/logic/iec_gate.typ": iec-gate
+#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
+#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
+#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
+#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor