diff --git a/gallery/riscv/alu_instr.yaml b/gallery/riscv/alu_instr.yaml
new file mode 100644
index 0000000..b1b0cd4
--- /dev/null
+++ b/gallery/riscv/alu_instr.yaml
@@ -0,0 +1,60 @@
+structures:
+  main:
+    bits: 32
+    ranges:
+      31-20:
+        name: op2
+        depends-on: 5
+        values:
+          0:
+            description: second operand is an immediate value
+            structure: immediateOp
+          1:
+            description: second operand is a register
+            structure: registerOp
+      19-15:
+        name: rs1
+      14-12:
+        name: funct3
+        description: operation
+        values:
+          000: add / sub
+          100: xor
+          110: or
+          111: and
+          001: sl
+          101: sr
+      11-7:
+        name: rd
+      6:
+        name: 0
+      5:
+        name: I
+      4:
+        name: 1
+      3:
+        name: 0
+      2:
+        name: 0
+      1:
+        name: 1
+      0:
+        name: 1
+  immediateOp:
+    bits: 12
+    ranges:
+      11-0:
+        name: 12-bit immediate value
+        description: signed number
+  registerOp:
+    bits: 12
+    ranges:
+      11-5:
+        name: funct7
+        description: function modifier
+        values:
+          0000000: default (add, srl)
+          "0100000": sub, sra
+      4-0:
+        name: rs2
+        description: second register operand
diff --git a/gallery/riscv/branch_instr.yaml b/gallery/riscv/branch_instr.yaml
new file mode 100644
index 0000000..e919d24
--- /dev/null
+++ b/gallery/riscv/branch_instr.yaml
@@ -0,0 +1,34 @@
+structures:
+  main:
+    bits: 32
+    ranges:
+      31-25:
+        name: imm
+      24-20:
+        name: rs2
+      19-15:
+        name: rs1
+      14-12:
+        name: funct3
+        description: function modifier
+        values:
+          000: if equal
+          001: if not equal
+          100: if less
+          101: if greater or equal
+      11-7:
+        name: imm
+      6:
+        name: 1
+      5:
+        name: 1
+      4:
+        name: 0
+      3:
+        name: 0
+      2:
+        name: 0
+      1:
+        name: 1
+      0:
+        name: 1
\ No newline at end of file
diff --git a/gallery/riscv/mem_instr.yaml b/gallery/riscv/mem_instr.yaml
new file mode 100644
index 0000000..778fac2
--- /dev/null
+++ b/gallery/riscv/mem_instr.yaml
@@ -0,0 +1,78 @@
+structures:
+  main:
+    bits: 32
+    ranges:
+      31-20:
+        name: src
+        depends-on: 5
+        values:
+          0:
+            description:
+            structure: srcImmediate
+          1:
+            description:
+            structure: srcRegister
+      19-15:
+        name: rs1
+      14-12:
+        name: funct3
+        description: function modifier
+        values:
+          000: byte
+          001: half-word
+          "010": word
+          100: upper byte (load only)
+          101: upper half (load only)
+      11-7:
+        name: dst
+        depends-on: 5
+        values:
+          0:
+            description:
+            structure: dstRegister
+          1:
+            description:
+            structure: dstImmediate
+      6:
+        name: 0
+      5:
+        name: I
+      4:
+        name: 0
+      3:
+        name: 0
+      2:
+        name: 0
+      1:
+        name: 1
+      0:
+        name: 1
+
+  srcImmediate:
+    bits: 12
+    ranges:
+      11-0:
+        name: src
+        description: source memory address
+  srcRegister:
+    bits: 12
+    ranges:
+      11-5:
+        name: dstU
+        description: destination address upper bits
+      4-0:
+        name: rs2
+        description: source register
+
+  dstImmediate:
+    bits: 5
+    ranges:
+      4-0:
+        name: destL
+        description: destination address lower bits
+  dstRegister:
+    bits: 5
+    ranges:
+      4-0:
+        name: rd
+        description: destination register
\ No newline at end of file
diff --git a/gallery/riscv/riscv.pdf b/gallery/riscv/riscv.pdf
new file mode 100644
index 0000000..dfa6bcf
Binary files /dev/null and b/gallery/riscv/riscv.pdf differ
diff --git a/gallery/riscv/riscv.typ b/gallery/riscv/riscv.typ
new file mode 100644
index 0000000..0802ad9
--- /dev/null
+++ b/gallery/riscv/riscv.typ
@@ -0,0 +1,14 @@
+#import "../../src/lib.typ": *
+
+#let conf = config.config(
+  full-page: true,
+  left-labels: true
+)
+#let alu = schema.load("/gallery/riscv/alu_instr.yaml")
+#schema.render(alu, config: conf)
+
+#let branch = schema.load("/gallery/riscv/branch_instr.yaml")
+#schema.render(branch, config: conf)
+
+#let mem = schema.load("/gallery/riscv/mem_instr.yaml")
+#schema.render(mem, config: conf)
diff --git a/gallery/test.pdf b/gallery/test.pdf
index 4b4afa0..a01d02e 100644
Binary files a/gallery/test.pdf and b/gallery/test.pdf differ
diff --git a/src/renderer.typ b/src/renderer.typ
index 5d940a5..b957a88 100644
--- a/src/renderer.typ
+++ b/src/renderer.typ
@@ -410,7 +410,6 @@
     shapes += draw-text(range_.name, txt-col, name-x, name-y, fill: bg-col)
     
     if range_.description != "" {
-      //draw.circle((desc-x, -desc-y), radius: 5, fill: red)
       let shapes_
       (shapes_, desc-x, desc-y) = draw-description(
         config, range_, start-x, bits-y, width, desc-x, desc-y