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version "32.1"
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font "Verdana,8,1"
)
xt "11910,17700,15010,18700"
st "gates"
blo "11910,18500"
tm "BdLibraryNameMgr"
)
*68 (Text
uid 413,0
va (VaSet
font "Verdana,8,1"
)
xt "11910,18700,16110,19700"
st "inverter"
blo "11910,19500"
tm "CptNameMgr"
)
*69 (Text
uid 414,0
va (VaSet
font "Verdana,8,1"
)
xt "11910,19700,14410,20700"
st "U_5"
blo "11910,20500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 415,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 416,0
text (MLText
uid 417,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "12000,20600,26100,21600"
st "delay = gateDelay    ( time )  "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "gateDelay"
)
]
)
viewicon (ZoomableIcon
uid 418,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "12250,16250,13750,17750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*70 (SaComponent
uid 421,0
optionalChildren [
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uid 431,0
ps "OnEdgeStrategy"
shape (Triangle
uid 432,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "24250,36625,25000,37375"
)
tg (CPTG
uid 433,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 434,0
va (VaSet
isHidden 1
)
xt "25000,36700,27300,37900"
st "in1"
blo "25000,37700"
)
s (Text
uid 435,0
va (VaSet
)
xt "25000,37900,25000,37900"
blo "25000,37900"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*72 (CptPort
uid 436,0
optionalChildren [
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uid 441,0
va (VaSet
fg "0,65535,0"
)
xt "30000,36625,30750,37375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 437,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "30750,36625,31500,37375"
)
tg (CPTG
uid 438,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 439,0
va (VaSet
isHidden 1
)
xt "26750,36700,29750,37900"
st "out1"
ju 2
blo "29750,37700"
)
s (Text
uid 440,0
va (VaSet
)
xt "29750,37900,29750,37900"
ju 2
blo "29750,37900"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 422,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "25000,34000,30000,40000"
)
showPorts 0
oxt "34000,15000,39000,21000"
ttg (MlTextGroup
uid 423,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 424,0
va (VaSet
font "Verdana,8,1"
)
xt "24910,39700,28010,40700"
st "gates"
blo "24910,40500"
tm "BdLibraryNameMgr"
)
*75 (Text
uid 425,0
va (VaSet
font "Verdana,8,1"
)
xt "24910,40700,29110,41700"
st "inverter"
blo "24910,41500"
tm "CptNameMgr"
)
*76 (Text
uid 426,0
va (VaSet
font "Verdana,8,1"
)
xt "24910,41700,27410,42700"
st "U_6"
blo "24910,42500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 427,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 428,0
text (MLText
uid 429,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "25000,42600,39100,43600"
st "delay = gateDelay    ( time )  "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "gateDelay"
)
]
)
viewicon (ZoomableIcon
uid 430,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "25250,38250,26750,39750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
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uid 442,0
decl (Decl
n "out1"
t "std_uLogic"
o 8
suid 8,0
)
declText (MLText
uid 443,0
va (VaSet
font "Courier New,8,0"
)
xt "41000,6200,56000,7000"
st "SIGNAL out1    : std_uLogic
"
)
)
*78 (Net
uid 448,0
decl (Decl
n "xorOut"
t "std_ulogic"
o 11
suid 9,0
)
declText (MLText
uid 449,0
va (VaSet
font "Courier New,8,0"
)
xt "41000,8600,56000,9400"
st "SIGNAL xorOut  : std_ulogic
"
)
)
*79 (Net
uid 454,0
decl (Decl
n "out2"
t "std_uLogic"
o 9
suid 10,0
)
declText (MLText
uid 455,0
va (VaSet
font "Courier New,8,0"
)
xt "41000,7000,56000,7800"
st "SIGNAL out2    : std_uLogic
"
)
)
*80 (Net
uid 466,0
decl (Decl
n "out3"
t "std_uLogic"
o 10
suid 11,0
)
declText (MLText
uid 467,0
va (VaSet
font "Courier New,8,0"
)
xt "41000,7800,56000,8600"
st "SIGNAL out3    : std_uLogic
"
)
)
*81 (Net
uid 472,0
decl (Decl
n "xorOut1"
t "std_ulogic"
o 12
suid 12,0
)
declText (MLText
uid 473,0
va (VaSet
font "Courier New,8,0"
)
xt "41000,9400,56000,10200"
st "SIGNAL xorOut1 : std_ulogic
"
)
)
*82 (Wire
uid 15,0
shape (OrthoPolyLine
uid 16,0
va (VaSet
vasetType 3
)
xt "0,39000,46000,42000"
pts [
"0,42000"
"44000,42000"
"44000,39000"
"46000,39000"
]
)
start &1
end &28
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20,0
va (VaSet
isHidden 1
)
xt "2000,40800,5400,42000"
st "clock"
blo "2000,41800"
tm "WireNameMgr"
)
)
on &2
)
*83 (Wire
uid 29,0
optionalChildren [
*84 (BdJunction
uid 482,0
ps "OnConnectorStrategy"
shape (Circle
uid 483,0
va (VaSet
vasetType 1
)
xt "5600,9600,6400,10400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 30,0
va (VaSet
vasetType 3
)
xt "0,10000,34000,10000"
pts [
"0,10000"
"34000,10000"
]
)
start &3
end &57
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 33,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 34,0
va (VaSet
isHidden 1
)
xt "2000,8800,4200,10000"
st "eni"
blo "2000,9800"
tm "WireNameMgr"
)
)
on &4
)
*85 (Wire
uid 43,0
optionalChildren [
*86 (BdJunction
uid 488,0
ps "OnConnectorStrategy"
shape (Circle
uid 489,0
va (VaSet
vasetType 1
)
xt "55600,34600,56400,35400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 44,0
va (VaSet
vasetType 3
)
xt "52000,35000,61000,35000"
pts [
"61000,35000"
"52000,35000"
]
)
start &5
end &31
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 47,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 48,0
va (VaSet
isHidden 1
)
xt "60000,33800,61900,35000"
st "Qi"
blo "60000,34800"
tm "WireNameMgr"
)
)
on &6
)
*87 (Wire
uid 57,0
shape (OrthoPolyLine
uid 58,0
va (VaSet
vasetType 3
)
xt "0,37000,25000,37000"
pts [
"0,37000"
"25000,37000"
]
)
start &7
end &71
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 61,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 62,0
va (VaSet
isHidden 1
)
xt "2000,35800,4700,37000"
st "RaZ"
blo "2000,36800"
tm "WireNameMgr"
)
)
on &8
)
*88 (Wire
uid 71,0
shape (OrthoPolyLine
uid 72,0
va (VaSet
vasetType 3
)
xt "40950,12000,60000,12000"
pts [
"60000,12000"
"40950,12000"
]
)
start &9
end &59
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 75,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 76,0
va (VaSet
isHidden 1
)
xt "59000,10800,62400,12000"
st "RCOi"
blo "59000,11800"
tm "WireNameMgr"
)
)
on &10
)
*89 (Wire
uid 85,0
shape (OrthoPolyLine
uid 86,0
va (VaSet
vasetType 3
)
xt "0,41000,49000,43000"
pts [
"0,43000"
"49000,43000"
"49000,41000"
]
)
start &11
end &30
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 89,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 90,0
va (VaSet
isHidden 1
)
xt "2000,41800,5300,43000"
st "reset"
blo "2000,42800"
tm "WireNameMgr"
)
)
on &12
)
*90 (Wire
uid 99,0
shape (OrthoPolyLine
uid 100,0
va (VaSet
vasetType 3
)
xt "0,15000,12000,15000"
pts [
"0,15000"
"12000,15000"
]
)
start &13
end &64
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 103,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 104,0
va (VaSet
isHidden 1
)
xt "2000,13800,3900,15000"
st "up"
blo "2000,14800"
tm "WireNameMgr"
)
)
on &14
)
*91 (Wire
uid 444,0
shape (OrthoPolyLine
uid 445,0
va (VaSet
vasetType 3
)
xt "17750,15000,20382,15000"
pts [
"17750,15000"
"20382,15000"
]
)
start &65
end &45
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 446,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 447,0
va (VaSet
isHidden 1
)
xt "19750,13800,22750,15000"
st "out1"
blo "19750,14800"
tm "WireNameMgr"
)
s (Text
uid 529,0
va (VaSet
isHidden 1
)
xt "19750,15000,19750,15000"
blo "19750,15000"
tm "SignalTypeMgr"
)
)
on &77
)
*92 (Wire
uid 450,0
shape (OrthoPolyLine
uid 451,0
va (VaSet
vasetType 3
)
xt "28000,14000,34000,17000"
pts [
"28000,17000"
"30000,17000"
"30000,14000"
"34000,14000"
]
)
start &43
end &58
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 452,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 453,0
va (VaSet
isHidden 1
)
xt "30000,15800,34200,17000"
st "xorOut"
blo "30000,16800"
tm "WireNameMgr"
)
s (Text
uid 530,0
va (VaSet
isHidden 1
)
xt "30000,17000,30000,17000"
blo "30000,17000"
tm "SignalTypeMgr"
)
)
on &78
)
*93 (Wire
uid 456,0
shape (OrthoPolyLine
uid 457,0
va (VaSet
vasetType 3
)
xt "42950,35000,46000,35000"
pts [
"42950,35000"
"46000,35000"
]
)
start &52
end &27
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 458,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 459,0
va (VaSet
isHidden 1
)
xt "44950,33800,47950,35000"
st "out2"
blo "44950,34800"
tm "WireNameMgr"
)
s (Text
uid 531,0
va (VaSet
isHidden 1
)
xt "44950,35000,44950,35000"
blo "44950,35000"
tm "SignalTypeMgr"
)
)
on &79
)
*94 (Wire
uid 468,0
shape (OrthoPolyLine
uid 469,0
va (VaSet
vasetType 3
)
xt "30750,37000,36000,37000"
pts [
"30750,37000"
"36000,37000"
]
)
start &72
end &51
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 470,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 471,0
va (VaSet
isHidden 1
)
xt "32750,35800,35750,37000"
st "out3"
blo "32750,36800"
tm "WireNameMgr"
)
s (Text
uid 532,0
va (VaSet
isHidden 1
)
xt "32750,37000,32750,37000"
blo "32750,37000"
tm "SignalTypeMgr"
)
)
on &80
)
*95 (Wire
uid 474,0
shape (OrthoPolyLine
uid 475,0
va (VaSet
vasetType 3
)
xt "28000,28000,36000,33000"
pts [
"28000,28000"
"32000,28000"
"32000,33000"
"36000,33000"
]
)
start &36
end &50
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 476,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 477,0
va (VaSet
isHidden 1
)
xt "30000,26800,34900,28000"
st "xorOut1"
blo "30000,27800"
tm "WireNameMgr"
)
s (Text
uid 533,0
va (VaSet
isHidden 1
)
xt "30000,28000,30000,28000"
blo "30000,28000"
tm "SignalTypeMgr"
)
)
on &81
)
*96 (Wire
uid 478,0
shape (OrthoPolyLine
uid 479,0
va (VaSet
vasetType 3
)
xt "6000,10000,20381,30000"
pts [
"6000,10000"
"6000,30000"
"20381,30000"
]
)
start &84
end &37
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 480,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 481,0
va (VaSet
)
xt "17381,28800,19581,30000"
st "eni"
blo "17381,29800"
tm "WireNameMgr"
)
)
on &4
)
*97 (Wire
uid 484,0
optionalChildren [
*98 (BdJunction
uid 494,0
ps "OnConnectorStrategy"
shape (Circle
uid 495,0
va (VaSet
vasetType 1
)
xt "15600,22600,16400,23400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 485,0
va (VaSet
vasetType 3
)
xt "16000,19000,56000,35000"
pts [
"56000,35000"
"56000,23000"
"16000,23000"
"16000,19000"
"20381,19000"
]
)
start &86
end &44
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 486,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 487,0
va (VaSet
)
xt "17381,17800,19281,19000"
st "Qi"
blo "17381,18800"
tm "WireNameMgr"
)
)
on &6
)
*99 (Wire
uid 490,0
shape (OrthoPolyLine
uid 491,0
va (VaSet
vasetType 3
)
xt "16000,23000,20382,26000"
pts [
"20382,26000"
"16000,26000"
"16000,23000"
]
)
start &38
end &98
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 492,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 493,0
va (VaSet
)
xt "17382,24800,19282,26000"
st "Qi"
blo "17382,25800"
tm "WireNameMgr"
)
)
on &6
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *100 (PackageList
uid 153,0
stg "VerticalLayoutStrategy"
textVec [
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uid 154,0
va (VaSet
font "Verdana,9,1"
)
xt "1000,-2400,8600,-1200"
st "Package List"
blo "1000,-1400"
)
*102 (MLText
uid 155,0
va (VaSet
)
xt "1000,-1200,20000,6000"
st "LIBRARY ieee;
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LIBRARY gates;
USE gates.gates.all;
USE ieee.NUMERIC_SIGNED.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 156,0
stg "VerticalLayoutStrategy"
textVec [
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uid 157,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,0,30800,1200"
st "Compiler Directives"
blo "20000,1000"
)
*104 (Text
uid 158,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,1200,33100,2400"
st "Pre-module directives:"
blo "20000,2200"
)
*105 (MLText
uid 159,0
va (VaSet
isHidden 1
)
xt "20000,2400,32100,4800"
st "`resetall
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tm "BdCompilerDirectivesTextMgr"
)
*106 (Text
uid 160,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,4800,33700,6000"
st "Post-module directives:"
blo "20000,5800"
)
*107 (MLText
uid 161,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*108 (Text
uid 162,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,6000,33200,7200"
st "End-module directives:"
blo "20000,7000"
)
*109 (MLText
uid 163,0
va (VaSet
isHidden 1
)
xt "20000,7200,20000,7200"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
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pageBreakOrigin "-7000,0"
lastUid 533,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "arial,8,0"
)
xt "500,2150,1400,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,9,1"
)
xt "1000,1000,5000,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*110 (Text
va (VaSet
font "Verdana,9,1"
)
xt "1300,3200,6700,4400"
st "<library>"
blo "1300,4200"
tm "BdLibraryNameMgr"
)
*111 (Text
va (VaSet
font "Verdana,9,1"
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dimension 50
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)
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dimension 100
uid 191,0
)
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pos 6
dimension 50
uid 192,0
)
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pos 7
dimension 80
uid 193,0
)
]
)
fixedCol 4
fixedRow 2
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vaOverrides [
]
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]
)
uid 165,0
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genericsCommonDM (CommonDM
ldm (LogicalDM
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*183 (TitleRowHdr
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*184 (FilterRowHdr
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tm "RefLabelColHdrMgr"
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*186 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*187 (GroupColHdr
tm "GroupColHdrMgr"
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*188 (NameColHdr
tm "GenericNameColHdrMgr"
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*189 (TypeColHdr
tm "GenericTypeColHdrMgr"
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*190 (InitColHdr
tm "GenericValueColHdrMgr"
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*191 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
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*192 (EolColHdr
tm "GenericEolColHdrMgr"
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]
)
pdm (PhysicalDM
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editShortBounds 1
uid 207,0
optionalChildren [
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sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
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groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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hidden 1
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uid 212,0
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sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
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litem &188
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uid 216,0
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litem &190
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litem &191
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uid 219,0
)
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pos 6
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uid 220,0
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)
fixedCol 3
fixedRow 2
name "Ports"
uid 208,0
vaOverrides [
]
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]
)
uid 194,0
type 1
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activeModelName "BlockDiag"
)
