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unitName "std_logic_1164"
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version "32.1"
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va (VaSet
font "Verdana,9,1"
)
xt "25600,17600,28100,18800"
st "U_0"
blo "25600,18600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 432,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 433,0
text (MLText
uid 434,0
va (VaSet
font "Courier New,8,0"
)
xt "25600,25200,25600,25200"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 435,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "24250,20250,25750,21750"
iconName "StateMachineViewIcon.png"
iconMaskName "StateMachineViewIcon.msk"
ftype 3
)
viewiconposition 0
)
*35 (Blk
uid 548,0
shape (Rectangle
uid 549,0
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "48000,14000,56000,24000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 550,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*36 (Text
uid 551,0
va (VaSet
font "Verdana,9,1"
)
xt "49600,17200,53300,18400"
st "Cursor"
blo "49600,18200"
tm "BdLibraryNameMgr"
)
*37 (Text
uid 552,0
va (VaSet
font "Verdana,9,1"
)
xt "49600,18400,52800,19600"
st "PWM"
blo "49600,19400"
tm "BlkNameMgr"
)
*38 (Text
uid 553,0
va (VaSet
font "Verdana,9,1"
)
xt "49600,19600,52100,20800"
st "U_4"
blo "49600,20600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 554,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 555,0
text (MLText
uid 556,0
va (VaSet
font "Courier New,8,0"
)
xt "49600,27200,49600,27200"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 557,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "48250,22250,49750,23750"
iconName "StateMachineViewIcon.png"
iconMaskName "StateMachineViewIcon.msk"
ftype 3
)
viewiconposition 0
)
*39 (Net
uid 574,0
decl (Decl
n "countOut"
t "std_ulogic_vector"
b "(7 DOWNTO 0)"
o 12
suid 19,0
)
declText (MLText
uid 575,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
)
)
*40 (SaComponent
uid 744,0
optionalChildren [
*41 (CptPort
uid 724,0
ps "OnEdgeStrategy"
shape (Triangle
uid 725,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "21250,36625,22000,37375"
)
tg (CPTG
uid 726,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 727,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,36300,26800,37700"
st "clock"
blo "23000,37500"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*42 (CptPort
uid 728,0
ps "OnEdgeStrategy"
shape (Triangle
uid 729,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38000,32625,38750,33375"
)
tg (CPTG
uid 730,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 731,0
va (VaSet
font "Verdana,12,0"
)
xt "30400,32300,37000,33700"
st "countOut"
ju 2
blo "37000,33500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "countOut"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*43 (CptPort
uid 732,0
ps "OnEdgeStrategy"
shape (Triangle
uid 733,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "21250,38625,22000,39375"
)
tg (CPTG
uid 734,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 735,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,38300,27100,39700"
st "reset"
blo "23000,39500"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*44 (CptPort
uid 736,0
ps "OnEdgeStrategy"
shape (Triangle
uid 737,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "21250,32625,22000,33375"
)
tg (CPTG
uid 738,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 739,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,32300,28100,33700"
st "enable"
blo "23000,33500"
)
)
thePort (LogicalPort
decl (Decl
n "enable"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*45 (CptPort
uid 740,0
ps "OnEdgeStrategy"
shape (Triangle
uid 741,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "21250,30625,22000,31375"
)
tg (CPTG
uid 742,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 743,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,30300,30000,31700"
st "resetSync"
blo "23000,31500"
)
)
thePort (LogicalPort
decl (Decl
n "resetSync"
t "std_ulogic"
o 5
suid 2005,0
)
)
)
]
shape (Rectangle
uid 745,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "22000,27000,38000,41000"
)
oxt "30000,9000,46000,23000"
ttg (MlTextGroup
uid 746,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*46 (Text
uid 747,0
va (VaSet
)
xt "22300,41400,28900,42600"
st "sequential"
blo "22300,42400"
tm "BdLibraryNameMgr"
)
*47 (Text
uid 748,0
va (VaSet
)
xt "22300,42600,37000,43800"
st "counterEnableResetSync"
blo "22300,43600"
tm "CptNameMgr"
)
*48 (Text
uid 749,0
va (VaSet
)
xt "22300,43800,25100,45000"
st "U_1"
blo "22300,44800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 750,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 751,0
text (MLText
uid 752,0
va (VaSet
)
xt "22000,45400,39800,47800"
st "bitNb = 8            ( positive )  
delay = gateDelay    ( time     )  "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "8"
)
(GiElement
name "delay"
type "time"
value "gateDelay"
)
]
)
viewicon (ZoomableIcon
uid 753,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "22250,39250,23750,40750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*49 (Net
uid 764,0
decl (Decl
n "enable"
t "std_ulogic"
o 10
suid 25,0
)
declText (MLText
uid 765,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
)
)
*50 (Net
uid 772,0
decl (Decl
n "resetSync"
t "std_ulogic"
o 11
suid 26,0
)
declText (MLText
uid 773,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
)
)
*51 (SaComponent
uid 840,0
optionalChildren [
*52 (CptPort
uid 836,0
ps "OnEdgeStrategy"
shape (Triangle
uid 837,0
ro 180
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "82625,13000,83375,13750"
)
tg (CPTG
uid 838,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 839,0
va (VaSet
isHidden 1
)
xt "84000,12000,88400,13200"
st "logic_1"
blo "84000,13000"
)
s (Text
uid 850,0
va (VaSet
)
xt "84000,13200,84000,13200"
blo "84000,13200"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "logic_1"
t "std_uLogic"
o 1
suid 2,0
)
)
)
]
shape (Pu
uid 841,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "80000,7000,85000,13000"
)
showPorts 0
oxt "34000,15000,39000,21000"
ttg (MlTextGroup
uid 842,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*53 (Text
uid 843,0
va (VaSet
font "Verdana,8,1"
)
xt "79910,10700,83010,11700"
st "gates"
blo "79910,11500"
tm "BdLibraryNameMgr"
)
*54 (Text
uid 844,0
va (VaSet
font "Verdana,8,1"
)
xt "79910,11700,83410,12700"
st "logic1"
blo "79910,12500"
tm "CptNameMgr"
)
*55 (Text
uid 845,0
va (VaSet
font "Verdana,8,1"
)
xt "79910,12700,82410,13700"
st "U_2"
blo "79910,13500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 846,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 847,0
text (MLText
uid 848,0
va (VaSet
font "Verdana,8,0"
)
xt "80000,15600,80000,15600"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 849,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "80250,11250,81750,12750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*56 (Wire
uid 15,0
optionalChildren [
*57 (BdJunction
uid 564,0
ps "OnConnectorStrategy"
shape (Circle
uid 565,0
va (VaSet
vasetType 1
)
xt "5600,36600,6400,37400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 16,0
va (VaSet
vasetType 3
)
xt "5000,37000,21250,37000"
pts [
"5000,37000"
"21250,37000"
]
)
start &1
end &41
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 19,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20,0
va (VaSet
isHidden 1
)
xt "7000,35800,10400,37000"
st "clock"
blo "7000,36800"
tm "WireNameMgr"
)
)
on &2
)
*58 (Wire
uid 29,0
shape (OrthoPolyLine
uid 30,0
va (VaSet
vasetType 3
)
xt "83000,13000,97000,21000"
pts [
"97000,21000"
"83000,21000"
"83000,13000"
]
)
start &3
end &52
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 33,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 34,0
va (VaSet
isHidden 1
)
xt "96000,19800,101100,21000"
st "motorOn"
blo "96000,20800"
tm "WireNameMgr"
)
)
on &4
)
*59 (Wire
uid 43,0
optionalChildren [
*60 (BdJunction
uid 857,0
ps "OnConnectorStrategy"
shape (Circle
uid 858,0
va (VaSet
vasetType 1
)
xt "44600,7600,45400,8400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 44,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "28000,7000,48000,16000"
pts [
"28000,7000"
"45000,7000"
"45000,16000"
"48000,16000"
]
)
start &5
end &35
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 47,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 48,0
va (VaSet
isHidden 1
)
xt "30000,5800,33700,7000"
st "Power"
blo "30000,6800"
tm "WireNameMgr"
)
)
on &6
)
*61 (Wire
uid 57,0
optionalChildren [
*62 (BdJunction
uid 572,0
ps "OnConnectorStrategy"
shape (Circle
uid 573,0
va (VaSet
vasetType 1
)
xt "6600,38600,7400,39400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 58,0
va (VaSet
vasetType 3
)
xt "5000,39000,21250,39000"
pts [
"5000,39000"
"21250,39000"
]
)
start &7
end &43
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 61,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 62,0
va (VaSet
isHidden 1
)
xt "7000,37800,10300,39000"
st "reset"
blo "7000,38800"
tm "WireNameMgr"
)
)
on &8
)
*63 (Wire
uid 71,0
shape (OrthoPolyLine
uid 72,0
va (VaSet
vasetType 3
)
xt "78000,37000,93000,37000"
pts [
"93000,37000"
"78000,37000"
]
)
start &9
end &26
sat 32
eat 2
st 0
sf 1
si 0
tg (WTG
uid 75,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 76,0
va (VaSet
isHidden 1
)
xt "92000,35800,95500,37000"
st "side1"
blo "92000,36800"
tm "WireNameMgr"
)
)
on &10
)
*64 (Wire
uid 85,0
shape (OrthoPolyLine
uid 86,0
va (VaSet
vasetType 3
)
xt "78000,41000,93000,41000"
pts [
"93000,41000"
"78000,41000"
]
)
start &11
end &26
sat 32
eat 2
st 0
sf 1
si 0
tg (WTG
uid 89,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 90,0
va (VaSet
isHidden 1
)
xt "92000,39800,95500,41000"
st "side2"
blo "92000,40800"
tm "WireNameMgr"
)
)
on &12
)
*65 (Wire
uid 99,0
shape (OrthoPolyLine
uid 100,0
va (VaSet
vasetType 3
)
xt "56000,38000,70000,38000"
pts [
"56000,38000"
"70000,38000"
]
)
start &13
end &26
sat 32
eat 1
st 0
sf 1
si 0
tg (WTG
uid 103,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 104,0
va (VaSet
isHidden 1
)
xt "58000,36800,61500,38000"
st "SideL"
blo "58000,37800"
tm "WireNameMgr"
)
)
on &14
)
*66 (Wire
uid 406,0
shape (OrthoPolyLine
uid 407,0
va (VaSet
vasetType 3
)
xt "56000,22000,70000,36000"
pts [
"56000,22000"
"64000,22000"
"64000,36000"
"70000,36000"
]
)
start &35
end &26
sat 2
eat 1
st 0
sf 1
si 0
tg (WTG
uid 412,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 413,0
va (VaSet
)
xt "58000,20800,63400,22000"
st "PWM_out"
blo "58000,21800"
tm "WireNameMgr"
)
)
on &30
)
*67 (Wire
uid 558,0
shape (OrthoPolyLine
uid 559,0
va (VaSet
vasetType 3
)
xt "6000,15000,24000,37000"
pts [
"6000,37000"
"6000,15000"
"24000,15000"
]
)
start &57
end &31
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 562,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 563,0
va (VaSet
)
xt "20000,13800,23400,15000"
st "clock"
blo "20000,14800"
tm "WireNameMgr"
)
)
on &2
)
*68 (Wire
uid 566,0
shape (OrthoPolyLine
uid 567,0
va (VaSet
vasetType 3
)
xt "7000,13000,24000,39000"
pts [
"7000,39000"
"7000,13000"
"24000,13000"
]
)
start &62
end &31
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 570,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 571,0
va (VaSet
)
xt "20000,11800,23300,13000"
st "reset"
blo "20000,12800"
tm "WireNameMgr"
)
)
on &8
)
*69 (Wire
uid 582,0
shape (OrthoPolyLine
uid 583,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "37000,17000,44000,22000"
pts [
"44000,22000"
"42000,22000"
"42000,17000"
"37000,17000"
]
)
start *70 (BdJunction
uid 762,0
ps "OnConnectorStrategy"
shape (Circle
uid 763,0
va (VaSet
vasetType 1
)
xt "43600,21600,44400,22400"
radius 400
)
)
end &31
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 586,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 587,0
va (VaSet
)
xt "39000,15800,44400,17000"
st "countOut"
blo "39000,16800"
tm "WireNameMgr"
)
)
on &39
)
*71 (Wire
uid 592,0
shape (OrthoPolyLine
uid 593,0
va (VaSet
vasetType 3
)
xt "51000,10000,51000,14000"
pts [
"51000,10000"
"51000,14000"
]
)
end &35
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 598,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 599,0
ro 270
va (VaSet
)
xt "49800,11500,51000,14900"
st "clock"
blo "50800,14900"
tm "WireNameMgr"
)
)
on &2
)
*72 (Wire
uid 602,0
shape (OrthoPolyLine
uid 603,0
va (VaSet
vasetType 3
)
xt "53000,10000,53000,14000"
pts [
"53000,10000"
"53000,14000"
]
)
end &35
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 608,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 609,0
ro 270
va (VaSet
)
xt "51800,11600,53000,14900"
st "reset"
blo "52800,14900"
tm "WireNameMgr"
)
)
on &8
)
*73 (Wire
uid 612,0
shape (OrthoPolyLine
uid 613,0
va (VaSet
vasetType 3
)
xt "73000,29000,73000,34000"
pts [
"73000,29000"
"73000,34000"
]
)
end &26
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 618,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 619,0
ro 270
va (VaSet
)
xt "71800,30500,73000,33900"
st "clock"
blo "72800,33900"
tm "WireNameMgr"
)
)
on &2
)
*74 (Wire
uid 622,0
shape (OrthoPolyLine
uid 623,0
va (VaSet
vasetType 3
)
xt "76000,29000,76000,34000"
pts [
"76000,29000"
"76000,34000"
]
)
end &26
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 628,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 629,0
ro 270
va (VaSet
)
xt "74800,30600,76000,33900"
st "reset"
blo "75800,33900"
tm "WireNameMgr"
)
)
on &8
)
*75 (Wire
uid 756,0
optionalChildren [
&70
]
shape (OrthoPolyLine
uid 757,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "38750,22000,48000,33000"
pts [
"38750,33000"
"44000,33000"
"44000,22000"
"48000,22000"
]
)
start &42
end &35
sat 32
eat 1
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 760,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 761,0
va (VaSet
)
xt "40750,31800,46150,33000"
st "countOut"
blo "40750,32800"
tm "WireNameMgr"
)
)
on &39
)
*76 (Wire
uid 766,0
shape (OrthoPolyLine
uid 767,0
va (VaSet
vasetType 3
)
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