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n "ramDataValid"
t "std_ulogic"
o 14
suid 21,0
)
)
)
*130 (CptPort
uid 297,0
ps "OnEdgeStrategy"
shape (Triangle
uid 298,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41250,5625,42000,6375"
)
tg (CPTG
uid 299,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 300,0
va (VaSet
)
xt "43000,5500,46300,6500"
st "ramAddr"
blo "43000,6300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 301,0
va (VaSet
font "courier,8,0"
)
xt "0,14200,30500,15100"
st "ramAddr        : IN     unsigned (addressBitNb-1 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "ramAddr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 3
suid 22,0
)
)
)
*131 (CptPort
uid 302,0
ps "OnEdgeStrategy"
shape (Triangle
uid 303,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,5625,58750,6375"
)
tg (CPTG
uid 304,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 305,0
va (VaSet
)
xt "51800,5500,57000,6500"
st "memAddress"
ju 2
blo "57000,6300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 306,0
va (VaSet
font "courier,8,0"
)
xt "0,19600,38000,20500"
st "memAddress     : OUT    std_ulogic_vector ( chipAddressBitNb-1 DOWNTO 0 ) ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "memAddress"
t "std_ulogic_vector"
b "( chipAddressBitNb-1 DOWNTO 0 )"
o 9
suid 23,0
)
)
)
*132 (CptPort
uid 307,0
ps "OnEdgeStrategy"
shape (Triangle
uid 308,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41250,9625,42000,10375"
)
tg (CPTG
uid 309,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 310,0
va (VaSet
)
xt "43000,9500,47900,10500"
st "ramDataOut"
blo "43000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 311,0
va (VaSet
font "courier,8,0"
)
xt "0,15100,33500,16000"
st "ramDataOut     : IN     std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "ramDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 24,0
)
)
)
*133 (CptPort
uid 312,0
ps "OnEdgeStrategy"
shape (Triangle
uid 313,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,9625,58750,10375"
)
tg (CPTG
uid 314,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 315,0
va (VaSet
)
xt "52800,9500,57000,10500"
st "memDataIn"
ju 2
blo "57000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 316,0
va (VaSet
font "courier,8,0"
)
xt "0,13300,33500,14200"
st "memDataIn      : IN     std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 25,0
)
)
)
*134 (CptPort
uid 317,0
ps "OnEdgeStrategy"
shape (Triangle
uid 318,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,11625,58750,12375"
)
tg (CPTG
uid 319,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 320,0
va (VaSet
)
xt "51800,11500,57000,12500"
st "memDataOut"
ju 2
blo "57000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 321,0
va (VaSet
font "courier,8,0"
)
xt "0,21400,33500,22300"
st "memDataOut     : OUT    std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "memDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 11
suid 26,0
)
)
)
*135 (CptPort
uid 322,0
ps "OnEdgeStrategy"
shape (Triangle
uid 323,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,19625,58750,20375"
)
tg (CPTG
uid 324,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 325,0
va (VaSet
)
xt "53200,19500,57000,20500"
st "memWr_n"
ju 2
blo "57000,20300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 326,0
va (VaSet
font "courier,8,0"
)
xt "0,22300,19000,23200"
st "memWr_n        : OUT    std_ulogic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr_n"
t "std_ulogic"
o 12
suid 27,0
)
)
)
*136 (CptPort
uid 327,0
ps "OnEdgeStrategy"
shape (Triangle
uid 328,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41250,27625,42000,28375"
)
tg (CPTG
uid 329,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 330,0
va (VaSet
)
xt "43000,27500,45600,28500"
st "ramEn"
blo "43000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 331,0
va (VaSet
font "courier,8,0"
)
xt "0,16000,19000,16900"
st "ramEn          : IN     std_ulogic  ;"
)
thePort (LogicalPort
decl (Decl
n "ramEn"
t "std_ulogic"
o 5
suid 28,0
)
)
)
*137 (CptPort
uid 332,0
ps "OnEdgeStrategy"
shape (Triangle
uid 333,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41250,11625,42000,12375"
)
tg (CPTG
uid 334,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 335,0
va (VaSet
)
xt "43000,11500,45700,12500"
st "ramRd"
blo "43000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 336,0
va (VaSet
font "courier,8,0"
)
xt "0,16900,19000,17800"
st "ramRd          : IN     std_ulogic  ;"
)
thePort (LogicalPort
decl (Decl
n "ramRd"
t "std_ulogic"
o 6
suid 29,0
)
)
)
*138 (CptPort
uid 337,0
ps "OnEdgeStrategy"
shape (Triangle
uid 338,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41250,13625,42000,14375"
)
tg (CPTG
uid 339,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 340,0
va (VaSet
)
xt "43000,13500,45700,14500"
st "ramWr"
blo "43000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 341,0
va (VaSet
font "courier,8,0"
)
xt "0,17800,19000,18700"
st "ramWr          : IN     std_ulogic  ;"
)
thePort (LogicalPort
decl (Decl
n "ramWr"
t "std_ulogic"
o 7
suid 30,0
)
)
)
*139 (CptPort
uid 342,0
ps "OnEdgeStrategy"
shape (Triangle
uid 343,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41250,31625,42000,32375"
)
tg (CPTG
uid 344,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 345,0
va (VaSet
)
xt "43000,31500,45100,32500"
st "reset"
blo "43000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 346,0
va (VaSet
font "courier,8,0"
)
xt "0,18700,19000,19600"
st "reset          : IN     std_ulogic  ;"
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 8
suid 31,0
)
)
)
*140 (CptPort
uid 347,0
ps "OnEdgeStrategy"
shape (Triangle
uid 348,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,17625,58750,18375"
)
tg (CPTG
uid 349,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 350,0
va (VaSet
)
xt "53600,17500,57000,18500"
st "sdCas_n"
ju 2
blo "57000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 351,0
va (VaSet
font "courier,8,0"
)
xt "0,25000,19000,25900"
st "sdCas_n        : OUT    std_ulogic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "sdCas_n"
t "std_ulogic"
o 15
suid 32,0
)
)
)
*141 (CptPort
uid 352,0
ps "OnEdgeStrategy"
shape (Triangle
uid 353,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,23625,58750,24375"
)
tg (CPTG
uid 354,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 355,0
va (VaSet
)
xt "54500,23500,57000,24500"
st "sdCke"
ju 2
blo "57000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 356,0
va (VaSet
font "courier,8,0"
)
xt "0,25900,19000,26800"
st "sdCke          : OUT    std_ulogic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "sdCke"
t "std_ulogic"
o 16
suid 33,0
)
)
)
*142 (CptPort
uid 357,0
ps "OnEdgeStrategy"
shape (Triangle
uid 358,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,25625,58750,26375"
)
tg (CPTG
uid 359,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 360,0
va (VaSet
)
xt "54700,25500,57000,26500"
st "sdClk"
ju 2
blo "57000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 361,0
va (VaSet
font "courier,8,0"
)
xt "0,26800,19000,27700"
st "sdClk          : OUT    std_ulogic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "sdClk"
t "std_ulogic"
o 17
suid 34,0
)
)
)
*143 (CptPort
uid 362,0
ps "OnEdgeStrategy"
shape (Triangle
uid 363,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,13625,58750,14375"
)
tg (CPTG
uid 364,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 365,0
va (VaSet
)
xt "54000,13500,57000,14500"
st "sdCs_n"
ju 2
blo "57000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 366,0
va (VaSet
font "courier,8,0"
)
xt "0,27700,19000,28600"
st "sdCs_n         : OUT    std_ulogic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "sdCs_n"
t "std_ulogic"
o 18
suid 35,0
)
)
)
*144 (CptPort
uid 367,0
ps "OnEdgeStrategy"
shape (Triangle
uid 368,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,21625,58750,22375"
)
tg (CPTG
uid 369,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 370,0
va (VaSet
)
xt "54100,21500,57000,22500"
st "sdDqm"
ju 2
blo "57000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 371,0
va (VaSet
font "courier,8,0"
)
xt "0,28600,28500,29500"
st "sdDqm          : OUT    std_ulogic_vector (1 DOWNTO 0) ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "sdDqm"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 19
suid 36,0
)
)
)
*145 (CptPort
uid 377,0
ps "OnEdgeStrategy"
shape (Triangle
uid 378,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,15625,58750,16375"
)
tg (CPTG
uid 379,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 380,0
va (VaSet
)
xt "53600,15500,57000,16500"
st "sdRas_n"
ju 2
blo "57000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 381,0
va (VaSet
font "courier,8,0"
)
xt "0,29500,19000,30400"
st "sdRas_n        : OUT    std_ulogic  ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "sdRas_n"
t "std_ulogic"
o 20
suid 38,0
)
)
)
*146 (CptPort
uid 487,0
ps "OnEdgeStrategy"
shape (Triangle
uid 518,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41250,7625,42000,8375"
)
tg (CPTG
uid 489,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 490,0
va (VaSet
)
xt "43000,7500,46900,8500"
st "ramDataIn"
blo "43000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 491,0
va (VaSet
font "courier,8,0"
)
xt "0,23200,33500,24100"
st "ramDataIn      : OUT    std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "ramDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 13
suid 42,0
)
)
)
*147 (CptPort
uid 548,0
ps "OnEdgeStrategy"
shape (Triangle
uid 549,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,7625,58750,8375"
)
tg (CPTG
uid 550,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 551,0
va (VaSet
)
xt "50200,7500,57000,8500"
st "memBankAddress"
ju 2
blo "57000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 552,0
va (VaSet
font "courier,8,0"
)
xt "0,20500,40000,21400"
st "memBankAddress : OUT    std_ulogic_vector ( chipBankAddressBitNb-1 DOWNTO 0 ) ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "memBankAddress"
t "std_ulogic_vector"
b "( chipBankAddressBitNb-1 DOWNTO 0 )"
o 10
suid 43,0
)
)
)
*148 (CptPort
uid 651,0
ps "OnEdgeStrategy"
shape (Triangle
uid 652,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58000,29625,58750,30375"
)
tg (CPTG
uid 653,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 654,0
va (VaSet
)
xt "51500,29500,57000,30500"
st "selectRefresh"
ju 2
blo "57000,30300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 655,0
va (VaSet
font "courier,8,0"
)
xt "0,30400,18000,31300"
st "selectRefresh  : OUT    std_ulogic "
)
thePort (LogicalPort
m 1
decl (Decl
n "selectRefresh"
t "std_ulogic"
o 21
suid 44,0
)
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "42000,2000,58000,34000"
)
oxt "15000,6000,31000,34000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "courier,8,1"
)
xt "42550,34500,45550,35400"
st "Memory"
blo "42550,35200"
)
second (Text
uid 12,0
va (VaSet
font "courier,8,1"
)
xt "42550,35400,50550,36300"
st "sdramController"
blo "42550,36100"
)
)
gi *149 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "courier,8,0"
)
xt "42000,38200,77500,55300"
st "Generic Declarations

addressBitNb               positive 24                                
dataBitNb                  positive 16                                
chipAddressBitNb           positive 12                                
chipBankAddressBitNb       positive 2                                 
rowAddressBitNb            positive 12                                
colAddressBitNb            positive 9                                 
activeToReadPeriodNb       positive 2    --66MHz * 20ns = 1.32        
activeToWritePeriodNb      positive 2    --66MHz * 20ns = 1.32        
loadModeToActivePeriodNb   positive 1    --1 CK                       
prechargeToRefreshPeriodNb positive 2    --66MHz * 20 ns = 1.32       
readToActivePeriodNb       positive 3    --1 CK + 66MHz * 20ns = 2.32 
readToSamplePeriodNb       positive 2    --2 CK with latency = 2      
refreshDelayPeriodNb       positive 5    --66MHz * 66ns = 4.356       
writeToActivePeriodNb      positive 3    --1 CK + 66MHz * 20ns = 2.32 
delayCounterbitNb          positive 13   --66MHz * 100us = 6600 < 8K  
refreshPeriodNb            positive 1031 --66MHz * 64ms / 4096        
maxDelayPeriodNb           positive 5    --66MHz*66ns = 4.356         "
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "24"
)
(GiElement
name "dataBitNb"
type "positive"
value "16"
)
(GiElement
name "chipAddressBitNb"
type "positive"
value "12"
)
(GiElement
name "chipBankAddressBitNb"
type "positive"
value "2"
)
(GiElement
name "rowAddressBitNb"
type "positive"
value "12"
)
(GiElement
name "colAddressBitNb"
type "positive"
value "9"
)
(GiElement
name "activeToReadPeriodNb"
type "positive"
value "2"
e "66MHz * 20ns = 1.32"
)
(GiElement
name "activeToWritePeriodNb"
type "positive"
value "2"
e "66MHz * 20ns = 1.32"
)
(GiElement
name "loadModeToActivePeriodNb"
type "positive"
value "1"
e "1 CK"
)
(GiElement
name "prechargeToRefreshPeriodNb"
type "positive"
value "2"
e "66MHz * 20 ns = 1.32"
)
(GiElement
name "readToActivePeriodNb"
type "positive"
value "3"
e "1 CK + 66MHz * 20ns = 2.32"
)
(GiElement
name "readToSamplePeriodNb"
type "positive"
value "2"
e "2 CK with latency = 2"
)
(GiElement
name "refreshDelayPeriodNb"
type "positive"
value "5"
e "66MHz * 66ns = 4.356"
)
(GiElement
name "writeToActivePeriodNb"
type "positive"
value "3"
e "1 CK + 66MHz * 20ns = 2.32"
)
(GiElement
name "delayCounterbitNb"
type "positive"
value "13"
e "66MHz * 100us = 6600 < 8K"
)
(GiElement
name "refreshPeriodNb"
type "positive"
value "1031"
e "66MHz * 64ms / 4096"
)
(GiElement
name "maxDelayPeriodNb"
type "positive"
value "5"
e "66MHz*66ns = 4.356"
)
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sTC 0
sF 0
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portVis (PortSigDisplay
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sF 0
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optionalChildren [
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xt "34000,48000,51000,49000"
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oxt "18000,70000,35000,71000"
text (MLText
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xt "34200,48000,49200,49000"
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
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position 1
ignorePrefs 1
titleBlock 1
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xt "51200,44000,54800,45000"
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Project:
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
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position 1
ignorePrefs 1
titleBlock 1
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text (MLText
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