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19 lines
343 B
VHDL
19 lines
343 B
VHDL
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ARCHITECTURE RTL OF counter IS
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signal count: unsigned(countOut'range);
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BEGIN
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countEndlessly: process(reset, clock)
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begin
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if reset = '1' then
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count <= (others => '0');
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elsif rising_edge(clock) then
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count <= count+1;
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end if;
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end process countEndlessly;
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countOut <= count after delay;
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END ARCHITECTURE RTL;
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