mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-23 09:53:29 +00:00
1542 lines
19 KiB
Plaintext
1542 lines
19 KiB
Plaintext
|
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
suid 2004,0
|
||
|
usingSuid 1
|
||
|
emptyRow *1 (LEmptyRow
|
||
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)
|
||
|
uid 145,0
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||
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optionalChildren [
|
||
|
*2 (LogPort
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||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "in1"
|
||
|
t "std_ulogic"
|
||
|
o 1
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||
|
suid 1,0
|
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|
)
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||
|
)
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||
|
uid 146,0
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||
|
)
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||
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*3 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "in3"
|
||
|
t "std_ulogic"
|
||
|
o 1
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||
|
suid 3,0
|
||
|
)
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||
|
)
|
||
|
uid 147,0
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||
|
)
|
||
|
*4 (LogPort
|
||
|
port (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "xorOut"
|
||
|
t "std_ulogic"
|
||
|
o 1
|
||
|
suid 4,0
|
||
|
)
|
||
|
)
|
||
|
uid 148,0
|
||
|
)
|
||
|
*5 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "in2"
|
||
|
t "std_ulogic"
|
||
|
o 1
|
||
|
suid 2,0
|
||
|
)
|
||
|
)
|
||
|
uid 149,0
|
||
|
)
|
||
|
*6 (RefLabelRowHdr
|
||
|
)
|
||
|
*7 (TitleRowHdr
|
||
|
)
|
||
|
*8 (FilterRowHdr
|
||
|
)
|
||
|
*9 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*10 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*11 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*12 (NameColHdr
|
||
|
tm "NameColHdrMgr"
|
||
|
)
|
||
|
*13 (ModeColHdr
|
||
|
tm "ModeColHdrMgr"
|
||
|
)
|
||
|
*14 (TypeColHdr
|
||
|
tm "TypeColHdrMgr"
|
||
|
)
|
||
|
*15 (BoundsColHdr
|
||
|
tm "BoundsColHdrMgr"
|
||
|
)
|
||
|
*16 (InitColHdr
|
||
|
tm "InitColHdrMgr"
|
||
|
)
|
||
|
*17 (EolColHdr
|
||
|
tm "EolColHdrMgr"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
uid 150,0
|
||
|
optionalChildren [
|
||
|
*18 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
emptyMRCItem *19 (MRCItem
|
||
|
litem &1
|
||
|
pos 4
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 87,0
|
||
|
optionalChildren [
|
||
|
*20 (MRCItem
|
||
|
litem &6
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 90,0
|
||
|
)
|
||
|
*21 (MRCItem
|
||
|
litem &7
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 92,0
|
||
|
)
|
||
|
*22 (MRCItem
|
||
|
litem &8
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 94,0
|
||
|
)
|
||
|
*23 (MRCItem
|
||
|
litem &2
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 113,0
|
||
|
)
|
||
|
*24 (MRCItem
|
||
|
litem &3
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
uid 114,0
|
||
|
)
|
||
|
*25 (MRCItem
|
||
|
litem &4
|
||
|
pos 3
|
||
|
dimension 20
|
||
|
uid 115,0
|
||
|
)
|
||
|
*26 (MRCItem
|
||
|
litem &5
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 116,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 88,0
|
||
|
optionalChildren [
|
||
|
*27 (MRCItem
|
||
|
litem &9
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 96,0
|
||
|
)
|
||
|
*28 (MRCItem
|
||
|
litem &11
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 100,0
|
||
|
)
|
||
|
*29 (MRCItem
|
||
|
litem &12
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 102,0
|
||
|
)
|
||
|
*30 (MRCItem
|
||
|
litem &13
|
||
|
pos 3
|
||
|
dimension 50
|
||
|
uid 104,0
|
||
|
)
|
||
|
*31 (MRCItem
|
||
|
litem &14
|
||
|
pos 4
|
||
|
dimension 100
|
||
|
uid 106,0
|
||
|
)
|
||
|
*32 (MRCItem
|
||
|
litem &15
|
||
|
pos 5
|
||
|
dimension 100
|
||
|
uid 108,0
|
||
|
)
|
||
|
*33 (MRCItem
|
||
|
litem &16
|
||
|
pos 6
|
||
|
dimension 50
|
||
|
uid 110,0
|
||
|
)
|
||
|
*34 (MRCItem
|
||
|
litem &17
|
||
|
pos 7
|
||
|
dimension 80
|
||
|
uid 112,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 86,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 144,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *35 (LEmptyRow
|
||
|
)
|
||
|
uid 152,0
|
||
|
optionalChildren [
|
||
|
*36 (RefLabelRowHdr
|
||
|
)
|
||
|
*37 (TitleRowHdr
|
||
|
)
|
||
|
*38 (FilterRowHdr
|
||
|
)
|
||
|
*39 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*40 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*41 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*42 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*43 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*44 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*45 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*46 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
*47 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "delay"
|
||
|
type "time"
|
||
|
value "gateDelay"
|
||
|
)
|
||
|
uid 142,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
uid 153,0
|
||
|
optionalChildren [
|
||
|
*48 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
emptyMRCItem *49 (MRCItem
|
||
|
litem &35
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 118,0
|
||
|
optionalChildren [
|
||
|
*50 (MRCItem
|
||
|
litem &36
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 121,0
|
||
|
)
|
||
|
*51 (MRCItem
|
||
|
litem &37
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 123,0
|
||
|
)
|
||
|
*52 (MRCItem
|
||
|
litem &38
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 125,0
|
||
|
)
|
||
|
*53 (MRCItem
|
||
|
litem &47
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 143,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 119,0
|
||
|
optionalChildren [
|
||
|
*54 (MRCItem
|
||
|
litem &39
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 127,0
|
||
|
)
|
||
|
*55 (MRCItem
|
||
|
litem &41
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 131,0
|
||
|
)
|
||
|
*56 (MRCItem
|
||
|
litem &42
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 133,0
|
||
|
)
|
||
|
*57 (MRCItem
|
||
|
litem &43
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 135,0
|
||
|
)
|
||
|
*58 (MRCItem
|
||
|
litem &44
|
||
|
pos 4
|
||
|
dimension 50
|
||
|
uid 137,0
|
||
|
)
|
||
|
*59 (MRCItem
|
||
|
litem &45
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 139,0
|
||
|
)
|
||
|
*60 (MRCItem
|
||
|
litem &46
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 141,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 117,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 151,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor3\\symbol.sb.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor3\\symbol.sb.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "concatenated"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_%(view)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor3"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor3"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "11.09.2019"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "Wed"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "Wednesday"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "11"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "xor3"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_author"
|
||
|
value "silvan.zahno"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_date"
|
||
|
value "11.09.2019"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_host"
|
||
|
value "WE6996"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_time"
|
||
|
value "14:35:03"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "WE6996"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "gates"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/ElN/Libraries/Gates/work"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "09"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "xor3"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "Sep"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "September"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor3\\symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor3\\symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_DesignCompilerPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEPath"
|
||
|
value "D:\\Labs\\ElN\\Board\\Board\\ise"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_LeonardoPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ModelSimPath"
|
||
|
value "c:\\eda\\modelsim\\win32"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_NC-SimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_PrecisionRTLPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_QuestaSimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_VCSPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_ext"
|
||
|
value "sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file_logical"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "time"
|
||
|
value "14:35:03"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "unit"
|
||
|
value "xor3"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "silvan.zahno"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2018.1 (Build 12)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2019"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "yy"
|
||
|
value "19"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
LanguageMgr "Vhdl2008LangMgr"
|
||
|
uid 51,0
|
||
|
optionalChildren [
|
||
|
*61 (SymbolBody
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||
|
uid 8,0
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||
|
optionalChildren [
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|
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||
|
uid 52,0
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||
|
ps "OnEdgeStrategy"
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shape (Triangle
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||
|
uid 53,0
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||
|
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||
|
va (VaSet
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||
|
vasetType 1
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||
|
fg "0,65535,0"
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||
|
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||
|
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||
|
)
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||
|
tg (CPTG
|
||
|
uid 54,0
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ps "CptPortTextPlaceStrategy"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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|
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||
|
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|
||
|
)
|
||
|
)
|
||
|
*63 (CptPort
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||
|
uid 57,0
|
||
|
ps "OnEdgeStrategy"
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||
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uid 58,0
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||
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|
va (VaSet
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vasetType 1
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fg "0,65535,0"
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||
|
)
|
||
|
tg (CPTG
|
||
|
uid 59,0
|
||
|
ps "CptPortTextPlaceStrategy"
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|
stg "VerticalLayoutStrategy"
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uid 60,0
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va (VaSet
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st "in2"
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|
blo "34888,16350"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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thePort (LogicalPort
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|
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|
n "in2"
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*64 (CptPort
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uid 62,0
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ps "OnEdgeStrategy"
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uid 63,0
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|
va (VaSet
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vasetType 1
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fg "0,65535,0"
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|
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|
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|
||
|
tg (CPTG
|
||
|
uid 64,0
|
||
|
ps "CptPortTextPlaceStrategy"
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|
stg "VerticalLayoutStrategy"
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uid 65,0
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|
va (VaSet
|
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|
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||
|
st "in3"
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|
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|
tm "CptPortNameMgr"
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va (VaSet
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|
st "in3 : IN std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "in3"
|
||
|
t "std_ulogic"
|
||
|
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|
||
|
suid 3,0
|
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|
)
|
||
|
)
|
||
|
)
|
||
|
*65 (CptPort
|
||
|
uid 67,0
|
||
|
ps "OnEdgeStrategy"
|
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|
shape (Triangle
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||
|
uid 68,0
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||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
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|
fg "0,65535,0"
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|
)
|
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|
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|
)
|
||
|
tg (CPTG
|
||
|
uid 69,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
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||
|
f (Text
|
||
|
uid 70,0
|
||
|
va (VaSet
|
||
|
isHidden 1
|
||
|
)
|
||
|
xt "38400,15700,41000,16700"
|
||
|
st "xorOut"
|
||
|
ju 2
|
||
|
blo "41000,16500"
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||
|
tm "CptPortNameMgr"
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|
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dt (MLText
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uid 71,0
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|
va (VaSet
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|
font "Verdana,8,0"
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|
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||
|
st "xorOut : OUT std_ulogic "
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "xorOut"
|
||
|
t "std_ulogic"
|
||
|
o 1
|
||
|
suid 4,0
|
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|
)
|
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|
)
|
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|
)
|
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|
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shape (XOr
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uid 83,0
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va (VaSet
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fg "0,65535,0"
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oxt "15000,6000,51000,26000"
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biTextGroup (BiTextGroup
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uid 10,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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first (Text
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|
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|
gi *66 (GenericInterface
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|
uid 13,0
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|
ps "CenterOffsetStrategy"
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|
matrix (Matrix
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text (MLText
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|
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||
|
|
||
|
delay time gateDelay "
|
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|
)
|
||
|
header "Generic Declarations"
|
||
|
showHdrWhenContentsEmpty 1
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|
)
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|
elements [
|
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|
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|
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|
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|
type "time"
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|
value "gateDelay"
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|
)
|
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|
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|
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|
portInstanceVis (PortSigDisplay
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|
sN 0
|
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|
sT 1
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|
)
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portVis (PortSigDisplay
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|
sN 0
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|
)
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|
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*67 (Grouping
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|
uid 177,0
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