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https://github.com/Klagarge/Cursor.git
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89 lines
3.2 KiB
VHDL
89 lines
3.2 KiB
VHDL
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LIBRARY BoardTester_test;
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USE BoardTester_test.testUtils.all;
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ARCHITECTURE test OF flashController_tester IS
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constant clockFrequency: real := 66.0E6;
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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signal flashAddr_int: natural := 0;
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signal flashDataOut_int: natural := 0;
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signal refreshEn: std_uLogic := '0';
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constant separator : string(1 to 80) := (others => '-');
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constant indent : string(1 to 2) := (others => ' ');
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- flash access
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process
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begin
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flashRd <= '0';
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flashWr <= '0';
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flashEn <= '1';
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wait for 1 us;
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print(cr & separator);
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-- erase block 0
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print(sprintf("%tu", now) & ": Erasing block 0");
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flashAddr_int <= 16#10000#;
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flashDataOut_int <= 16#0020#;
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flashWr <= '1', '0' after clockPeriod;
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wait until falling_edge(flashDataValid);
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wait for clockPeriod/10;
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flashDataOut_int <= 16#00D0#;
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flashWr <= '1', '0' after clockPeriod;
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wait for 2 us;
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-- program word
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print(sprintf("%tu", now) & ": Writing data into Flash");
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flashAddr_int <= 16#0000#;
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flashDataOut_int <= 16#0040#;
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flashWr <= '1', '0' after clockPeriod;
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wait until falling_edge(flashDataValid);
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wait for clockPeriod/10;
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flashAddr_int <= 16#0010#;
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flashDataOut_int <= 16#CAFE#;
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flashWr <= '1', '0' after clockPeriod;
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wait for 2 us;
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-- read word
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print(sprintf("%tu", now) & ": Reading data from Flash");
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flashAddr_int <= 16#0000#;
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flashRd <= '1', '0' after clockPeriod;
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wait for 1 us;
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-- read word
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print(sprintf("%tu", now) & ": Reading data from Flash");
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flashAddr_int <= 16#000F#;
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flashRd <= '1', '0' after clockPeriod;
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wait for 500 ns;
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flashAddr_int <= 16#0010#;
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flashRd <= '1', '0' after clockPeriod;
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wait for 500 ns;
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flashAddr_int <= 16#0011#;
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flashRd <= '1', '0' after clockPeriod;
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wait for 500 ns;
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wait;
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end process;
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------------------------------------------------------------------------------
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-- address and data
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flashAddr <= to_unsigned(flashAddr_int, flashAddr'length);
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flashDataOut <= std_ulogic_vector(to_unsigned(flashDataOut_int, flashDataOut'length));
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------------------------------------------------------------------------------
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-- memory bus hold
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refreshEn <= '1' after 15*clockPeriod when refreshEn = '0'
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else '0' after clockPeriod;
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memBusEn_n <= refreshEn;
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END ARCHITECTURE test;
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