mirror of
https://github.com/Klagarge/Cursor.git
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2449 lines
30 KiB
Plaintext
2449 lines
30 KiB
Plaintext
|
DocumentHdrVersion "1.1"
|
||
|
Header (DocumentHdr
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|
version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
|
||
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library "std"
|
||
|
unitName "textio"
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||
|
)
|
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(DmPackageRef
|
||
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library "ieee"
|
||
|
unitName "std_logic_1164"
|
||
|
)
|
||
|
(DmPackageRef
|
||
|
library "ieee"
|
||
|
unitName "NUMERIC_STD"
|
||
|
)
|
||
|
(DmPackageRef
|
||
|
library "memory_test"
|
||
|
unitName "mti_pkg"
|
||
|
)
|
||
|
]
|
||
|
libraryRefs [
|
||
|
"STD"
|
||
|
"ieee"
|
||
|
"memory_test"
|
||
|
]
|
||
|
)
|
||
|
version "26.1"
|
||
|
appVersion "2018.1 (Build 12)"
|
||
|
model (Symbol
|
||
|
commonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
suid 32,0
|
||
|
usingSuid 1
|
||
|
emptyRow *1 (LEmptyRow
|
||
|
)
|
||
|
uid 74,0
|
||
|
optionalChildren [
|
||
|
*2 (RefLabelRowHdr
|
||
|
)
|
||
|
*3 (TitleRowHdr
|
||
|
)
|
||
|
*4 (FilterRowHdr
|
||
|
)
|
||
|
*5 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*6 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*7 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*8 (NameColHdr
|
||
|
tm "NameColHdrMgr"
|
||
|
)
|
||
|
*9 (ModeColHdr
|
||
|
tm "ModeColHdrMgr"
|
||
|
)
|
||
|
*10 (TypeColHdr
|
||
|
tm "TypeColHdrMgr"
|
||
|
)
|
||
|
*11 (BoundsColHdr
|
||
|
tm "BoundsColHdrMgr"
|
||
|
)
|
||
|
*12 (InitColHdr
|
||
|
tm "InitColHdrMgr"
|
||
|
)
|
||
|
*13 (EolColHdr
|
||
|
tm "EolColHdrMgr"
|
||
|
)
|
||
|
*14 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "addr"
|
||
|
t "std_ulogic_vector"
|
||
|
b "( addr_bits-1 DOWNTO 0 )"
|
||
|
o 9
|
||
|
suid 22,0
|
||
|
)
|
||
|
)
|
||
|
uid 379,0
|
||
|
)
|
||
|
*15 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "Ba"
|
||
|
t "std_ulogic_vector"
|
||
|
b "(1 DOWNTO 0)"
|
||
|
o 1
|
||
|
suid 23,0
|
||
|
i "\"00\""
|
||
|
)
|
||
|
)
|
||
|
uid 381,0
|
||
|
)
|
||
|
*16 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "Cas_n"
|
||
|
t "std_ulogic"
|
||
|
o 2
|
||
|
suid 24,0
|
||
|
)
|
||
|
)
|
||
|
uid 383,0
|
||
|
)
|
||
|
*17 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "Cke"
|
||
|
t "std_ulogic"
|
||
|
o 3
|
||
|
suid 25,0
|
||
|
)
|
||
|
)
|
||
|
uid 385,0
|
||
|
)
|
||
|
*18 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "Clk"
|
||
|
t "std_ulogic"
|
||
|
o 4
|
||
|
suid 26,0
|
||
|
)
|
||
|
)
|
||
|
uid 387,0
|
||
|
)
|
||
|
*19 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "Cs_n"
|
||
|
t "std_ulogic"
|
||
|
o 5
|
||
|
suid 27,0
|
||
|
)
|
||
|
)
|
||
|
uid 389,0
|
||
|
)
|
||
|
*20 (LogPort
|
||
|
port (LogicalPort
|
||
|
m 2
|
||
|
decl (Decl
|
||
|
n "Dq"
|
||
|
t "std_logic_vector"
|
||
|
b "( data_bits-1 DOWNTO 0 )"
|
||
|
o 10
|
||
|
suid 28,0
|
||
|
)
|
||
|
)
|
||
|
uid 391,0
|
||
|
)
|
||
|
*21 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "Dqm"
|
||
|
t "std_ulogic_vector"
|
||
|
b "( 1 DOWNTO 0 )"
|
||
|
o 6
|
||
|
suid 29,0
|
||
|
i "\"00\""
|
||
|
)
|
||
|
)
|
||
|
uid 393,0
|
||
|
)
|
||
|
*22 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "Ras_n"
|
||
|
t "std_ulogic"
|
||
|
o 7
|
||
|
suid 31,0
|
||
|
)
|
||
|
)
|
||
|
uid 397,0
|
||
|
)
|
||
|
*23 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "WE_n"
|
||
|
t "std_ulogic"
|
||
|
o 8
|
||
|
suid 32,0
|
||
|
)
|
||
|
)
|
||
|
uid 399,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 87,0
|
||
|
optionalChildren [
|
||
|
*24 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
emptyMRCItem *25 (MRCItem
|
||
|
litem &1
|
||
|
pos 10
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 89,0
|
||
|
optionalChildren [
|
||
|
*26 (MRCItem
|
||
|
litem &2
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 90,0
|
||
|
)
|
||
|
*27 (MRCItem
|
||
|
litem &3
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 91,0
|
||
|
)
|
||
|
*28 (MRCItem
|
||
|
litem &4
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 92,0
|
||
|
)
|
||
|
*29 (MRCItem
|
||
|
litem &14
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 380,0
|
||
|
)
|
||
|
*30 (MRCItem
|
||
|
litem &15
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 382,0
|
||
|
)
|
||
|
*31 (MRCItem
|
||
|
litem &16
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
uid 384,0
|
||
|
)
|
||
|
*32 (MRCItem
|
||
|
litem &17
|
||
|
pos 3
|
||
|
dimension 20
|
||
|
uid 386,0
|
||
|
)
|
||
|
*33 (MRCItem
|
||
|
litem &18
|
||
|
pos 4
|
||
|
dimension 20
|
||
|
uid 388,0
|
||
|
)
|
||
|
*34 (MRCItem
|
||
|
litem &19
|
||
|
pos 5
|
||
|
dimension 20
|
||
|
uid 390,0
|
||
|
)
|
||
|
*35 (MRCItem
|
||
|
litem &20
|
||
|
pos 6
|
||
|
dimension 20
|
||
|
uid 392,0
|
||
|
)
|
||
|
*36 (MRCItem
|
||
|
litem &21
|
||
|
pos 7
|
||
|
dimension 20
|
||
|
uid 394,0
|
||
|
)
|
||
|
*37 (MRCItem
|
||
|
litem &22
|
||
|
pos 8
|
||
|
dimension 20
|
||
|
uid 398,0
|
||
|
)
|
||
|
*38 (MRCItem
|
||
|
litem &23
|
||
|
pos 9
|
||
|
dimension 20
|
||
|
uid 400,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 93,0
|
||
|
optionalChildren [
|
||
|
*39 (MRCItem
|
||
|
litem &5
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 94,0
|
||
|
)
|
||
|
*40 (MRCItem
|
||
|
litem &7
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 95,0
|
||
|
)
|
||
|
*41 (MRCItem
|
||
|
litem &8
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 96,0
|
||
|
)
|
||
|
*42 (MRCItem
|
||
|
litem &9
|
||
|
pos 3
|
||
|
dimension 50
|
||
|
uid 97,0
|
||
|
)
|
||
|
*43 (MRCItem
|
||
|
litem &10
|
||
|
pos 4
|
||
|
dimension 100
|
||
|
uid 98,0
|
||
|
)
|
||
|
*44 (MRCItem
|
||
|
litem &11
|
||
|
pos 5
|
||
|
dimension 100
|
||
|
uid 99,0
|
||
|
)
|
||
|
*45 (MRCItem
|
||
|
litem &12
|
||
|
pos 6
|
||
|
dimension 50
|
||
|
uid 100,0
|
||
|
)
|
||
|
*46 (MRCItem
|
||
|
litem &13
|
||
|
pos 7
|
||
|
dimension 80
|
||
|
uid 101,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 88,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 73,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *47 (LEmptyRow
|
||
|
)
|
||
|
uid 103,0
|
||
|
optionalChildren [
|
||
|
*48 (RefLabelRowHdr
|
||
|
)
|
||
|
*49 (TitleRowHdr
|
||
|
)
|
||
|
*50 (FilterRowHdr
|
||
|
)
|
||
|
*51 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*52 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*53 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*54 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*55 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*56 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*57 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*58 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
*59 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "addr_bits"
|
||
|
type "integer"
|
||
|
value "13"
|
||
|
)
|
||
|
uid 447,0
|
||
|
)
|
||
|
*60 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "data_bits"
|
||
|
type "integer"
|
||
|
value "16"
|
||
|
)
|
||
|
uid 449,0
|
||
|
)
|
||
|
*61 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "col_bits"
|
||
|
type "integer"
|
||
|
value "9"
|
||
|
)
|
||
|
uid 451,0
|
||
|
)
|
||
|
*62 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "index"
|
||
|
type "integer"
|
||
|
value "0"
|
||
|
)
|
||
|
uid 453,0
|
||
|
)
|
||
|
*63 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "fname"
|
||
|
type "string"
|
||
|
value "\"sdram.srec\""
|
||
|
)
|
||
|
uid 455,0
|
||
|
)
|
||
|
*64 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tAC"
|
||
|
type "time"
|
||
|
value "6 ns"
|
||
|
)
|
||
|
uid 457,0
|
||
|
)
|
||
|
*65 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tHZ"
|
||
|
type "time"
|
||
|
value "7 ns"
|
||
|
)
|
||
|
uid 459,0
|
||
|
)
|
||
|
*66 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tOH"
|
||
|
type "time"
|
||
|
value "2.7 ns"
|
||
|
)
|
||
|
uid 461,0
|
||
|
)
|
||
|
*67 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tMRD"
|
||
|
type "integer"
|
||
|
value "2"
|
||
|
)
|
||
|
uid 463,0
|
||
|
)
|
||
|
*68 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tRAS"
|
||
|
type "time"
|
||
|
value "44 ns"
|
||
|
)
|
||
|
uid 465,0
|
||
|
)
|
||
|
*69 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tRC"
|
||
|
type "time"
|
||
|
value "66 ns"
|
||
|
)
|
||
|
uid 467,0
|
||
|
)
|
||
|
*70 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tRCD"
|
||
|
type "time"
|
||
|
value "20 ns"
|
||
|
)
|
||
|
uid 469,0
|
||
|
)
|
||
|
*71 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tRP"
|
||
|
type "time"
|
||
|
value "20 ns"
|
||
|
)
|
||
|
uid 471,0
|
||
|
)
|
||
|
*72 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tRRD"
|
||
|
type "time"
|
||
|
value "15 ns"
|
||
|
)
|
||
|
uid 473,0
|
||
|
)
|
||
|
*73 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tWRa"
|
||
|
type "time"
|
||
|
value "7.5 ns"
|
||
|
)
|
||
|
uid 475,0
|
||
|
)
|
||
|
*74 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tWRp"
|
||
|
type "time"
|
||
|
value "15 ns"
|
||
|
)
|
||
|
uid 477,0
|
||
|
)
|
||
|
*75 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tAH"
|
||
|
type "time"
|
||
|
value "0.8 ns"
|
||
|
)
|
||
|
uid 479,0
|
||
|
)
|
||
|
*76 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tAS"
|
||
|
type "time"
|
||
|
value "1.5 ns"
|
||
|
)
|
||
|
uid 481,0
|
||
|
)
|
||
|
*77 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tCH"
|
||
|
type "time"
|
||
|
value "2.5 ns"
|
||
|
)
|
||
|
uid 483,0
|
||
|
)
|
||
|
*78 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tCL"
|
||
|
type "time"
|
||
|
value "2.5 ns"
|
||
|
)
|
||
|
uid 485,0
|
||
|
)
|
||
|
*79 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tCK"
|
||
|
type "time"
|
||
|
value "10 ns"
|
||
|
)
|
||
|
uid 487,0
|
||
|
)
|
||
|
*80 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tDH"
|
||
|
type "time"
|
||
|
value "0.8 ns"
|
||
|
)
|
||
|
uid 489,0
|
||
|
)
|
||
|
*81 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tDS"
|
||
|
type "time"
|
||
|
value "1.5 ns"
|
||
|
)
|
||
|
uid 491,0
|
||
|
)
|
||
|
*82 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tCKH"
|
||
|
type "time"
|
||
|
value "0.8 ns"
|
||
|
)
|
||
|
uid 493,0
|
||
|
)
|
||
|
*83 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tCKS"
|
||
|
type "time"
|
||
|
value "1.5 ns"
|
||
|
)
|
||
|
uid 495,0
|
||
|
)
|
||
|
*84 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tCMH"
|
||
|
type "time"
|
||
|
value "0.8 ns"
|
||
|
)
|
||
|
uid 497,0
|
||
|
)
|
||
|
*85 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "tCMS"
|
||
|
type "time"
|
||
|
value "1.5 ns"
|
||
|
)
|
||
|
uid 499,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 115,0
|
||
|
optionalChildren [
|
||
|
*86 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
emptyMRCItem *87 (MRCItem
|
||
|
litem &47
|
||
|
pos 27
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 117,0
|
||
|
optionalChildren [
|
||
|
*88 (MRCItem
|
||
|
litem &48
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 118,0
|
||
|
)
|
||
|
*89 (MRCItem
|
||
|
litem &49
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 119,0
|
||
|
)
|
||
|
*90 (MRCItem
|
||
|
litem &50
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 120,0
|
||
|
)
|
||
|
*91 (MRCItem
|
||
|
litem &59
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 448,0
|
||
|
)
|
||
|
*92 (MRCItem
|
||
|
litem &60
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 450,0
|
||
|
)
|
||
|
*93 (MRCItem
|
||
|
litem &61
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
uid 452,0
|
||
|
)
|
||
|
*94 (MRCItem
|
||
|
litem &62
|
||
|
pos 3
|
||
|
dimension 20
|
||
|
uid 454,0
|
||
|
)
|
||
|
*95 (MRCItem
|
||
|
litem &63
|
||
|
pos 4
|
||
|
dimension 20
|
||
|
uid 456,0
|
||
|
)
|
||
|
*96 (MRCItem
|
||
|
litem &64
|
||
|
pos 5
|
||
|
dimension 20
|
||
|
uid 458,0
|
||
|
)
|
||
|
*97 (MRCItem
|
||
|
litem &65
|
||
|
pos 6
|
||
|
dimension 20
|
||
|
uid 460,0
|
||
|
)
|
||
|
*98 (MRCItem
|
||
|
litem &66
|
||
|
pos 7
|
||
|
dimension 20
|
||
|
uid 462,0
|
||
|
)
|
||
|
*99 (MRCItem
|
||
|
litem &67
|
||
|
pos 8
|
||
|
dimension 20
|
||
|
uid 464,0
|
||
|
)
|
||
|
*100 (MRCItem
|
||
|
litem &68
|
||
|
pos 9
|
||
|
dimension 20
|
||
|
uid 466,0
|
||
|
)
|
||
|
*101 (MRCItem
|
||
|
litem &69
|
||
|
pos 10
|
||
|
dimension 20
|
||
|
uid 468,0
|
||
|
)
|
||
|
*102 (MRCItem
|
||
|
litem &70
|
||
|
pos 11
|
||
|
dimension 20
|
||
|
uid 470,0
|
||
|
)
|
||
|
*103 (MRCItem
|
||
|
litem &71
|
||
|
pos 12
|
||
|
dimension 20
|
||
|
uid 472,0
|
||
|
)
|
||
|
*104 (MRCItem
|
||
|
litem &72
|
||
|
pos 13
|
||
|
dimension 20
|
||
|
uid 474,0
|
||
|
)
|
||
|
*105 (MRCItem
|
||
|
litem &73
|
||
|
pos 14
|
||
|
dimension 20
|
||
|
uid 476,0
|
||
|
)
|
||
|
*106 (MRCItem
|
||
|
litem &74
|
||
|
pos 15
|
||
|
dimension 20
|
||
|
uid 478,0
|
||
|
)
|
||
|
*107 (MRCItem
|
||
|
litem &75
|
||
|
pos 16
|
||
|
dimension 20
|
||
|
uid 480,0
|
||
|
)
|
||
|
*108 (MRCItem
|
||
|
litem &76
|
||
|
pos 17
|
||
|
dimension 20
|
||
|
uid 482,0
|
||
|
)
|
||
|
*109 (MRCItem
|
||
|
litem &77
|
||
|
pos 18
|
||
|
dimension 20
|
||
|
uid 484,0
|
||
|
)
|
||
|
*110 (MRCItem
|
||
|
litem &78
|
||
|
pos 19
|
||
|
dimension 20
|
||
|
uid 486,0
|
||
|
)
|
||
|
*111 (MRCItem
|
||
|
litem &79
|
||
|
pos 20
|
||
|
dimension 20
|
||
|
uid 488,0
|
||
|
)
|
||
|
*112 (MRCItem
|
||
|
litem &80
|
||
|
pos 21
|
||
|
dimension 20
|
||
|
uid 490,0
|
||
|
)
|
||
|
*113 (MRCItem
|
||
|
litem &81
|
||
|
pos 22
|
||
|
dimension 20
|
||
|
uid 492,0
|
||
|
)
|
||
|
*114 (MRCItem
|
||
|
litem &82
|
||
|
pos 23
|
||
|
dimension 20
|
||
|
uid 494,0
|
||
|
)
|
||
|
*115 (MRCItem
|
||
|
litem &83
|
||
|
pos 24
|
||
|
dimension 20
|
||
|
uid 496,0
|
||
|
)
|
||
|
*116 (MRCItem
|
||
|
litem &84
|
||
|
pos 25
|
||
|
dimension 20
|
||
|
uid 498,0
|
||
|
)
|
||
|
*117 (MRCItem
|
||
|
litem &85
|
||
|
pos 26
|
||
|
dimension 20
|
||
|
uid 500,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 121,0
|
||
|
optionalChildren [
|
||
|
*118 (MRCItem
|
||
|
litem &51
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 122,0
|
||
|
)
|
||
|
*119 (MRCItem
|
||
|
litem &53
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 123,0
|
||
|
)
|
||
|
*120 (MRCItem
|
||
|
litem &54
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 124,0
|
||
|
)
|
||
|
*121 (MRCItem
|
||
|
litem &55
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 125,0
|
||
|
)
|
||
|
*122 (MRCItem
|
||
|
litem &56
|
||
|
pos 4
|
||
|
dimension 166
|
||
|
uid 126,0
|
||
|
)
|
||
|
*123 (MRCItem
|
||
|
litem &57
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 127,0
|
||
|
)
|
||
|
*124 (MRCItem
|
||
|
litem &58
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 128,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 116,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 102,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/sdram_mt48lc16m16a2/symbol.sb.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/sdram_mt48lc16m16a2/symbol.sb.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "concatenated"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_%(view)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/sdram_mt48lc16m16a2"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/sdram_mt48lc16m16a2"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "08/28/19"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "Wed"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "Wednesday"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "28"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "sdram_mt48lc16m16a2"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_author"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_date"
|
||
|
value "08/28/19"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_group"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_host"
|
||
|
value "Aphelia"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_time"
|
||
|
value "13:45:34"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "Aphelia"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "Memory_test"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/Libs/Memory_test/work"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "08"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "sdram_mt48lc16m16a2"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "Aug"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "August"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/sdram_mt48lc16m16a2/symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/sdram_mt48lc16m16a2/symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_DesignCompilerPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEPath"
|
||
|
value "D:\\Labs\\ElN\\Board\\Board\\ise"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_LeonardoPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
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(vvPair
|
||
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variable "task_ModelSimPath"
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||
|
value "C:\\EDA\\Modelsim\\win32"
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||
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(vvPair
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variable "task_NC-SimPath"
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value "<TBD>"
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||
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(vvPair
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||
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variable "task_PrecisionRTLPath"
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||
|
value "<TBD>"
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||
|
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||
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(vvPair
|
||
|
variable "task_QuestaSimPath"
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||
|
value "<TBD>"
|
||
|
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||
|
(vvPair
|
||
|
variable "task_VCSPath"
|
||
|
value "<TBD>"
|
||
|
)
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||
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(vvPair
|
||
|
variable "this_ext"
|
||
|
value "sb"
|
||
|
)
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||
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(vvPair
|
||
|
variable "this_file"
|
||
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value "symbol"
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||
|
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||
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(vvPair
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||
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variable "this_file_logical"
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value "symbol"
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||
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variable "time"
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||
|
value "13:45:34"
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||
|
)
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||
|
(vvPair
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||
|
variable "unit"
|
||
|
value "sdram_mt48lc16m16a2"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2018.1 (Build 12)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2019"
|
||
|
)
|
||
|
(vvPair
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||
|
variable "yy"
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||
|
value "19"
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||
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||
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||
|
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uid 72,0
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ps "CptPortTextPlaceStrategy"
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decl (Decl
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uid 329,0
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ps "OnEdgeStrategy"
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blo "32000,13300"
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tm "CptPortNameMgr"
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dt (MLText
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uid 333,0
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thePort (LogicalPort
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suid 23,0
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*128 (CptPort
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uid 334,0
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ps "OnEdgeStrategy"
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uid 335,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "30250,18625,31000,19375"
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tg (CPTG
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uid 336,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 337,0
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va (VaSet
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xt "32000,18500,34600,19500"
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st "Cas_n"
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blo "32000,19300"
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tm "CptPortNameMgr"
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)
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dt (MLText
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uid 338,0
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va (VaSet
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font "courier,8,0"
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st "Cas_n : IN std_ulogic ;"
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thePort (LogicalPort
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decl (Decl
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n "Cas_n"
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t "std_ulogic"
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suid 24,0
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)
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*129 (CptPort
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uid 339,0
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ps "OnEdgeStrategy"
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uid 340,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "30250,24625,31000,25375"
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)
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tg (CPTG
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uid 341,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 342,0
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va (VaSet
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st "Cke"
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blo "32000,25300"
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tm "CptPortNameMgr"
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uid 343,0
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va (VaSet
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font "courier,8,0"
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st "Cke : IN std_ulogic ;"
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thePort (LogicalPort
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decl (Decl
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n "Cke"
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t "std_ulogic"
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suid 25,0
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*130 (CptPort
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uid 344,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 345,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
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uid 346,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 347,0
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va (VaSet
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st "Clk"
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blo "32000,27300"
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tm "CptPortNameMgr"
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dt (MLText
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uid 348,0
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va (VaSet
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st "Clk : IN std_ulogic ;"
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thePort (LogicalPort
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||
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decl (Decl
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n "Clk"
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t "std_ulogic"
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suid 26,0
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*131 (CptPort
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uid 349,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 350,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
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uid 351,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 352,0
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va (VaSet
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st "Cs_n"
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blo "32000,15300"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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decl (Decl
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n "Cs_n"
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uid 354,0
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ps "OnEdgeStrategy"
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uid 355,0
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uid 356,0
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ps "CptPortTextPlaceStrategy"
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uid 357,0
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va (VaSet
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tm "CptPortNameMgr"
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dt (MLText
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uid 358,0
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va (VaSet
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font "courier,8,0"
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thePort (LogicalPort
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||
|
m 2
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||
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decl (Decl
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|
n "Dq"
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t "std_logic_vector"
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*133 (CptPort
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uid 359,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 360,0
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ro 90
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va (VaSet
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fg "0,65535,0"
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tg (CPTG
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uid 361,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 362,0
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va (VaSet
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st "Dqm"
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blo "32000,23300"
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tm "CptPortNameMgr"
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dt (MLText
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uid 363,0
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va (VaSet
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font "courier,8,0"
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)
|
||
|
thePort (LogicalPort
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||
|
decl (Decl
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||
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n "Dqm"
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t "std_ulogic_vector"
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b "( 1 DOWNTO 0 )"
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||
|
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|
suid 29,0
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|
i "\"00\""
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|
)
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||
|
)
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||
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)
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|
*134 (CptPort
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||
|
uid 369,0
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||
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 370,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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|
)
|
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tg (CPTG
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||
|
uid 371,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 372,0
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va (VaSet
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)
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st "Ras_n"
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|
blo "32000,17300"
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|
tm "CptPortNameMgr"
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)
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)
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dt (MLText
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uid 373,0
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|
va (VaSet
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font "courier,8,0"
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|
)
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|
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||
|
st "Ras_n : IN std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "Ras_n"
|
||
|
t "std_ulogic"
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||
|
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|
||
|
suid 31,0
|
||
|
)
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||
|
)
|
||
|
)
|
||
|
*135 (CptPort
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||
|
uid 374,0
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||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
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||
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uid 375,0
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||
|
ro 90
|
||
|
va (VaSet
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||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "30250,20625,31000,21375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 376,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 377,0
|
||
|
va (VaSet
|
||
|
)
|
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|
xt "32000,20500,34400,21500"
|
||
|
st "WE_n"
|
||
|
blo "32000,21300"
|
||
|
tm "CptPortNameMgr"
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||
|
)
|
||
|
)
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||
|
dt (MLText
|
||
|
uid 378,0
|
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|
va (VaSet
|
||
|
font "courier,8,0"
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|
)
|
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|
xt "-4000,21500,10500,22400"
|
||
|
st "WE_n : IN std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "WE_n"
|
||
|
t "std_ulogic"
|
||
|
o 8
|
||
|
suid 32,0
|
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|
)
|
||
|
)
|
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|
)
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|
]
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shape (Rectangle
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