1
0
mirror of https://github.com/Klagarge/Cursor.git synced 2024-11-23 09:53:29 +00:00
Cursor/Libs/Sequential/hds/reg@latch/symbol.sb

1163 lines
14 KiB
Plaintext
Raw Normal View History

2021-11-24 09:50:51 +00:00
DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
(DmPackageRef
library "gates"
unitName "gates"
itemName "ALL"
)
]
libraryRefs [
"ieee"
"gates"
]
)
version "26.1"
appVersion "2018.1 (Build 12)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
suid 2003,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
uid 152,0
optionalChildren [
*2 (LogPort
port (LogicalPort
decl (Decl
n "load"
t "std_ulogic"
o 2
suid 2,0
)
)
uid 153,0
)
*3 (LogPort
port (LogicalPort
decl (Decl
n "dataIn"
t "signed"
b "(nbBits-1 DOWNTO 0)"
o 4
suid 3,0
)
)
uid 154,0
)
*4 (LogPort
port (LogicalPort
m 1
decl (Decl
n "dataOut"
t "signed"
b "(nbBits-1 DOWNTO 0)"
o 1
suid 1,0
)
)
uid 155,0
)
*5 (RefLabelRowHdr
)
*6 (TitleRowHdr
)
*7 (FilterRowHdr
)
*8 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*9 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*10 (GroupColHdr
tm "GroupColHdrMgr"
)
*11 (NameColHdr
tm "NameColHdrMgr"
)
*12 (ModeColHdr
tm "ModeColHdrMgr"
)
*13 (TypeColHdr
tm "TypeColHdrMgr"
)
*14 (BoundsColHdr
tm "BoundsColHdrMgr"
)
*15 (InitColHdr
tm "InitColHdrMgr"
)
*16 (EolColHdr
tm "EolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 156,0
optionalChildren [
*17 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *18 (MRCItem
litem &1
pos 3
dimension 20
)
uid 91,0
optionalChildren [
*19 (MRCItem
litem &5
pos 0
dimension 20
uid 94,0
)
*20 (MRCItem
litem &6
pos 1
dimension 23
uid 96,0
)
*21 (MRCItem
litem &7
pos 2
hidden 1
dimension 20
uid 98,0
)
*22 (MRCItem
litem &2
pos 0
dimension 20
uid 117,0
)
*23 (MRCItem
litem &3
pos 1
dimension 20
uid 118,0
)
*24 (MRCItem
litem &4
pos 2
dimension 20
uid 119,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
)
uid 92,0
optionalChildren [
*25 (MRCItem
litem &8
pos 0
dimension 20
uid 100,0
)
*26 (MRCItem
litem &10
pos 1
dimension 50
uid 104,0
)
*27 (MRCItem
litem &11
pos 2
dimension 100
uid 106,0
)
*28 (MRCItem
litem &12
pos 3
dimension 50
uid 108,0
)
*29 (MRCItem
litem &13
pos 4
dimension 100
uid 110,0
)
*30 (MRCItem
litem &14
pos 5
dimension 100
uid 112,0
)
*31 (MRCItem
litem &15
pos 6
dimension 50
uid 114,0
)
*32 (MRCItem
litem &16
pos 7
dimension 80
uid 116,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 90,0
vaOverrides [
]
)
]
)
uid 151,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *33 (LEmptyRow
)
uid 158,0
optionalChildren [
*34 (RefLabelRowHdr
)
*35 (TitleRowHdr
)
*36 (FilterRowHdr
)
*37 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*38 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*39 (GroupColHdr
tm "GroupColHdrMgr"
)
*40 (NameColHdr
tm "GenericNameColHdrMgr"
)
*41 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*42 (InitColHdr
tm "GenericValueColHdrMgr"
)
*43 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*44 (EolColHdr
tm "GenericEolColHdrMgr"
)
*45 (LogGeneric
generic (GiElement
name "delay"
type "time"
value "gateDelay"
)
uid 145,0
)
*46 (LogGeneric
generic (GiElement
name "nbBits"
type "positive"
value "4"
)
uid 146,0
)
]
)
pdm (PhysicalDM
uid 159,0
optionalChildren [
*47 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *48 (MRCItem
litem &33
pos 2
dimension 20
)
uid 121,0
optionalChildren [
*49 (MRCItem
litem &34
pos 0
dimension 20
uid 124,0
)
*50 (MRCItem
litem &35
pos 1
dimension 23
uid 126,0
)
*51 (MRCItem
litem &36
pos 2
hidden 1
dimension 20
uid 128,0
)
*52 (MRCItem
litem &45
pos 0
dimension 20
uid 147,0
)
*53 (MRCItem
litem &46
pos 1
dimension 20
uid 148,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
)
uid 122,0
optionalChildren [
*54 (MRCItem
litem &37
pos 0
dimension 20
uid 130,0
)
*55 (MRCItem
litem &39
pos 1
dimension 50
uid 134,0
)
*56 (MRCItem
litem &40
pos 2
dimension 100
uid 136,0
)
*57 (MRCItem
litem &41
pos 3
dimension 100
uid 138,0
)
*58 (MRCItem
litem &42
pos 4
dimension 50
uid 140,0
)
*59 (MRCItem
litem &43
pos 5
dimension 50
uid 142,0
)
*60 (MRCItem
litem &44
pos 6
dimension 80
uid 144,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 120,0
vaOverrides [
]
)
]
)
uid 157,0
type 1
)
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hdl"
)
(vvPair
variable "HDSDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds"
)
(vvPair
variable "SideDataDesignDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/reg@latch/symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/reg@latch/symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/reg@latch"
)
(vvPair
variable "d_logical"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/regLatch"
)
(vvPair
variable "date"
value "08/28/19"
)
(vvPair
variable "day"
value "Wed"
)
(vvPair
variable "day_long"
value "Wednesday"
)
(vvPair
variable "dd"
value "28"
)
(vvPair
variable "entity_name"
value "regLatch"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "graphical_source_author"
value "francois"
)
(vvPair
variable "graphical_source_date"
value "08/28/19"
)
(vvPair
variable "graphical_source_group"
value "francois"
)
(vvPair
variable "graphical_source_host"
value "Aphelia"
)
(vvPair
variable "graphical_source_time"
value "13:46:18"
)
(vvPair
variable "group"
value "francois"
)
(vvPair
variable "host"
value "Aphelia"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "sequential"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Libraries/sequential/work"
)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "regLatch"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/reg@latch/symbol.sb"
)
(vvPair
variable "p_logical"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Sequential/hds/regLatch/symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "13:46:18"
)
(vvPair
variable "unit"
value "regLatch"
)
(vvPair
variable "user"
value "francois"
)
(vvPair
variable "version"
value "2018.1 (Build 12)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2019"
)
(vvPair
variable "yy"
value "19"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 29,0
optionalChildren [
*61 (SymbolBody
uid 8,0
optionalChildren [
*62 (CptPort
uid 62,0
ps "OnEdgeStrategy"
shape (Triangle
uid 83,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39625,250,40375,1000"
)
tg (CPTG
uid 64,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 65,0
va (VaSet
font "courier,12,0"
)
xt "38000,1000,44000,2400"
st "dataOut"
blo "38000,2200"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 66,0
va (VaSet
)
xt "2000,11400,28400,12400"
st "dataOut : OUT signed (nbBits-1 DOWNTO 0)"
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "signed"
b "(nbBits-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*63 (CptPort
uid 68,0
ps "OnEdgeStrategy"
shape (Triangle
uid 69,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33250,3625,34000,4375"
)
tg (CPTG
uid 70,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 71,0
va (VaSet
font "courier,12,0"
)
xt "35000,3300,38500,4700"
st "load"
blo "35000,4500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 72,0
va (VaSet
)
xt "2000,10400,20600,11400"
st "load : IN std_ulogic ;"
)
thePort (LogicalPort
decl (Decl
n "load"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*64 (CptPort
uid 78,0
ps "OnEdgeStrategy"
shape (Triangle
uid 85,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "39625,7000,40375,7750"
)
tg (CPTG
uid 80,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 81,0
va (VaSet
font "courier,12,0"
)
xt "38000,5600,43000,7000"
st "dataIn"
blo "38000,6800"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 82,0
va (VaSet
)
xt "2000,9400,29600,10400"
st "dataIn : IN signed (nbBits-1 DOWNTO 0) ;"
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "signed"
b "(nbBits-1 DOWNTO 0)"
o 4
suid 3,0
)
)
)
]
shape (Rectangle
uid 67,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "34000,1000,46000,7000"
)
oxt "15000,18000,21000,24000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
)
xt "34910,7700,41510,8700"
st "sequential"
blo "34910,8500"
)
second (Text
uid 12,0
va (VaSet
)
xt "34910,8700,39710,9700"
st "regLatch"
blo "34910,9500"
)
)
gi *65 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
)
xt "35000,12200,51800,16200"
st "Generic Declarations
delay time gateDelay
nbBits positive 4 "
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
(GiElement
name "delay"
type "time"
value "gateDelay"
)
(GiElement
name "nbBits"
type "positive"
value "4"
)
]
)
portInstanceVis (PortSigDisplay
sT 1
sIVOD 1
)
portVis (PortSigDisplay
sTC 0
sF 0
)
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "65535,0,0"
)
packageList *66 (PackageList
uid 5,0
stg "VerticalLayoutStrategy"
textVec [
*67 (Text
uid 149,0
va (VaSet
font "courier,12,1"
)
xt "0,-2500,8800,-1000"
st "Package List"
blo "0,-1300"
)
*68 (MLText
uid 150,0
va (VaSet
font "courier,12,0"
)
xt "0,-1000,21700,5500"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY gates;
USE gates.gates.ALL;"
tm "PackageList"
)
]
)
windowSize "7,40,1032,788"
viewArea "-700,-6400,47917,28187"
cachedDiagramExtent "0,-2500,49800,17000"
hasePageBreakOrigin 1
pageBreakOrigin "0,-3000"
defaultCommentText (CommentText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,2600,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 14000
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "courier,8,0"
)
xt "450,2150,1450,3050"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "courier,10,1"
)
xt "1000,1000,5000,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
parentGraphicsRef (HdmGraphicsRef
libraryName ""
entityName ""
viewName ""
)
defaultSymbolBody (SymbolBody
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "15000,16000,43000,36000"
)
biTextGroup (BiTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "26910,24700,30410,25700"
st "<library>"
blo "26910,25500"
)
second (Text
va (VaSet
)
xt "26910,25700,29510,26700"
st "<cell>"
blo "26910,26500"
)
)
gi *69 (GenericInterface
ps "CenterOffsetStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "20000,5000,20000,5000"
)
header "Generic Declarations"
)
elements [
]
)
portInstanceVis (PortSigDisplay
sT 1
sIVOD 1
)
)
defaultCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "courier,8,0"
)
xt "0,750,1500,1650"
st "In0"
blo "0,1450"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "courier,8,0"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "In0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
defaultCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
bg "0,0,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "courier,8,0"
)
xt "0,750,3500,1650"
st "Buffer0"
blo "0,1450"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "courier,8,0"
)
)
thePort (LogicalPort
lang 11
m 3
decl (Decl
n "Buffer0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
DeclarativeBlock *70 (SymDeclBlock
uid 31,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "courier,10,1"
)
xt "0,7000,7400,8200"
st "Declarations"
blo "0,8000"
)
portLabel (Text
uid 2,0
va (VaSet
font "courier,10,1"
)
xt "0,8200,3500,9400"
st "Ports:"
blo "0,9200"
)
externalLabel (Text
uid 2,0
va (VaSet
font "courier,10,1"
)
xt "0,12400,3000,13400"
st "User:"
blo "0,13200"
)
internalLabel (Text
uid 2,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "0,15100,7800,16300"
st "Internal User:"
blo "0,16100"
)
externalText (MLText
uid 3,0
va (VaSet
font "courier,8,0"
)
xt "2000,13400,2000,13400"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
uid 4,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "2000,16800,2000,16800"
tm "SyDeclarativeTextMgr"
)
)
lastUid 182,0
)