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Cursor/Cursor_test/hds/pulse@width@modulator_tb/struct.bd

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DocumentHdrVersion "1.1"
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type "positive"
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2021-11-24 09:50:51 +00:00
decl (Decl
n "SideL"
t "std_ulogic"
o 2
)
)
)
]
shape (Rectangle
uid 3055,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "29000,15000,37000,29000"
)
oxt "15000,6000,23000,20000"
ttg (MlTextGroup
uid 3056,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*26 (Text
uid 3057,0
va (VaSet
font "Verdana,9,1"
)
xt "31150,20800,34850,22000"
st "Cursor"
blo "31150,21800"
tm "BdLibraryNameMgr"
)
*27 (Text
uid 3058,0
va (VaSet
font "Verdana,9,1"
)
xt "31150,22000,34750,23200"
st "Driver"
blo "31150,23000"
tm "CptNameMgr"
)
*28 (Text
uid 3059,0
va (VaSet
font "Verdana,9,1"
)
xt "31150,23200,32850,24400"
st "I3"
blo "31150,24200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3060,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3061,0
text (MLText
uid 3062,0
va (VaSet
font "Courier New,8,0"
)
xt "3500,18000,3500,18000"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*29 (SaComponent
uid 3223,0
optionalChildren [
*30 (CptPort
uid 3233,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3234,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "19250,-9375,20000,-8625"
)
tg (CPTG
uid 3235,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3236,0
va (VaSet
font "Verdana,12,0"
)
xt "21000,-9700,24800,-8300"
st "clock"
blo "21000,-8500"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
2021-11-24 09:50:51 +00:00
o 1
)
)
)
*31 (CptPort
uid 3237,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3238,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36000,-13375,36750,-12625"
)
tg (CPTG
uid 3239,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3240,0
va (VaSet
font "Verdana,12,0"
)
xt "28400,-13700,35000,-12300"
st "countOut"
ju 2
blo "35000,-12500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "countOut"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 2
)
)
)
*32 (CptPort
uid 3241,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3242,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "19250,-7375,20000,-6625"
)
tg (CPTG
uid 3243,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3244,0
va (VaSet
font "Verdana,12,0"
)
xt "21000,-7700,25100,-6300"
st "reset"
blo "21000,-6500"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*33 (CptPort
uid 3245,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3246,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "19250,-13375,20000,-12625"
)
tg (CPTG
uid 3247,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3248,0
va (VaSet
font "Verdana,12,0"
)
xt "21000,-13700,26100,-12300"
st "enable"
blo "21000,-12500"
)
)
thePort (LogicalPort
decl (Decl
n "enable"
t "std_ulogic"
o 4
)
)
)
*34 (CptPort
uid 3249,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3250,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "19250,-15375,20000,-14625"
)
tg (CPTG
uid 3251,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3252,0
va (VaSet
font "Verdana,12,0"
)
xt "21000,-15700,28000,-14300"
st "resetSync"
blo "21000,-14500"
)
)
thePort (LogicalPort
decl (Decl
n "resetSync"
t "std_ulogic"
o 5
)
)
)
]
shape (Rectangle
uid 3224,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "20000,-19000,36000,-5000"
)
oxt "30000,9000,46000,23000"
ttg (MlTextGroup
uid 3225,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*35 (Text
uid 3226,0
va (VaSet
)
xt "20300,-4600,26900,-3400"
st "sequential"
blo "20300,-3600"
tm "BdLibraryNameMgr"
)
*36 (Text
uid 3227,0
va (VaSet
)
xt "20300,-3400,35000,-2200"
st "counterEnableResetSync"
blo "20300,-2400"
tm "CptNameMgr"
)
*37 (Text
uid 3228,0
va (VaSet
)
xt "20300,-2200,23100,-1000"
st "U_1"
blo "20300,-1200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3229,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3230,0
text (MLText
uid 3231,0
va (VaSet
)
xt "20000,-600,37800,1800"
st "bitNb = 8 ( positive )
delay = gateDelay ( time ) "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "8"
)
(GiElement
name "delay"
type "time"
value "gateDelay"
)
]
)
viewicon (ZoomableIcon
uid 3232,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "20250,-6750,21750,-5250"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*38 (Blk
uid 3343,0
shape (Rectangle
uid 3344,0
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "21000,-34000,32000,-24000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 3345,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*39 (Text
uid 3346,0
va (VaSet
font "Verdana,12,1"
)
xt "21700,-31100,31300,-29700"
st "Cursor_test"
blo "21700,-29900"
tm "BdLibraryNameMgr"
)
*40 (Text
uid 3347,0
va (VaSet
font "Verdana,12,1"
)
xt "21700,-29700,28300,-28300"
st "pwmtest"
blo "21700,-28500"
tm "BlkNameMgr"
)
*41 (Text
uid 3348,0
va (VaSet
font "Verdana,12,1"
)
xt "21700,-28300,23200,-26900"
st "I0"
blo "21700,-27100"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3349,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3350,0
text (MLText
uid 3351,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "21700,-21100,21700,-21100"
)
header ""
)
elements [
]
)
)
*42 (Net
uid 3352,0
decl (Decl
n "resetSync"
t "std_ulogic"
o 8
suid 40,0
)
declText (MLText
uid 3353,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,16000,1200"
st "SIGNAL resetSync : std_ulogic
"
)
)
*43 (Net
uid 3360,0
decl (Decl
n "enable"
t "std_ulogic"
o 9
suid 41,0
)
declText (MLText
uid 3361,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,16000,1200"
st "SIGNAL enable : std_ulogic
"
)
)
*44 (Net
uid 3368,0
decl (Decl
n "countOut"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 10
suid 42,0
)
declText (MLText
uid 3369,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,24500,1200"
st "SIGNAL countOut : unsigned(bitNb-1 DOWNTO 0)
"
)
)
*45 (SaComponent
uid 3386,0
optionalChildren [
*46 (CptPort
uid 3382,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3383,0
ro 180
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "16625,19000,17375,19750"
)
tg (CPTG
uid 3384,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3385,0
va (VaSet
isHidden 1
)
xt "18000,18000,22400,19200"
st "logic_1"
blo "18000,19000"
)
s (Text
uid 3395,0
va (VaSet
)
xt "18000,19200,18000,19200"
blo "18000,19200"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "logic_1"
t "std_uLogic"
o 1
suid 2,0
)
)
)
]
shape (Pu
uid 3387,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "14000,13000,19000,19000"
)
showPorts 0
oxt "34000,15000,39000,21000"
ttg (MlTextGroup
uid 3388,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*47 (Text
uid 3389,0
va (VaSet
font "Verdana,8,1"
)
xt "13910,16700,17010,17700"
st "gates"
blo "13910,17500"
tm "BdLibraryNameMgr"
)
*48 (Text
uid 3390,0
va (VaSet
font "Verdana,8,1"
)
xt "13910,17700,17410,18700"
st "logic1"
blo "13910,18500"
tm "CptNameMgr"
)
*49 (Text
uid 3391,0
va (VaSet
font "Verdana,8,1"
)
xt "13910,18700,15510,19700"
st "I2"
blo "13910,19500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3392,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3393,0
text (MLText
uid 3394,0
va (VaSet
font "Verdana,8,0"
)
xt "14000,21600,14000,21600"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*50 (Net
uid 3396,0
lang 11
decl (Decl
n "SideL"
t "std_ulogic"
o 6
suid 43,0
)
declText (MLText
uid 3397,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,16000,1200"
st "SIGNAL SideL : std_ulogic
"
)
)
*51 (Net
uid 3416,0
lang 11
decl (Decl
n "clk"
t "unsigned"
o 7
suid 44,0
)
declText (MLText
uid 3417,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,15000,1200"
st "SIGNAL clk : unsigned
"
)
)
*52 (Net
uid 3426,0
lang 11
decl (Decl
n "rst"
t "unsigned"
o 8
suid 45,0
)
declText (MLText
uid 3427,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,15000,1200"
st "SIGNAL rst : unsigned
"
)
)
*53 (Wire
uid 1317,0
shape (OrthoPolyLine
uid 1318,0
va (VaSet
vasetType 3
)
xt "20000,27000,28250,43000"
pts [
"28250,27000"
"20000,27000"
"20000,43000"
]
)
start &22
end &14
ss 0
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1321,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1322,0
va (VaSet
font "Verdana,12,0"
)
xt "25000,25600,29100,27000"
st "reset"
blo "25000,26800"
tm "WireNameMgr"
)
)
on &1
)
*54 (Wire
uid 1327,0
shape (OrthoPolyLine
uid 1328,0
va (VaSet
vasetType 3
)
xt "18000,26000,28250,43000"
pts [
"28250,26000"
"18000,26000"
"18000,43000"
]
)
start &19
end &14
ss 0
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1331,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1332,0
va (VaSet
font "Verdana,12,0"
)
xt "25000,24600,28800,26000"
st "clock"
blo "25000,25800"
tm "WireNameMgr"
)
)
on &2
)
*55 (Wire
uid 3283,0
shape (OrthoPolyLine
uid 3284,0
2021-11-24 09:50:51 +00:00
va (VaSet
vasetType 3
2021-11-24 09:50:51 +00:00
)
xt "3000,-7000,19250,-7000"
pts [
"3000,-7000"
"19250,-7000"
]
2021-11-24 09:50:51 +00:00
)
end &32
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 3285,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
2021-11-24 09:50:51 +00:00
f (Text
uid 3286,0
2021-11-24 09:50:51 +00:00
va (VaSet
isHidden 1
2021-11-24 09:50:51 +00:00
)
xt "5000,-8200,8300,-7000"
st "reset"
blo "5000,-7200"
tm "WireNameMgr"
2021-11-24 09:50:51 +00:00
)
)
on &1
2021-11-24 09:50:51 +00:00
)
*56 (Wire
uid 3305,0
shape (OrthoPolyLine
uid 3306,0
2021-11-24 09:50:51 +00:00
va (VaSet
vasetType 3
2021-11-24 09:50:51 +00:00
)
xt "3000,-9000,19250,-9000"
pts [
"3000,-9000"
"19250,-9000"
]
2021-11-24 09:50:51 +00:00
)
end &30
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 3307,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
2021-11-24 09:50:51 +00:00
f (Text
uid 3308,0
2021-11-24 09:50:51 +00:00
va (VaSet
isHidden 1
2021-11-24 09:50:51 +00:00
)
xt "5000,-10200,8400,-9000"
st "clock"
blo "5000,-9200"
tm "WireNameMgr"
2021-11-24 09:50:51 +00:00
)
)
on &2
2021-11-24 09:50:51 +00:00
)
*57 (Wire
uid 3354,0
shape (OrthoPolyLine
uid 3355,0
2021-11-24 09:50:51 +00:00
va (VaSet
vasetType 3
2021-11-24 09:50:51 +00:00
)
xt "17000,-27000,21000,-15000"
pts [
"21000,-27000"
"17000,-27000"
"17000,-15000"
"19250,-15000"
]
2021-11-24 09:50:51 +00:00
)
start &38
end &34
sat 2
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3358,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3359,0
2021-11-24 09:50:51 +00:00
va (VaSet
font "Verdana,12,0"
2021-11-24 09:50:51 +00:00
)
xt "13000,-28400,20000,-27000"
st "resetSync"
blo "13000,-27200"
tm "WireNameMgr"
2021-11-24 09:50:51 +00:00
)
)
on &42
2021-11-24 09:50:51 +00:00
)
*58 (Wire
uid 3362,0
shape (OrthoPolyLine
uid 3363,0
2021-11-24 09:50:51 +00:00
va (VaSet
vasetType 3
2021-11-24 09:50:51 +00:00
)
xt "12000,-29000,21000,-13000"
pts [
"21000,-29000"
"12000,-29000"
"12000,-13000"
"19250,-13000"
2021-11-24 09:50:51 +00:00
]
)
start &38
end &33
sat 2
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3366,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3367,0
2021-11-24 09:50:51 +00:00
va (VaSet
font "Verdana,12,0"
2021-11-24 09:50:51 +00:00
)
xt "15000,-30400,20100,-29000"
st "enable"
blo "15000,-29200"
tm "WireNameMgr"
2021-11-24 09:50:51 +00:00
)
)
on &43
2021-11-24 09:50:51 +00:00
)
*59 (Wire
uid 3370,0
optionalChildren [
*60 (BdJunction
uid 3406,0
ps "OnConnectorStrategy"
shape (Circle
uid 3407,0
va (VaSet
vasetType 1
2021-11-24 09:50:51 +00:00
)
xt "38600,-13400,39400,-12600"
radius 400
2021-11-24 09:50:51 +00:00
)
)
]
2021-11-24 09:50:51 +00:00
shape (OrthoPolyLine
uid 3371,0
2021-11-24 09:50:51 +00:00
va (VaSet
vasetType 3
lineWidth 2
2021-11-24 09:50:51 +00:00
)
xt "32000,-29000,41000,-13000"
2021-11-24 09:50:51 +00:00
pts [
"36750,-13000"
"41000,-13000"
"41000,-29000"
"32000,-29000"
2021-11-24 09:50:51 +00:00
]
)
start &31
end &38
2021-11-24 09:50:51 +00:00
sat 32
eat 1
sty 1
2021-11-24 09:50:51 +00:00
stc 0
sf 1
si 0
tg (WTG
uid 3374,0
2021-11-24 09:50:51 +00:00
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3375,0
2021-11-24 09:50:51 +00:00
va (VaSet
font "Verdana,12,0"
)
xt "38750,-14400,45350,-13000"
st "countOut"
blo "38750,-13200"
2021-11-24 09:50:51 +00:00
tm "WireNameMgr"
)
)
on &44
2021-11-24 09:50:51 +00:00
)
*61 (Wire
uid 3398,0
2021-11-24 09:50:51 +00:00
shape (OrthoPolyLine
uid 3399,0
2021-11-24 09:50:51 +00:00
va (VaSet
vasetType 3
)
xt "17000,19000,28250,22000"
2021-11-24 09:50:51 +00:00
pts [
"28250,22000"
"17000,22000"
"17000,19000"
2021-11-24 09:50:51 +00:00
]
)
start &25
end &46
2021-11-24 09:50:51 +00:00
sat 32
eat 32
2021-11-24 09:50:51 +00:00
stc 0
st 0
si 0
tg (WTG
uid 3400,0
2021-11-24 09:50:51 +00:00
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3401,0
2021-11-24 09:50:51 +00:00
va (VaSet
font "Verdana,12,0"
)
xt "23250,20600,27450,22000"
st "SideL"
blo "23250,21800"
2021-11-24 09:50:51 +00:00
tm "WireNameMgr"
)
)
on &50
2021-11-24 09:50:51 +00:00
)
*62 (Wire
uid 3402,0
2021-11-24 09:50:51 +00:00
shape (OrthoPolyLine
uid 3403,0
2021-11-24 09:50:51 +00:00
va (VaSet
vasetType 3
lineWidth 2
2021-11-24 09:50:51 +00:00
)
xt "26000,-13000,39000,18000"
2021-11-24 09:50:51 +00:00
pts [
"39000,-13000"
"39000,10000"
"26000,10000"
"26000,18000"
"28250,18000"
2021-11-24 09:50:51 +00:00
]
)
start &60
end &21
2021-11-24 09:50:51 +00:00
sat 32
eat 32
sty 1
stc 0
2021-11-24 09:50:51 +00:00
st 0
sf 1
si 0
tg (WTG
uid 3404,0
2021-11-24 09:50:51 +00:00
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3405,0
2021-11-24 09:50:51 +00:00
va (VaSet
font "Verdana,12,0"
)
xt "20250,16600,26850,18000"
st "countOut"
blo "20250,17800"
2021-11-24 09:50:51 +00:00
tm "WireNameMgr"
)
)
on &44
2021-11-24 09:50:51 +00:00
)
*63 (Wire
uid 3408,0
2021-11-24 09:50:51 +00:00
shape (OrthoPolyLine
uid 3409,0
2021-11-24 09:50:51 +00:00
va (VaSet
vasetType 3
)
xt "11000,-26000,21000,-26000"
2021-11-24 09:50:51 +00:00
pts [
"11000,-26000"
"21000,-26000"
2021-11-24 09:50:51 +00:00
]
)
end &38
sat 16
2021-11-24 09:50:51 +00:00
eat 1
stc 0
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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2021-11-24 09:50:51 +00:00
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