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70 lines
2.3 KiB
VHDL
70 lines
2.3 KiB
VHDL
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ARCHITECTURE test OF lcdSerializer_tester IS
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_ulogic := '1';
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constant initializationSequenceLength: positive := 14;
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type initializtionDataType is array (1 to initializationSequenceLength)
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of std_ulogic_vector(data'range);
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constant initializtionData: initializtionDataType :=(
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'0' & X"40", -- Display start line 0
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'0' & X"A1", --
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'0' & X"C0", --
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'0' & X"A6", --
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'0' & X"A2", --
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'0' & X"2F", --
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'0' & X"F8", --
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'0' & X"00", --
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'0' & X"23", --
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'0' & X"81", --
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'0' & X"1F", --
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'0' & X"AC", --
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'0' & X"00", --
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'0' & X"AF" --
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);
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- send sequence
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process
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begin
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data <= (others => '0');
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send <= '0';
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wait until falling_edge(busy);
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-- send initialization codes
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wait until rising_edge(clock_int);
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for index in initializtionData'range loop
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data <= initializtionData(index);
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send <= '1', '0' after clockPeriod;
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wait until rising_edge(busy);
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wait until falling_edge(busy);
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wait for 1 ns;
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end loop;
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wait for 100*clockPeriod;
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-- send pixel codes
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wait until rising_edge(clock_int);
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for index in 1 to 8 loop
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data <= std_ulogic_vector(to_unsigned(index, data'length));
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data(data'high) <= '1';
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send <= '1', '0' after clockPeriod;
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wait until rising_edge(busy);
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wait until falling_edge(busy);
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wait for 1 ns;
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end loop;
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wait for 100*clockPeriod;
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-- end of simulation
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assert false
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report "End of simulation"
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severity failure;
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wait;
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end process;
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END ARCHITECTURE test;
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