mirror of
https://github.com/Klagarge/Cursor.git
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1824 lines
23 KiB
Plaintext
1824 lines
23 KiB
Plaintext
|
DocumentHdrVersion "1.1"
|
||
|
Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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|
)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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|
]
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libraryRefs [
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"ieee"
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|
]
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)
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||
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version "26.1"
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|
appVersion "2018.1 (Build 12)"
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model (Symbol
|
||
|
commonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
suid 24,0
|
||
|
usingSuid 1
|
||
|
emptyRow *1 (LEmptyRow
|
||
|
)
|
||
|
uid 81,0
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||
|
optionalChildren [
|
||
|
*2 (RefLabelRowHdr
|
||
|
)
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||
|
*3 (TitleRowHdr
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||
|
)
|
||
|
*4 (FilterRowHdr
|
||
|
)
|
||
|
*5 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*6 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*7 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
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||
|
)
|
||
|
*8 (NameColHdr
|
||
|
tm "NameColHdrMgr"
|
||
|
)
|
||
|
*9 (ModeColHdr
|
||
|
tm "ModeColHdrMgr"
|
||
|
)
|
||
|
*10 (TypeColHdr
|
||
|
tm "TypeColHdrMgr"
|
||
|
)
|
||
|
*11 (BoundsColHdr
|
||
|
tm "BoundsColHdrMgr"
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||
|
)
|
||
|
*12 (InitColHdr
|
||
|
tm "InitColHdrMgr"
|
||
|
)
|
||
|
*13 (EolColHdr
|
||
|
tm "EolColHdrMgr"
|
||
|
)
|
||
|
*14 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "addrSelCol"
|
||
|
t "std_ulogic"
|
||
|
o 26
|
||
|
suid 18,0
|
||
|
)
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||
|
)
|
||
|
uid 360,0
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||
|
)
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||
|
*15 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "addrSelModeReg"
|
||
|
t "std_ulogic"
|
||
|
o 26
|
||
|
suid 19,0
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||
|
)
|
||
|
)
|
||
|
uid 362,0
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||
|
)
|
||
|
*16 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "addrSelPrecharge"
|
||
|
t "std_ulogic"
|
||
|
o 26
|
||
|
suid 20,0
|
||
|
)
|
||
|
)
|
||
|
uid 364,0
|
||
|
)
|
||
|
*17 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "addrSelRow"
|
||
|
t "std_ulogic"
|
||
|
o 26
|
||
|
suid 21,0
|
||
|
)
|
||
|
)
|
||
|
uid 366,0
|
||
|
)
|
||
|
*18 (LogPort
|
||
|
port (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "memAddress"
|
||
|
t "std_ulogic_vector"
|
||
|
b "( chipAddressBitNb-1 DOWNTO 0 )"
|
||
|
o 9
|
||
|
suid 22,0
|
||
|
)
|
||
|
)
|
||
|
uid 368,0
|
||
|
)
|
||
|
*19 (LogPort
|
||
|
port (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "memBankAddress"
|
||
|
t "std_ulogic_vector"
|
||
|
b "( chipBankAddressBitNb-1 DOWNTO 0 )"
|
||
|
o 10
|
||
|
suid 23,0
|
||
|
)
|
||
|
)
|
||
|
uid 370,0
|
||
|
)
|
||
|
*20 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "ramAddr"
|
||
|
t "unsigned"
|
||
|
b "(addressBitNb-1 DOWNTO 0)"
|
||
|
o 3
|
||
|
suid 24,0
|
||
|
)
|
||
|
)
|
||
|
uid 372,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 94,0
|
||
|
optionalChildren [
|
||
|
*21 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
emptyMRCItem *22 (MRCItem
|
||
|
litem &1
|
||
|
pos 7
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 96,0
|
||
|
optionalChildren [
|
||
|
*23 (MRCItem
|
||
|
litem &2
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 97,0
|
||
|
)
|
||
|
*24 (MRCItem
|
||
|
litem &3
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 98,0
|
||
|
)
|
||
|
*25 (MRCItem
|
||
|
litem &4
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 99,0
|
||
|
)
|
||
|
*26 (MRCItem
|
||
|
litem &14
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 361,0
|
||
|
)
|
||
|
*27 (MRCItem
|
||
|
litem &15
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 363,0
|
||
|
)
|
||
|
*28 (MRCItem
|
||
|
litem &16
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
uid 365,0
|
||
|
)
|
||
|
*29 (MRCItem
|
||
|
litem &17
|
||
|
pos 3
|
||
|
dimension 20
|
||
|
uid 367,0
|
||
|
)
|
||
|
*30 (MRCItem
|
||
|
litem &18
|
||
|
pos 4
|
||
|
dimension 20
|
||
|
uid 369,0
|
||
|
)
|
||
|
*31 (MRCItem
|
||
|
litem &19
|
||
|
pos 5
|
||
|
dimension 20
|
||
|
uid 371,0
|
||
|
)
|
||
|
*32 (MRCItem
|
||
|
litem &20
|
||
|
pos 6
|
||
|
dimension 20
|
||
|
uid 373,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 100,0
|
||
|
optionalChildren [
|
||
|
*33 (MRCItem
|
||
|
litem &5
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 101,0
|
||
|
)
|
||
|
*34 (MRCItem
|
||
|
litem &7
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 102,0
|
||
|
)
|
||
|
*35 (MRCItem
|
||
|
litem &8
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 103,0
|
||
|
)
|
||
|
*36 (MRCItem
|
||
|
litem &9
|
||
|
pos 3
|
||
|
dimension 50
|
||
|
uid 104,0
|
||
|
)
|
||
|
*37 (MRCItem
|
||
|
litem &10
|
||
|
pos 4
|
||
|
dimension 100
|
||
|
uid 105,0
|
||
|
)
|
||
|
*38 (MRCItem
|
||
|
litem &11
|
||
|
pos 5
|
||
|
dimension 100
|
||
|
uid 106,0
|
||
|
)
|
||
|
*39 (MRCItem
|
||
|
litem &12
|
||
|
pos 6
|
||
|
dimension 50
|
||
|
uid 107,0
|
||
|
)
|
||
|
*40 (MRCItem
|
||
|
litem &13
|
||
|
pos 7
|
||
|
dimension 80
|
||
|
uid 108,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 95,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 80,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *41 (LEmptyRow
|
||
|
)
|
||
|
uid 110,0
|
||
|
optionalChildren [
|
||
|
*42 (RefLabelRowHdr
|
||
|
)
|
||
|
*43 (TitleRowHdr
|
||
|
)
|
||
|
*44 (FilterRowHdr
|
||
|
)
|
||
|
*45 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*46 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*47 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*48 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*49 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*50 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*51 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*52 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
*53 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "addressBitNb"
|
||
|
type "positive"
|
||
|
value "24"
|
||
|
)
|
||
|
uid 159,0
|
||
|
)
|
||
|
*54 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "chipAddressBitNb"
|
||
|
type "positive"
|
||
|
value "12"
|
||
|
)
|
||
|
uid 161,0
|
||
|
)
|
||
|
*55 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "chipBankAddressBitNb"
|
||
|
type "positive"
|
||
|
value "2"
|
||
|
)
|
||
|
uid 163,0
|
||
|
)
|
||
|
*56 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "rowAddressBitNb"
|
||
|
type "positive"
|
||
|
value "12"
|
||
|
)
|
||
|
uid 420,0
|
||
|
)
|
||
|
*57 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "colAddressBitNb"
|
||
|
type "positive"
|
||
|
value "2"
|
||
|
)
|
||
|
uid 422,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 122,0
|
||
|
optionalChildren [
|
||
|
*58 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
)
|
||
|
emptyMRCItem *59 (MRCItem
|
||
|
litem &41
|
||
|
pos 5
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 124,0
|
||
|
optionalChildren [
|
||
|
*60 (MRCItem
|
||
|
litem &42
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 125,0
|
||
|
)
|
||
|
*61 (MRCItem
|
||
|
litem &43
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 126,0
|
||
|
)
|
||
|
*62 (MRCItem
|
||
|
litem &44
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 127,0
|
||
|
)
|
||
|
*63 (MRCItem
|
||
|
litem &53
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 160,0
|
||
|
)
|
||
|
*64 (MRCItem
|
||
|
litem &54
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 162,0
|
||
|
)
|
||
|
*65 (MRCItem
|
||
|
litem &55
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
uid 164,0
|
||
|
)
|
||
|
*66 (MRCItem
|
||
|
litem &56
|
||
|
pos 3
|
||
|
dimension 20
|
||
|
uid 421,0
|
||
|
)
|
||
|
*67 (MRCItem
|
||
|
litem &57
|
||
|
pos 4
|
||
|
dimension 20
|
||
|
uid 423,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "courier,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 128,0
|
||
|
optionalChildren [
|
||
|
*68 (MRCItem
|
||
|
litem &45
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 129,0
|
||
|
)
|
||
|
*69 (MRCItem
|
||
|
litem &47
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 130,0
|
||
|
)
|
||
|
*70 (MRCItem
|
||
|
litem &48
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 131,0
|
||
|
)
|
||
|
*71 (MRCItem
|
||
|
litem &49
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 132,0
|
||
|
)
|
||
|
*72 (MRCItem
|
||
|
litem &50
|
||
|
pos 4
|
||
|
dimension 50
|
||
|
uid 133,0
|
||
|
)
|
||
|
*73 (MRCItem
|
||
|
litem &51
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 134,0
|
||
|
)
|
||
|
*74 (MRCItem
|
||
|
litem &52
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 135,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 123,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 109,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@build@address/symbol.sb.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@build@address/symbol.sb.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "concatenated"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_%(view)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@build@address"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerBuildAddress"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "08/28/19"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "Wed"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "Wednesday"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "28"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "designName"
|
||
|
value "$DESIGN_NAME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "sdramControllerBuildAddress"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_author"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_date"
|
||
|
value "08/28/19"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_group"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_host"
|
||
|
value "Aphelia"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_time"
|
||
|
value "13:45:14"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "Aphelia"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "Memory"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/Libs/Memory/work"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "08"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "sdramControllerBuildAddress"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "Aug"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "August"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@build@address/symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerBuildAddress/symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_DesignCompilerPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_HDSPath"
|
||
|
value "$HDS_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEBinPath"
|
||
|
value "$ISE_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEPath"
|
||
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_LeonardoPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ModelSimPath"
|
||
|
value "$MODELSIM_HOME\\win32"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_NC-SimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_PrecisionRTLPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_QuestaSimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_VCSPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_ext"
|
||
|
value "sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file_logical"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "time"
|
||
|
value "13:45:14"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "unit"
|
||
|
value "sdramControllerBuildAddress"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2018.1 (Build 12)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2019"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "yy"
|
||
|
value "19"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
LanguageMgr "Vhdl2008LangMgr"
|
||
|
uid 79,0
|
||
|
optionalChildren [
|
||
|
*75 (SymbolBody
|
||
|
uid 8,0
|
||
|
optionalChildren [
|
||
|
*76 (CptPort
|
||
|
uid 325,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 326,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "33250,17625,34000,18375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 327,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 328,0
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "35000,17500,39600,18500"
|
||
|
st "addrSelCol"
|
||
|
blo "35000,18300"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 329,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "0,30400,20000,31300"
|
||
|
st "addrSelCol : IN std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "addrSelCol"
|
||
|
t "std_ulogic"
|
||
|
o 26
|
||
|
suid 18,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*77 (CptPort
|
||
|
uid 330,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 331,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "33250,13625,34000,14375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 332,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 333,0
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "35000,13500,41800,14500"
|
||
|
st "addrSelModeReg"
|
||
|
blo "35000,14300"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 334,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "0,31300,20000,32200"
|
||
|
st "addrSelModeReg : IN std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "addrSelModeReg"
|
||
|
t "std_ulogic"
|
||
|
o 26
|
||
|
suid 19,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*78 (CptPort
|
||
|
uid 335,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 336,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "33250,11625,34000,12375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 337,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 338,0
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "35000,11500,42000,12500"
|
||
|
st "addrSelPrecharge"
|
||
|
blo "35000,12300"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 339,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "0,32200,20000,33100"
|
||
|
st "addrSelPrecharge : IN std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "addrSelPrecharge"
|
||
|
t "std_ulogic"
|
||
|
o 26
|
||
|
suid 20,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*79 (CptPort
|
||
|
uid 340,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 341,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "33250,15625,34000,16375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 342,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 343,0
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "35000,15500,39900,16500"
|
||
|
st "addrSelRow"
|
||
|
blo "35000,16300"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 344,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "0,33100,20000,34000"
|
||
|
st "addrSelRow : IN std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "addrSelRow"
|
||
|
t "std_ulogic"
|
||
|
o 26
|
||
|
suid 21,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*80 (CptPort
|
||
|
uid 345,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 346,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "50000,9625,50750,10375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 347,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 348,0
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "43800,9500,49000,10500"
|
||
|
st "memAddress"
|
||
|
ju 2
|
||
|
blo "49000,10300"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 349,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "0,34900,39000,35800"
|
||
|
st "memAddress : OUT std_ulogic_vector ( chipAddressBitNb-1 DOWNTO 0 ) ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "memAddress"
|
||
|
t "std_ulogic_vector"
|
||
|
b "( chipAddressBitNb-1 DOWNTO 0 )"
|
||
|
o 9
|
||
|
suid 22,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*81 (CptPort
|
||
|
uid 350,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 351,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "50000,11625,50750,12375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 352,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 353,0
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "42200,11500,49000,12500"
|
||
|
st "memBankAddress"
|
||
|
ju 2
|
||
|
blo "49000,12300"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 354,0
|
||
|
va (VaSet
|
||
|
font "courier,8,0"
|
||
|
)
|
||
|
xt "0,35800,40000,36700"
|
||
|
st "memBankAddress : OUT std_ulogic_vector ( chipBankAddressBitNb-1 DOWNTO 0 )"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "memBankAddress"
|
||
|
t "std_ulogic_vector"
|
||
|
b "( chipBankAddressBitNb-1 DOWNTO 0 )"
|
||
|
o 10
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lineColor "0,0,32768"
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)
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|
xt "0,0,15000,5000"
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)
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text (MLText
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va (VaSet
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fg "0,0,32768"
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)
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xt "200,200,2600,1200"
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st "
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Text
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tm "CommentText"
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wrapOption 3
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visibleHeight 4600
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|
visibleWidth 14600
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)
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)
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defaultRequirementText (RequirementText
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shape (ZoomableIcon
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layer 0
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va (VaSet
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vasetType 1
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fg "59904,39936,65280"
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lineColor "0,0,32768"
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)
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)
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autoResize 1
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text (MLText
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va (VaSet
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fg "0,0,32768"
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font "courier,8,0"
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)
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xt "450,2150,1450,3050"
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st "
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Text
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"
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tm "RequirementText"
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wrapOption 3
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visibleHeight 1350
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|
visibleWidth 1100
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)
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)
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defaultPanel (Panel
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shape (RectFrame
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va (VaSet
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vasetType 1
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fg "65535,65535,65535"
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lineColor "32768,0,0"
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)
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xt "0,0,20000,20000"
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)
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title (TextAssociate
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ps "TopLeftStrategy"
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text (Text
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va (VaSet
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font "courier,8,1"
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)
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blo "1000,1800"
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tm "PanelText"
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)
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)
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)
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parentGraphicsRef (HdmGraphicsRef
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entityName "sdramController"
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)
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defaultSymbolBody (SymbolBody
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shape (Rectangle
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va (VaSet
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stg "VerticalLayoutStrategy"
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va (VaSet
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va (VaSet
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font "courier,8,1"
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blo "22200,16800"
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)
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gi *98 (GenericInterface
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ps "CenterOffsetStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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)
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header "Generic Declarations"
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)
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elements [
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]
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)
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portInstanceVis (PortSigDisplay
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sIVOD 1
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)
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portVis (PortSigDisplay
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sIVOD 1
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)
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)
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defaultCptPort (CptPort
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ps "OnEdgeStrategy"
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ro 90
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va (VaSet
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)
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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blo "0,1450"
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tm "CptPortNameMgr"
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)
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dt (MLText
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va (VaSet
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font "courier,8,0"
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)
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thePort (LogicalPort
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lang 11
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decl (Decl
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n "In0"
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b "(15 DOWNTO 0)"
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o 0
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)
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)
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)
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defaultCptPortBuffer (CptPort
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ps "OnEdgeStrategy"
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shape (Diamond
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va (VaSet
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vasetType 1
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fg "65535,65535,65535"
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bg "0,0,0"
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)
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xt "0,0,750,750"
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)
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "courier,8,0"
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st "Buffer0"
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blo "0,1450"
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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va (VaSet
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font "courier,8,0"
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)
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)
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thePort (LogicalPort
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lang 11
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m 3
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decl (Decl
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n "Buffer0"
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t "std_logic_vector"
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b "(15 DOWNTO 0)"
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o 0
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)
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)
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)
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DeclarativeBlock *99 (SymDeclBlock
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uid 1,0
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stg "SymDeclLayoutStrategy"
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declLabel (Text
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uid 2,0
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va (VaSet
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font "courier,8,1"
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)
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st "Declarations"
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blo "-2000,29200"
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)
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portLabel (Text
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uid 3,0
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va (VaSet
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font "courier,8,1"
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)
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xt "-2000,29400,700,30400"
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st "Ports:"
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blo "-2000,30200"
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)
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externalLabel (Text
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uid 4,0
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va (VaSet
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font "courier,8,1"
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)
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st "User:"
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blo "-2000,37400"
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)
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internalLabel (Text
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uid 6,0
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va (VaSet
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|
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font "courier,8,1"
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)
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xt "-2000,28400,3800,29400"
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|
st "Internal User:"
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|
blo "-2000,29200"
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)
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externalText (MLText
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uid 5,0
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va (VaSet
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|
font "courier,8,0"
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)
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|
xt "0,37600,0,37600"
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|
tm "SyDeclarativeTextMgr"
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)
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internalText (MLText
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uid 7,0
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|
va (VaSet
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|
isHidden 1
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|
font "courier,8,0"
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)
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|
xt "-2000,28400,-2000,28400"
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|
tm "SyDeclarativeTextMgr"
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|
)
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)
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lastUid 446,0
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activeModelName "Symbol:GEN"
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)
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