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Cursor/Cursor_test/hds/divider_tb/struct.bd

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2021-11-24 09:50:51 +00:00
DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
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library "ieee"
unitName "std_logic_1164"
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library "ieee"
unitName "numeric_std"
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duLibraryName "Cursor_test"
duName "divider_tester"
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duLibraryName "Cursor"
duName "divider"
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version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
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value " "
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hdl"
)
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variable "HDSDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd.user"
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variable "config"
value "%(unit)_%(view)_config"
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variable "d"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb"
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(vvPair
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value "11.11.2019"
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value "Mon"
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value "Monday"
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variable "dd"
value "11"
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variable "entity_name"
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variable "f_noext"
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variable "graphical_source_author"
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variable "graphical_source_date"
value "11.11.2019"
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variable "graphical_source_group"
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value "WE6996"
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variable "graphical_source_time"
value "08:13:22"
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variable "group"
value "UNKNOWN"
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variable "host"
value "WE6996"
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variable "language"
value "VHDL"
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variable "library"
value "Cursor_test"
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variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
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variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Cursor_test/work"
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(vvPair
variable "mm"
value "11"
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variable "module_name"
value "divider_tb"
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(vvPair
variable "month"
value "Nov"
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variable "month_long"
value "November"
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variable "p"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd"
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variable "p_logical"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd"
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variable "package_name"
value "<Undefined Variable>"
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variable "project_name"
value "hds"
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variable "series"
value "HDL Designer Series"
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variable "task_ADMS"
value "<TBD>"
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variable "task_DesignCompilerPath"
value "<TBD>"
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variable "task_LeonardoPath"
value "<TBD>"
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variable "task_ModelSimPath"
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variable "unit"
value "divider_tb"
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(vvPair
variable "user"
value "silvan.zahno"
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(vvPair
variable "version"
value "2019.2 (Build 5)"
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(vvPair
variable "view"
value "struct"
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(vvPair
variable "year"
value "2019"
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*70 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*71 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*72 (GroupColHdr
tm "GroupColHdrMgr"
)
*73 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*74 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*75 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*76 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*77 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*78 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
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m 4
decl (Decl
n "reset"
t "std_ulogic"
o 4
suid 1,0
)
)
uid 2369,0
)
*80 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 2,0
)
)
uid 2371,0
)
*81 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "testMode"
t "std_uLogic"
o 5
suid 3,0
)
)
uid 2373,0
)
*82 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "enPWM"
t "std_uLogic"
o 2
suid 6,0
)
)
uid 2379,0
)
*83 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "enRamp"
t "std_uLogic"
o 3
suid 9,0
)
)
uid 2541,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 2395,0
optionalChildren [
*84 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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)
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optionalChildren [
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pos 4
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uid 2542,0
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sheetCol (SheetCol
propVa (MVa
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optionalChildren [
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uid 2402,0
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uid 2406,0
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*100 (MRCItem
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pos 6
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uid 2408,0
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pos 7
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uid 2409,0
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)
fixedCol 4
fixedRow 2
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vaOverrides [
]
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uid 2381,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *102 (LEmptyRow
)
uid 2411,0
optionalChildren [
*103 (RefLabelRowHdr
)
*104 (TitleRowHdr
)
*105 (FilterRowHdr
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*106 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*107 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*108 (GroupColHdr
tm "GroupColHdrMgr"
)
*109 (NameColHdr
tm "GenericNameColHdrMgr"
)
*110 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*111 (InitColHdr
tm "GenericValueColHdrMgr"
)
*112 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*113 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
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optionalChildren [
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
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groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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sheetCol (SheetCol
propVa (MVa
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fontColor "0,0,0"
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uid 2434,0
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fixedCol 3
fixedRow 2
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vaOverrides [
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uid 2410,0
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activeModelName "BlockDiag"
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