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17 lines
264 B
VHDL
17 lines
264 B
VHDL
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ARCHITECTURE sim OF DFFE_pre IS
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BEGIN
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process(clk, pre)
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begin
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if pre = '1' then
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q <= '1' after delay;
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elsif rising_edge(clk) then
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if e = '1' then
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q <= d after delay;
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end if;
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end if;
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end process;
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END ARCHITECTURE sim;
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