Cursor/Libs/Memory_test/hds/flash@controller_tb/struct.bd

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)
)
*35 (Net
uid 6843,0
decl (Decl
n "flashEn"
t "std_ulogic"
o 11
suid 86,0
)
declText (MLText
uid 6844,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL flashEn        : std_ulogic"
)
)
*36 (Net
uid 6922,0
decl (Decl
n "flashDataValid"
t "std_ulogic"
o 10
suid 87,0
)
declText (MLText
uid 6923,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL flashDataValid : std_ulogic"
)
)
*37 (Net
uid 6930,0
decl (Decl
n "flashRd"
t "std_ulogic"
o 12
suid 88,0
)
declText (MLText
uid 6931,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL flashRd        : std_ulogic"
)
)
*38 (Net
uid 6938,0
decl (Decl
n "flashWr"
t "std_ulogic"
o 14
suid 89,0
)
declText (MLText
uid 6939,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL flashWr        : std_ulogic"
)
)
*39 (Net
uid 6946,0
decl (Decl
n "flashDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 9
suid 90,0
)
declText (MLText
uid 6947,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,32000,900"
st "SIGNAL flashDataOut   : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*40 (Net
uid 6954,0
decl (Decl
n "flashDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 8
suid 91,0
)
declText (MLText
uid 6955,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,32000,900"
st "SIGNAL flashDataIn    : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*41 (Net
uid 6962,0
decl (Decl
n "flashAddr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 6
suid 92,0
)
declText (MLText
uid 6963,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,29000,900"
st "SIGNAL flashAddr      : unsigned(addressBitNb-1 DOWNTO 0)"
)
)
*42 (Net
uid 6984,0
decl (Decl
n "A"
t "unsigned"
b "(23 DOWNTO 0)"
o 1
suid 93,0
)
declText (MLText
uid 6985,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,23000,900"
st "SIGNAL A              : unsigned(23 DOWNTO 0)"
)
)
*43 (Net
uid 6994,0
decl (Decl
n "CE"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 3
suid 94,0
)
declText (MLText
uid 6995,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,27000,900"
st "SIGNAL CE             : std_ulogic_vector(2 DOWNTO 0)"
)
)
*44 (Net
uid 7044,0
decl (Decl
n "memWrDelayed_n"
t "std_ulogic"
o 21
suid 95,0
)
declText (MLText
uid 7045,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL memWrDelayed_n : std_ulogic"
)
)
*45 (Net
uid 7125,0
decl (Decl
n "memRst_n"
t "std_ulogic"
o 20
suid 96,0
)
declText (MLText
uid 7126,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL memRst_n       : std_ulogic"
)
)
*46 (SaComponent
uid 7294,0
optionalChildren [
*47 (CptPort
uid 7222,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7223,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,74625,46000,75375"
)
tg (CPTG
uid 7224,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7225,0
va (VaSet
)
xt "47000,74500,49100,75500"
st "clock"
blo "47000,75300"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 20,0
)
)
)
*48 (CptPort
uid 7226,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7227,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,66625,46000,67375"
)
tg (CPTG
uid 7228,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7229,0
va (VaSet
)
xt "47000,66500,52700,67500"
st "flashDataValid"
blo "47000,67300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "flashDataValid"
t "std_ulogic"
o 14
suid 21,0
)
)
)
*49 (CptPort
uid 7230,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7231,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,56625,46000,57375"
)
tg (CPTG
uid 7232,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7233,0
va (VaSet
)
xt "47000,56500,50600,57500"
st "flashAddr"
blo "47000,57300"
)
)
thePort (LogicalPort
decl (Decl
n "flashAddr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 3
suid 22,0
)
)
)
*50 (CptPort
uid 7234,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7235,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,56625,62750,57375"
)
tg (CPTG
uid 7236,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7237,0
va (VaSet
)
xt "55800,56500,61000,57500"
st "memAddress"
ju 2
blo "61000,57300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memAddress"
t "std_ulogic_vector"
b "( chipAddressBitNb-1 DOWNTO 0 )"
o 10
suid 23,0
)
)
)
*51 (CptPort
uid 7238,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7239,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,60625,46000,61375"
)
tg (CPTG
uid 7240,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7241,0
va (VaSet
)
xt "47000,60500,52200,61500"
st "flashDataOut"
blo "47000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "flashDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 24,0
)
)
)
*52 (CptPort
uid 7242,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7243,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,58625,62750,59375"
)
tg (CPTG
uid 7244,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7245,0
va (VaSet
)
xt "56800,58500,61000,59500"
st "memDataIn"
ju 2
blo "61000,59300"
)
)
thePort (LogicalPort
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 25,0
)
)
)
*53 (CptPort
uid 7246,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7247,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,60625,62750,61375"
)
tg (CPTG
uid 7248,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7249,0
va (VaSet
)
xt "55800,60500,61000,61500"
st "memDataOut"
ju 2
blo "61000,61300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 11
suid 26,0
)
)
)
*54 (CptPort
uid 7250,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7251,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,64625,62750,65375"
)
tg (CPTG
uid 7252,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7253,0
va (VaSet
)
xt "57200,64500,61000,65500"
st "memWr_n"
ju 2
blo "61000,65300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr_n"
t "std_ulogic"
o 12
suid 27,0
)
)
)
*55 (CptPort
uid 7254,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7255,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,72625,46000,73375"
)
tg (CPTG
uid 7256,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7257,0
va (VaSet
)
xt "47000,72500,49900,73500"
st "flashEn"
blo "47000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "flashEn"
t "std_ulogic"
o 5
suid 28,0
)
)
)
*56 (CptPort
uid 7258,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7259,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,62625,46000,63375"
)
tg (CPTG
uid 7260,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7261,0
va (VaSet
)
xt "47000,62500,50000,63500"
st "flashRd"
blo "47000,63300"
)
)
thePort (LogicalPort
decl (Decl
n "flashRd"
t "std_ulogic"
o 6
suid 29,0
)
)
)
*57 (CptPort
uid 7262,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7263,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,64625,46000,65375"
)
tg (CPTG
uid 7264,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7265,0
va (VaSet
)
xt "47000,64500,50000,65500"
st "flashWr"
blo "47000,65300"
)
)
thePort (LogicalPort
decl (Decl
n "flashWr"
t "std_ulogic"
o 7
suid 30,0
)
)
)
*58 (CptPort
uid 7266,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7267,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,76625,46000,77375"
)
tg (CPTG
uid 7268,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7269,0
va (VaSet
)
xt "47000,76500,49100,77500"
st "reset"
blo "47000,77300"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 8
suid 31,0
)
)
)
*59 (CptPort
uid 7270,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7271,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,68625,62750,69375"
)
tg (CPTG
uid 7272,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7273,0
va (VaSet
)
xt "57000,68500,61000,69500"
st "memRst_n"
ju 2
blo "61000,69300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memRst_n"
t "std_ulogic"
o 15
suid 33,0
)
)
)
*60 (CptPort
uid 7274,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7275,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,70625,62750,71375"
)
tg (CPTG
uid 7276,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7277,0
va (VaSet
)
xt "57500,70500,61000,71500"
st "flashSTS"
ju 2
blo "61000,71300"
)
)
thePort (LogicalPort
decl (Decl
n "flashSTS"
t "std_ulogic"
o 16
suid 34,0
)
)
)
*61 (CptPort
uid 7278,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7279,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,62625,62750,63375"
)
tg (CPTG
uid 7280,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7281,0
va (VaSet
)
xt "57100,62500,61000,63500"
st "flashCE_n"
ju 2
blo "61000,63300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "flashCE_n"
t "std_ulogic"
o 9
suid 35,0
)
)
)
*62 (CptPort
uid 7282,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7283,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,66625,62750,67375"
)
tg (CPTG
uid 7284,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7285,0
va (VaSet
)
xt "57100,66500,61000,67500"
st "memOE_n"
ju 2
blo "61000,67300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memOE_n"
t "std_ulogic"
o 17
suid 36,0
)
)
)
*63 (CptPort
uid 7286,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7287,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,58625,46000,59375"
)
tg (CPTG
uid 7288,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7289,0
va (VaSet
)
xt "47000,58500,51600,59500"
st "flashDataIn"
blo "47000,59300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "flashDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 13
suid 42,0
)
)
)
*64 (CptPort
uid 7290,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7291,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,70625,46000,71375"
)
tg (CPTG
uid 7292,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7293,0
va (VaSet
)
xt "47000,70500,52400,71500"
st "memBusEn_n"
blo "47000,71300"
)
)
thePort (LogicalPort
decl (Decl
n "memBusEn_n"
t "std_ulogic"
o 18
suid 44,0
)
)
)
]
shape (Rectangle
uid 7295,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "46000,53000,62000,79000"
)
oxt "37000,5000,53000,31000"
ttg (MlTextGroup
uid 7296,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*65 (Text
uid 7297,0
va (VaSet
font "courier,8,1"
)
xt "46550,79500,49850,80500"
st "memory"
blo "46550,80300"
tm "BdLibraryNameMgr"
)
*66 (Text
uid 7298,0
va (VaSet
font "courier,8,1"
)
xt "46550,80500,52950,81500"
st "flashController"
blo "46550,81300"
tm "CptNameMgr"
)
*67 (Text
uid 7299,0
va (VaSet
font "courier,8,1"
)
xt "46550,81500,47550,82500"
st "I0"
blo "46550,82300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 7300,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 7301,0
text (MLText
uid 7302,0
va (VaSet
font "courier,8,0"
)
xt "46000,83200,71000,85900"
st "addressBitNb     = addressBitNb    ( positive )  
dataBitNb        = dataBitNb       ( positive )  
chipAddressBitNb = addressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "chipAddressBitNb"
type "positive"
value "addressBitNb"
)
]
)
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*68 (Net
uid 7303,0
decl (Decl
n "memBusEn_n"
t "std_ulogic"
o 16
suid 97,0
)
declText (MLText
uid 7304,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL memBusEn_n     : std_ulogic"
)
)
*69 (SaComponent
uid 7440,0
optionalChildren [
*70 (CptPort
uid 7408,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7409,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,60625,78000,61375"
)
tg (CPTG
uid 7410,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7411,0
va (VaSet
)
xt "79000,60500,79900,61500"
st "A"
blo "79000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "A"
t "unsigned"
b "(23 DOWNTO 0)"
o 45
suid 1,0
)
)
)
*71 (CptPort
uid 7412,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7413,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,68625,78000,69375"
)
tg (CPTG
uid 7414,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7415,0
va (VaSet
)
xt "79000,68500,82200,69500"
st "BYTE_n"
blo "79000,69300"
)
)
thePort (LogicalPort
decl (Decl
n "BYTE_n"
t "std_ulogic"
o 48
suid 2,0
)
)
)
*72 (CptPort
uid 7416,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7417,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,62625,78000,63375"
)
tg (CPTG
uid 7418,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7419,0
va (VaSet
)
xt "79000,62500,80500,63500"
st "CE"
blo "79000,63300"
)
)
thePort (LogicalPort
decl (Decl
n "CE"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 45
suid 3,0
)
)
)
*73 (CptPort
uid 7420,0
ps "OnEdgeStrategy"
shape (Diamond
uid 7421,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "86000,60625,86750,61375"
)
tg (CPTG
uid 7422,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7423,0
va (VaSet
)
xt "83400,60500,85000,61500"
st "DQ"
ju 2
blo "85000,61300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "DQ"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 45
suid 4,0
)
)
)
*74 (CptPort
uid 7424,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7425,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,66625,78000,67375"
)
tg (CPTG
uid 7426,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7427,0
va (VaSet
)
xt "79000,66500,81300,67500"
st "OE_n"
blo "79000,67300"
)
)
thePort (LogicalPort
decl (Decl
n "OE_n"
t "std_ulogic"
o 48
suid 5,0
)
)
)
*75 (CptPort
uid 7428,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7429,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,72625,78000,73375"
)
tg (CPTG
uid 7430,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7431,0
va (VaSet
)
xt "79000,72500,81300,73500"
st "RP_n"
blo "79000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "RP_n"
t "std_ulogic"
o 48
suid 6,0
)
)
)
*76 (CptPort
uid 7432,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7433,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "86000,62625,86750,63375"
)
tg (CPTG
uid 7434,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7435,0
va (VaSet
)
xt "83100,62500,85000,63500"
st "STS"
ju 2
blo "85000,63300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "STS"
t "std_ulogic"
o 48
suid 7,0
)
)
)
*77 (CptPort
uid 7436,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7437,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,64625,78000,65375"
)
tg (CPTG
uid 7438,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7439,0
va (VaSet
)
xt "79000,64500,81400,65500"
st "WE_n"
blo "79000,65300"
)
)
thePort (LogicalPort
decl (Decl
n "WE_n"
t "std_ulogic"
o 48
suid 8,0
)
)
)
]
shape (Rectangle
uid 7441,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,57000,86000,75000"
)
oxt "35000,13000,43000,31000"
ttg (MlTextGroup
uid 7442,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*78 (Text
uid 7443,0
va (VaSet
font "courier,8,1"
)
xt "77800,75000,83300,76000"
st "memory_test"
blo "77800,75800"
tm "BdLibraryNameMgr"
)
*79 (Text
uid 7444,0
va (VaSet
font "courier,8,1"
)
xt "77800,76000,84600,77000"
st "flash_28F128J3A"
blo "77800,76800"
tm "CptNameMgr"
)
*80 (Text
uid 7445,0
va (VaSet
font "courier,8,1"
)
xt "77800,77000,78800,78000"
st "I2"
blo "77800,77800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 7446,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 7447,0
text (MLText
uid 7448,0
va (VaSet
font "courier,8,0"
)
xt "78000,78600,112500,86700"
st "fileSpec      = \"U:\\ELN_board\\Simulation\\flash.srec\"    ( string )  
T_W13         = 500 ns                                  ( time   )  
T_W16_program = 1 us                                    ( time   )  
T_W16_erase   = 1.5 us                                  ( time   )  
T_R2          = 120 ns                                  ( time   )  
T_R3          = 120 ns                                  ( time   )  
T_R7          = 0 ns                                    ( time   )  
T_R8          = 55 ns                                   ( time   )  
T_R9          = 15 ns                                   ( time   )  "
)
header ""
)
elements [
(GiElement
name "fileSpec"
type "string"
value "\"U:\\ELN_board\\Simulation\\flash.srec\""
)
(GiElement
name "T_W13"
type "time"
value "500 ns"
)
(GiElement
name "T_W16_program"
type "time"
value "1 us"
)
(GiElement
name "T_W16_erase"
type "time"
value "1.5 us"
)
(GiElement
name "T_R2"
type "time"
value "120 ns"
)
(GiElement
name "T_R3"
type "time"
value "120 ns"
)
(GiElement
name "T_R7"
type "time"
value "0 ns"
)
(GiElement
name "T_R8"
type "time"
value "55 ns"
)
(GiElement
name "T_R9"
type "time"
value "15 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*81 (Wire
uid 5552,0
shape (OrthoPolyLine
uid 5553,0
va (VaSet
vasetType 3
)
xt "44000,77000,45250,87000"
pts [
"45250,77000"
"44000,77000"
"44000,87000"
]
)
start &58
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 5556,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5557,0
va (VaSet
font "courier,12,0"
)
xt "40250,75600,43750,76900"
st "reset"
blo "40250,76600"
tm "WireNameMgr"
)
)
on &16
)
*82 (Wire
uid 5560,0
shape (OrthoPolyLine
uid 5561,0
va (VaSet
vasetType 3
)
xt "42000,75000,45250,87000"
pts [
"45250,75000"
"42000,75000"
"42000,87000"
]
)
start &47
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 5564,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5565,0
va (VaSet
font "courier,12,0"
)
xt "40250,73600,43750,74900"
st "clock"
blo "40250,74600"
tm "WireNameMgr"
)
)
on &17
)
*83 (Wire
uid 5568,0
shape (OrthoPolyLine
uid 5569,0
va (VaSet
vasetType 3
)
xt "40000,73000,45250,87000"
pts [
"45250,73000"
"40000,73000"
"40000,87000"
]
)
start &55
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 5572,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5573,0
va (VaSet
font "courier,12,0"
)
xt "39250,71600,44150,72900"
st "flashEn"
blo "39250,72600"
tm "WireNameMgr"
)
)
on &35
)
*84 (Wire
uid 5921,0
shape (OrthoPolyLine
uid 5922,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62750,59000,66000,59000"
pts [
"62750,59000"
"66000,59000"
]
)
start &52
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 5925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5926,0
va (VaSet
font "courier,12,0"
)
xt "64750,57600,71050,58900"
st "memDataIn"
blo "64750,58600"
tm "WireNameMgr"
)
)
on &18
)
*85 (Wire
uid 5929,0
shape (OrthoPolyLine
uid 5930,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62750,61000,66000,61000"
pts [
"62750,61000"
"66000,61000"
]
)
start &53
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 5933,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5934,0
va (VaSet
font "courier,12,0"
)
xt "64750,59600,72450,60900"
st "memDataOut"
blo "64750,60600"
tm "WireNameMgr"
)
)
on &19
)
*86 (Wire
uid 6050,0
shape (OrthoPolyLine
uid 6051,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "86750,61000,94000,61000"
pts [
"86750,61000"
"94000,61000"
]
)
start &73
end &22
sat 32
eat 4
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6054,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6055,0
va (VaSet
font "courier,12,0"
)
xt "88750,59600,90150,60900"
st "DQ"
blo "88750,60600"
tm "WireNameMgr"
)
)
on &21
)
*87 (Wire
uid 6114,0
shape (OrthoPolyLine
uid 6115,0
va (VaSet
vasetType 3
)
xt "90000,63000,94000,63000"
pts [
"90000,63000"
"94000,63000"
]
)
end &22
sat 16
eat 1
stc 0
st 0
si 0
tg (WTG
uid 6120,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6121,0
va (VaSet
font "courier,12,0"
)
xt "87000,61600,91900,62900"
st "memWr_n"
blo "87000,62600"
tm "WireNameMgr"
)
)
on &20
)
*88 (Wire
uid 6122,0
shape (OrthoPolyLine
uid 6123,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,61000,114000,61000"
pts [
"110000,61000"
"114000,61000"
]
)
start &22
sat 2
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6128,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6129,0
va (VaSet
font "courier,12,0"
)
xt "112750,59600,119050,60900"
st "memDataIn"
blo "112750,60600"
tm "WireNameMgr"
)
)
on &18
)
*89 (Wire
uid 6130,0
shape (OrthoPolyLine
uid 6131,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,63000,114000,63000"
pts [
"110000,63000"
"114000,63000"
]
)
start &22
sat 1
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6136,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6137,0
va (VaSet
font "courier,12,0"
)
xt "112750,61600,120450,62900"
st "memDataOut"
blo "112750,62600"
tm "WireNameMgr"
)
)
on &19
)
*90 (Wire
uid 6770,0
shape (OrthoPolyLine
uid 6771,0
va (VaSet
vasetType 3
)
xt "62750,63000,66000,63000"
pts [
"62750,63000"
"66000,63000"
]
)
start &61
sat 32
eat 16
stc 0
st 0
si 0
tg (WTG
uid 6772,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6773,0
va (VaSet
font "courier,12,0"
)
xt "64750,61600,71050,62900"
st "flashCE_n"
blo "64750,62600"
tm "WireNameMgr"
)
)
on &26
)
*91 (Wire
uid 6776,0
shape (OrthoPolyLine
uid 6777,0
va (VaSet
vasetType 3
)
xt "62750,65000,77250,65000"
pts [
"62750,65000"
"77250,65000"
]
)
start &54
end &77
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 6778,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6779,0
va (VaSet
font "courier,12,0"
)
xt "64750,63600,69650,64900"
st "memWr_n"
blo "64750,64600"
tm "WireNameMgr"
)
)
on &20
)
*92 (Wire
uid 6782,0
shape (OrthoPolyLine
uid 6783,0
va (VaSet
vasetType 3
)
xt "62750,67000,77250,67000"
pts [
"62750,67000"
"77250,67000"
]
)
start &62
end &74
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 6784,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6785,0
va (VaSet
font "courier,12,0"
)
xt "64750,65600,69650,66900"
st "memOE_n"
blo "64750,66600"
tm "WireNameMgr"
)
)
on &27
)
*93 (Wire
uid 6794,0
shape (OrthoPolyLine
uid 6795,0
va (VaSet
vasetType 3
)
xt "62750,69000,77250,73000"
pts [
"62750,69000"
"70000,69000"
"70000,73000"
"77250,73000"
]
)
start &59
end &75
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 6796,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6797,0
va (VaSet
font "courier,12,0"
)
xt "64750,67600,70350,68900"
st "memRst_n"
blo "64750,68600"
tm "WireNameMgr"
)
)
on &45
)
*94 (Wire
uid 6800,0
shape (OrthoPolyLine
uid 6801,0
va (VaSet
vasetType 3
)
xt "62750,63000,88000,79000"
pts [
"62750,71000"
"68000,71000"
"68000,79000"
"88000,79000"
"88000,63000"
"86750,63000"
]
)
start &60
end &76
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 6802,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6803,0
va (VaSet
font "courier,12,0"
)
xt "64750,69600,70350,70900"
st "flashSTS"
blo "64750,70600"
tm "WireNameMgr"
)
)
on &28
)
*95 (Wire
uid 6806,0
shape (OrthoPolyLine
uid 6807,0
va (VaSet
vasetType 3
)
xt "74000,69000,77250,69000"
pts [
"77250,69000"
"74000,69000"
]
)
start &71
sat 32
eat 16
stc 0
st 0
si 0
tg (WTG
uid 6810,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6811,0
va (VaSet
font "courier,12,0"
)
xt "72000,67600,76200,68900"
st "BYTE_n"
blo "72000,68600"
tm "WireNameMgr"
)
)
on &29
)
*96 (Wire
uid 6814,0
shape (OrthoPolyLine
uid 6815,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62750,57000,66000,57000"
pts [
"62750,57000"
"66000,57000"
]
)
start &50
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6816,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6817,0
va (VaSet
font "courier,12,0"
)
xt "64750,55600,72450,56900"
st "memAddress"
blo "64750,56600"
tm "WireNameMgr"
)
)
on &30
)
*97 (Wire
uid 6827,0
shape (OrthoPolyLine
uid 6828,0
va (VaSet
vasetType 3
)
xt "70000,41000,74000,41000"
pts [
"70000,41000"
"74000,41000"
]
)
start &31
sat 2
eat 16
stc 0
st 0
si 0
tg (WTG
uid 6833,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6834,0
va (VaSet
font "courier,12,0"
)
xt "72000,39600,76200,40900"
st "BYTE_n"
blo "72000,40600"
tm "WireNameMgr"
)
)
on &29
)
*98 (Wire
uid 6924,0
shape (OrthoPolyLine
uid 6925,0
va (VaSet
vasetType 3
)
xt "34000,67000,45250,87000"
pts [
"45250,67000"
"34000,67000"
"34000,87000"
]
)
start &48
end &12
sat 32
eat 1
stc 0
st 0
si 0
tg (WTG
uid 6928,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6929,0
va (VaSet
font "courier,12,0"
)
xt "34000,65600,44500,66900"
st "flashDataValid"
blo "34000,66600"
tm "WireNameMgr"
)
)
on &36
)
*99 (Wire
uid 6932,0
shape (OrthoPolyLine
uid 6933,0
va (VaSet
vasetType 3
)
xt "30000,63000,45250,87000"
pts [
"45250,63000"
"30000,63000"
"30000,87000"
]
)
start &56
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 6936,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6937,0
va (VaSet
font "courier,12,0"
)
xt "38000,61600,42900,62900"
st "flashRd"
blo "38000,62600"
tm "WireNameMgr"
)
)
on &37
)
*100 (Wire
uid 6940,0
shape (OrthoPolyLine
uid 6941,0
va (VaSet
vasetType 3
)
xt "32000,65000,45250,87000"
pts [
"45250,65000"
"32000,65000"
"32000,87000"
]
)
start &57
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 6944,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6945,0
va (VaSet
font "courier,12,0"
)
xt "38250,63600,43150,64900"
st "flashWr"
blo "38250,64600"
tm "WireNameMgr"
)
)
on &38
)
*101 (Wire
uid 6948,0
shape (OrthoPolyLine
uid 6949,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "28000,61000,45250,87000"
pts [
"45250,61000"
"28000,61000"
"28000,87000"
]
)
start &51
end &12
sat 32
eat 2
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6952,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6953,0
va (VaSet
font "courier,12,0"
)
xt "34250,59600,43350,60900"
st "flashDataOut"
blo "34250,60600"
tm "WireNameMgr"
)
)
on &39
)
*102 (Wire
uid 6956,0
shape (OrthoPolyLine
uid 6957,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "26000,59000,45250,87000"
pts [
"45250,59000"
"26000,59000"
"26000,87000"
]
)
start &63
end &12
sat 32
eat 1
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6960,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6961,0
va (VaSet
font "courier,12,0"
)
xt "35250,57600,43650,58900"
st "flashDataIn"
blo "35250,58600"
tm "WireNameMgr"
)
)
on &40
)
*103 (Wire
uid 6964,0
shape (OrthoPolyLine
uid 6965,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "24000,57000,45250,87000"
pts [
"45250,57000"
"24000,57000"
"24000,87000"
]
)
start &49
end &12
sat 32
eat 2
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6968,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6969,0
va (VaSet
font "courier,12,0"
)
xt "37250,55600,43550,56900"
st "flashAddr"
blo "37250,56600"
tm "WireNameMgr"
)
)
on &41
)
*104 (Wire
uid 6986,0
shape (OrthoPolyLine
uid 6987,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "74000,61000,77250,61000"
pts [
"77250,61000"
"74000,61000"
]
)
start &70
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6990,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6991,0
va (VaSet
font "courier,12,0"
)
xt "74250,59600,74950,60900"
st "A"
blo "74250,60600"
tm "WireNameMgr"
)
)
on &42
)
*105 (Wire
uid 6996,0
shape (OrthoPolyLine
uid 6997,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "74000,63000,77250,63000"
pts [
"77250,63000"
"74000,63000"
]
)
start &72
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7000,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7001,0
va (VaSet
font "courier,12,0"
)
xt "73250,61600,74650,62900"
st "CE"
blo "73250,62600"
tm "WireNameMgr"
)
)
on &43
)
*106 (Wire
uid 7002,0
shape (OrthoPolyLine
uid 7003,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "50000,37000,54000,37000"
pts [
"54000,37000"
"50000,37000"
]
)
start &31
sat 1
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7008,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7009,0
va (VaSet
font "courier,12,0"
)
xt "45000,35600,52700,36900"
st "memAddress"
blo "45000,36600"
tm "WireNameMgr"
)
)
on &30
)
*107 (Wire
uid 7010,0
shape (OrthoPolyLine
uid 7011,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,37000,74250,37000"
pts [
"74250,37000"
"70000,37000"
]
)
end &31
sat 16
eat 2
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7016,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7017,0
va (VaSet
font "courier,12,0"
)
xt "72000,35600,72700,36900"
st "A"
blo "72000,36600"
tm "WireNameMgr"
)
)
on &42
)
*108 (Wire
uid 7018,0
shape (OrthoPolyLine
uid 7019,0
va (VaSet
vasetType 3
)
xt "50000,39000,54000,39000"
pts [
"54000,39000"
"50000,39000"
]
)
start &31
sat 1
eat 16
stc 0
st 0
si 0
tg (WTG
uid 7024,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7025,0
va (VaSet
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tm "WireNameMgr"
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uid 7026,0
shape (OrthoPolyLine
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start &31
sat 2
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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st "CE"
blo "72000,38600"
tm "WireNameMgr"
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)
on &43
)
*110 (Wire
uid 7036,0
shape (OrthoPolyLine
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va (VaSet
vasetType 3
)
xt "102000,67000,102000,69000"
pts [
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end &22
sat 16
eat 4
stc 0
st 0
si 0
tg (WTG
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
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tm "WireNameMgr"
)
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on &44
)
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uid 7305,0
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va (VaSet
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xt "38000,71000,45250,87000"
pts [
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start &64
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
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va (VaSet
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tm "WireNameMgr"
)
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on &68
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stg "VerticalLayoutStrategy"
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va (VaSet
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tm "PackageList"
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stg "VerticalLayoutStrategy"
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va (VaSet
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va (VaSet
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tm "BdCompilerDirectivesTextMgr"
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st "
Text
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tm "CommentText"
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Text
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tm "RequirementText"
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xt "0,0,20000,20000"
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text (Text
va (VaSet
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xt "1000,1000,3300,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
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)
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vasetType 1
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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blo "1500,3750"
tm "BdLibraryNameMgr"
)
*123 (Text
va (VaSet
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blo "1500,5150"
tm "BlkNameMgr"
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*124 (Text
va (VaSet
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st "I0"
blo "1500,6550"
tm "InstanceNameMgr"
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)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
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xt "1500,12550,1500,12550"
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header ""
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elements [
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va (VaSet
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xt "-600,0,8600,10000"
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ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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st "Library"
blo "-100,3800"
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*126 (Text
va (VaSet
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xt "-100,4000,5900,5000"
st "MWComponent"
blo "-100,4800"
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*127 (Text
va (VaSet
)
xt "-100,5000,500,6000"
st "I0"
blo "-100,5800"
tm "InstanceNameMgr"
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ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
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xt "-7100,1000,-7100,1000"
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header ""
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elements [
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pname "params"
ptn "String"
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visOptions (mwParamsVisibilityOptions
)
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xt "-850,0,8850,10000"
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ttg (MlTextGroup
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tm "BdLibraryNameMgr"
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va (VaSet
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xt "-350,3550,5150,4550"
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blo "-350,4350"
tm "CptNameMgr"
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va (VaSet
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st "I0"
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tm "InstanceNameMgr"
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matrix (Matrix
text (MLText
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xt "-7350,550,-7350,550"
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header ""
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elements [
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va (VaSet
vasetType 1
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xt "-1350,0,9350,10000"
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ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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)
xt "-850,2550,1450,3550"
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blo "-850,3350"
)
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va (VaSet
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xt "-850,3550,5250,4550"
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blo "-850,4350"
)
*133 (Text
va (VaSet
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st "I0"
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tm "InstanceNameMgr"
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ga (GenericAssociation
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matrix (Matrix
text (MLText
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xt "-7850,550,-7850,550"
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header ""
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ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "-1600,3550,5500,4550"
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blo "-1600,4350"
)
*136 (Text
va (VaSet
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xt "-1600,4550,-1000,5550"
st "I0"
blo "-1600,5350"
tm "InstanceNameMgr"
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ga (GenericAssociation
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matrix (Matrix
text (MLText
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xt "-8600,550,-8600,550"
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header ""
)
elements [
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entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
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vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
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xt "0,0,8000,10000"
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ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "2950,3400,4150,4400"
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blo "2950,4200"
tm "HdlTextNameMgr"
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*138 (Text
va (VaSet
)
xt "2950,4400,3350,5400"
st "1"
blo "2950,5200"
tm "HdlTextNumberMgr"
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]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
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text (MLText
va (VaSet
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xt "200,200,2200,1100"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
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blo "-300,300"
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)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
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"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
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)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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ro 270
xt "-2000,-375,-500,375"
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(Line
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ro 270
xt "-500,0,0,0"
pts [
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)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "-2875,-375,-2875,-375"
ju 2
blo "-2875,-375"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "-2875,-375,-2875,-375"
ju 2
blo "-2875,-375"
tm "SignalTypeMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
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]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "2875,-375,2875,-375"
blo "2875,-375"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "2875,-375,2875,-375"
blo "2875,-375"
tm "SignalTypeMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
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)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "3000,500,3000,500"
blo "3000,500"
tm "SignalTypeMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
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sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
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)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "3000,500,3000,500"
blo "3000,500"
tm "SignalTypeMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "courier,12,0"
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xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
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)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "courier,12,0"
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xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineStyle 3
lineWidth 2
)
pts [
"0,0"
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]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
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xt "0,0,5100,1400"
st "bundle0"
blo "0,1200"
tm "BundleNameMgr"
)
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va (VaSet
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st "()"
tm "BundleContentsMgr"
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bundleNet &0
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vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
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xt "0,0,10000,12000"
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portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "0,0,6300,1300"
st "Auto list"
)
second (MLText
va (VaSet
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)
xt "0,1400,12600,2700"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
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va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 2
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xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1400,17400,-400"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
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)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
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va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1750"
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num (Text
va (VaSet
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xt "200,300,600,1300"
st "1"
blo "200,1100"
tm "FrameSeqNumMgr"
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decls (MlTextGroup
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stg "VerticalLayoutStrategy"
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blo "11800,21000"
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tm "BdFrameDeclTextMgr"
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xt "0,0,20000,20000"
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title (TextAssociate
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xt "50,50,1050,1750"
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num (Text
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tm "FrameSeqNumMgr"
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stg "VerticalLayoutStrategy"
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tm "BdFrameDeclTextMgr"
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tg (CPTG
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xt "0,750,2600,2150"
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blo "0,1950"
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thePort (LogicalPort
decl (Decl
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t ""
o 0
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)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
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vasetType 1
fg "65535,65535,65535"
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xt "0,0,750,750"
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tg (CPTG
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stg "VerticalLayoutStrategy"
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xt "0,750,2600,2150"
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blo "0,1950"
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thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
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defaultDeclText (MLText
va (VaSet
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archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "courier,10,1"
)
xt "-7000,26200,1600,27400"
st "Declarations"
blo "-7000,27200"
)
portLabel (Text
uid 3,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "-7000,27400,-2800,28600"
st "Ports:"
blo "-7000,28400"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "courier,10,1"
)
xt "-7000,27400,-1000,28600"
st "Pre User:"
blo "-7000,28400"
)
preUserText (MLText
uid 5,0
va (VaSet
)
xt "-5000,28600,18400,30600"
st "constant addressBitNb: positive := 24;
constant dataBitNb: positive := 16;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "-7000,27400,4000,28600"
st "Diagram Signals:"
blo "-7000,28400"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "-7000,27400,300,28600"
st "Post User:"
blo "-7000,28400"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
)
xt "-5000,41800,-5000,41800"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 97,0
usingSuid 1
emptyRow *143 (LEmptyRow
)
uid 3310,0
optionalChildren [
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)
*145 (TitleRowHdr
)
*146 (FilterRowHdr
)
*147 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*148 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*149 (GroupColHdr
tm "GroupColHdrMgr"
)
*150 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*151 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*152 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*153 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*154 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*155 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*156 (LeafLogPort
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m 4
decl (Decl
n "reset"
t "std_ulogic"
o 23
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)
)
uid 5622,0
)
*157 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clock"
t "std_ulogic"
o 5
suid 56,0
)
)
uid 5624,0
)
*158 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
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o 17
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)
)
uid 5939,0
)
*159 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
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t "std_ulogic_vector"
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o 18
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)
)
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)
*160 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
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o 22
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)
)
uid 6040,0
)
*161 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "DQ"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 75,0
)
)
uid 6056,0
)
*162 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashCE_n"
t "std_ulogic"
o 7
suid 79,0
)
)
uid 6786,0
)
*163 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memOE_n"
t "std_ulogic"
o 19
suid 81,0
)
)
uid 6790,0
)
*164 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashSTS"
t "std_ulogic"
o 13
suid 83,0
)
)
uid 6837,0
)
*165 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "BYTE_n"
t "std_ulogic"
o 2
suid 84,0
)
)
uid 6839,0
)
*166 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memAddress"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 15
suid 85,0
)
)
uid 6841,0
)
*167 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashEn"
t "std_ulogic"
o 11
suid 86,0
)
)
uid 6970,0
)
*168 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashDataValid"
t "std_ulogic"
o 10
suid 87,0
)
)
uid 6972,0
)
*169 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashRd"
t "std_ulogic"
o 12
suid 88,0
)
)
uid 6974,0
)
*170 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashWr"
t "std_ulogic"
o 14
suid 89,0
)
)
uid 6976,0
)
*171 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 9
suid 90,0
)
)
uid 6978,0
)
*172 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 8
suid 91,0
)
)
uid 6980,0
)
*173 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashAddr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 6
suid 92,0
)
)
uid 6982,0
)
*174 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "A"
t "unsigned"
b "(23 DOWNTO 0)"
o 1
suid 93,0
)
)
uid 6992,0
)
*175 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CE"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 3
suid 94,0
)
)
uid 7034,0
)
*176 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memWrDelayed_n"
t "std_ulogic"
o 21
suid 95,0
)
)
uid 7046,0
)
*177 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memRst_n"
t "std_ulogic"
o 20
suid 96,0
)
)
uid 7127,0
)
*178 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memBusEn_n"
t "std_ulogic"
o 16
suid 97,0
)
)
uid 7311,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 3323,0
optionalChildren [
*179 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *180 (MRCItem
litem &143
pos 23
dimension 20
)
uid 3325,0
optionalChildren [
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litem &144
pos 0
dimension 20
uid 3326,0
)
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pos 1
dimension 23
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)
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litem &146
pos 2
hidden 1
dimension 20
uid 3328,0
)
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litem &156
pos 0
dimension 20
uid 5623,0
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litem &157
pos 1
dimension 20
uid 5625,0
)
*186 (MRCItem
litem &158
pos 2
dimension 20
uid 5940,0
)
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litem &159
pos 3
dimension 20
uid 5942,0
)
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litem &160
pos 4
dimension 20
uid 6041,0
)
*189 (MRCItem
litem &161
pos 5
dimension 20
uid 6057,0
)
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litem &162
pos 6
dimension 20
uid 6787,0
)
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litem &163
pos 7
dimension 20
uid 6791,0
)
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litem &164
pos 8
dimension 20
uid 6838,0
)
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litem &165
pos 9
dimension 20
uid 6840,0
)
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litem &166
pos 10
dimension 20
uid 6842,0
)
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litem &167
pos 11
dimension 20
uid 6971,0
)
*196 (MRCItem
litem &168
pos 12
dimension 20
uid 6973,0
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litem &169
pos 13
dimension 20
uid 6975,0
)
*198 (MRCItem
litem &170
pos 14
dimension 20
uid 6977,0
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litem &171
pos 15
dimension 20
uid 6979,0
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*200 (MRCItem
litem &172
pos 16
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uid 6981,0
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uid 6983,0
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litem &174
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uid 6993,0
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litem &175
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uid 7035,0
)
*204 (MRCItem
litem &176
pos 20
dimension 20
uid 7047,0
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*205 (MRCItem
litem &177
pos 21
dimension 20
uid 7128,0
)
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litem &178
pos 22
dimension 20
uid 7312,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
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uid 3329,0
optionalChildren [
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litem &147
pos 0
dimension 20
uid 3330,0
)
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litem &149
pos 1
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uid 3331,0
)
*209 (MRCItem
litem &150
pos 2
dimension 100
uid 3332,0
)
*210 (MRCItem
litem &151
pos 3
dimension 50
uid 3333,0
)
*211 (MRCItem
litem &152
pos 4
dimension 100
uid 3334,0
)
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litem &153
pos 5
dimension 100
uid 3335,0
)
*213 (MRCItem
litem &154
pos 6
dimension 50
uid 3336,0
)
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litem &155
pos 7
dimension 80
uid 3337,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 3324,0
vaOverrides [
]
)
]
)
uid 3309,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *215 (LEmptyRow
)
uid 3339,0
optionalChildren [
*216 (RefLabelRowHdr
)
*217 (TitleRowHdr
)
*218 (FilterRowHdr
)
*219 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*220 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*221 (GroupColHdr
tm "GroupColHdrMgr"
)
*222 (NameColHdr
tm "GenericNameColHdrMgr"
)
*223 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*224 (InitColHdr
tm "GenericValueColHdrMgr"
)
*225 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*226 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 3351,0
optionalChildren [
*227 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *228 (MRCItem
litem &215
pos 0
dimension 20
)
uid 3353,0
optionalChildren [
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litem &216
pos 0
dimension 20
uid 3354,0
)
*230 (MRCItem
litem &217
pos 1
dimension 23
uid 3355,0
)
*231 (MRCItem
litem &218
pos 2
hidden 1
dimension 20
uid 3356,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
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uid 3357,0
optionalChildren [
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litem &219
pos 0
dimension 20
uid 3358,0
)
*233 (MRCItem
litem &221
pos 1
dimension 50
uid 3359,0
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*234 (MRCItem
litem &222
pos 2
dimension 100
uid 3360,0
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*235 (MRCItem
litem &223
pos 3
dimension 100
uid 3361,0
)
*236 (MRCItem
litem &224
pos 4
dimension 50
uid 3362,0
)
*237 (MRCItem
litem &225
pos 5
dimension 50
uid 3363,0
)
*238 (MRCItem
litem &226
pos 6
dimension 80
uid 3364,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 3352,0
vaOverrides [
]
)
]
)
uid 3338,0
type 1
)
activeModelName "BlockDiag"
)