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27 lines
562 B
VHDL
27 lines
562 B
VHDL
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LIBRARY Common;
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USE Common.CommonLib.all;
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ARCHITECTURE RTL OF freqDivider IS
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signal count: unsigned(requiredBitNb(divideValue)-1 downto 0);
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BEGIN
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countEndlessly: process(reset, clock)
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begin
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if reset = '1' then
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count <= (others => '0');
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elsif rising_edge(clock) then
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if count = 0 then
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count <= to_unsigned(divideValue-1, count'length);
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else
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count <= count-1 ;
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end if;
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end if;
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end process countEndlessly;
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enable <= '1' after delay when count = 0
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else '0' after delay;
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END ARCHITECTURE RTL;
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