Cursor/Libs/Memory_test/hds/bram_tb/struct.bd

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
]
instances [
(Instance
name "I1"
duLibraryName "memory_test"
duName "bram_tester"
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
mwi 0
uid 1774,0
)
(Instance
name "I0"
duLibraryName "memory"
duName "bramDualportWritefirst"
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "initFile"
type "string"
value "\"U:/ELN_board/Simulation/bramInit.txt\""
)
]
mwi 0
uid 5605,0
)
]
libraryRefs [
"ieee"
]
)
version "31.1"
appVersion "2018.1 (Build 12)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl"
)
(vvPair
variable "HDSDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
)
(vvPair
variable "SideDataDesignDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tb/struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tb/struct.bd.user"
)
(vvPair
variable "SourceDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tb"
)
(vvPair
variable "d_logical"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tb"
)
(vvPair
variable "date"
value "08/28/19"
)
(vvPair
variable "day"
value "Wed"
)
(vvPair
variable "day_long"
value "Wednesday"
)
(vvPair
variable "dd"
value "28"
)
(vvPair
variable "entity_name"
value "bram_tb"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "francois"
)
(vvPair
variable "graphical_source_date"
value "08/28/19"
)
(vvPair
variable "graphical_source_group"
value "francois"
)
(vvPair
variable "graphical_source_host"
value "Aphelia"
)
(vvPair
variable "graphical_source_time"
value "13:45:28"
)
(vvPair
variable "group"
value "francois"
)
(vvPair
variable "host"
value "Aphelia"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "Memory_test"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Libs/Memory_test/work"
)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "bram_tb"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tb/struct.bd"
)
(vvPair
variable "p_logical"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tb/struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_ISEPath"
value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\EDA\\Modelsim\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "13:45:28"
)
(vvPair
variable "unit"
value "bram_tb"
)
(vvPair
variable "user"
value "francois"
)
(vvPair
variable "version"
value "2018.1 (Build 12)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2019"
)
(vvPair
variable "yy"
value "19"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 198,0
optionalChildren [
*1 (Grouping
uid 1487,0
optionalChildren [
*2 (CommentText
uid 1489,0
shape (Rectangle
uid 1490,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "72000,77000,91000,79000"
)
oxt "45000,22000,64000,24000"
text (MLText
uid 1491,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "72200,77500,87800,78500"
st "
<enter project name here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 18600
)
position 1
ignorePrefs 1
)
*3 (CommentText
uid 1492,0
shape (Rectangle
uid 1493,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "40000,77000,66000,79000"
)
oxt "13000,22000,39000,24000"
text (MLText
uid 1494,0
va (VaSet
fg "32768,0,0"
font "courier,12,1"
)
xt "47750,77350,58250,78650"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 25600
)
position 1
ignorePrefs 1
)
*4 (CommentText
uid 1495,0
shape (Rectangle
uid 1496,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "45000,83000,66000,85000"
)
oxt "18000,28000,39000,30000"
text (MLText
uid 1497,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "45200,83500,61400,84500"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*5 (CommentText
uid 1498,0
shape (Rectangle
uid 1499,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "66000,77000,72000,79000"
)
oxt "39000,22000,45000,24000"
text (MLText
uid 1500,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "66200,77500,71000,78500"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 5600
)
position 1
ignorePrefs 1
)
*6 (CommentText
uid 1501,0
shape (Rectangle
uid 1502,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "45000,79000,66000,81000"
)
oxt "18000,24000,39000,26000"
text (MLText
uid 1503,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "45200,79500,61400,80500"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*7 (CommentText
uid 1504,0
shape (Rectangle
uid 1505,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "40000,79000,45000,81000"
)
oxt "13000,24000,18000,26000"
text (MLText
uid 1506,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "40200,79500,43800,80500"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
*8 (CommentText
uid 1507,0
shape (Rectangle
uid 1508,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "40000,81000,45000,83000"
)
oxt "13000,26000,18000,28000"
text (MLText
uid 1509,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "40200,81500,43200,82500"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
*9 (CommentText
uid 1510,0
shape (Rectangle
uid 1511,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "66000,79000,91000,85000"
)
oxt "39000,24000,64000,30000"
text (MLText
uid 1512,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "66200,79200,79400,80200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 5600
visibleWidth 24600
)
ignorePrefs 1
)
*10 (CommentText
uid 1513,0
shape (Rectangle
uid 1514,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "45000,81000,66000,83000"
)
oxt "18000,26000,39000,28000"
text (MLText
uid 1515,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "45200,81500,61400,82500"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*11 (CommentText
uid 1516,0
shape (Rectangle
uid 1517,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "40000,83000,45000,85000"
)
oxt "13000,28000,18000,30000"
text (MLText
uid 1518,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "40200,83500,44400,84500"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
uid 1488,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 1
)
xt "40000,77000,91000,85000"
)
oxt "13000,22000,64000,30000"
)
*12 (Blk
uid 1774,0
shape (Rectangle
uid 1775,0
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "11000,58000,71000,66000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1776,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*13 (Text
uid 1777,0
va (VaSet
font "courier,12,1"
)
xt "11600,65900,22200,67300"
st "memory_test"
blo "11600,67100"
tm "BdLibraryNameMgr"
)
*14 (Text
uid 1778,0
va (VaSet
font "courier,12,1"
)
xt "11600,67300,21600,68700"
st "bram_tester"
blo "11600,68500"
tm "BlkNameMgr"
)
*15 (Text
uid 1779,0
va (VaSet
font "courier,12,1"
)
xt "11600,68700,14000,70100"
st "I1"
blo "11600,69900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1780,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1781,0
text (MLText
uid 1782,0
va (VaSet
font "courier,9,0"
)
xt "11000,70800,34000,72600"
st "addressBitNb = addressBitNb    ( positive )  
dataBitNb    = dataBitNb       ( positive )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
)
)
*16 (Net
uid 5380,0
lang 11
decl (Decl
n "clockA"
t "std_ulogic"
o 3
suid 55,0
)
declText (MLText
uid 5381,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,14500,900"
st "SIGNAL clockA   : std_ulogic
"
)
)
*17 (Net
uid 5388,0
lang 11
decl (Decl
n "enA"
t "std_ulogic"
o 9
suid 56,0
)
declText (MLText
uid 5389,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,14500,900"
st "SIGNAL enA      : std_ulogic
"
)
)
*18 (Net
uid 5396,0
lang 11
decl (Decl
n "writeEnA"
t "std_ulogic"
o 11
suid 57,0
)
declText (MLText
uid 5397,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,14500,900"
st "SIGNAL writeEnA : std_ulogic
"
)
)
*19 (Net
uid 5440,0
lang 11
decl (Decl
n "clockB"
t "std_ulogic"
o 4
suid 61,0
)
declText (MLText
uid 5441,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,14500,900"
st "SIGNAL clockB   : std_ulogic
"
)
)
*20 (Net
uid 5448,0
lang 11
decl (Decl
n "enB"
t "std_ulogic"
o 10
suid 62,0
)
declText (MLText
uid 5449,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,14500,900"
st "SIGNAL enB      : std_ulogic
"
)
)
*21 (Net
uid 5456,0
lang 11
decl (Decl
n "writeEnB"
t "std_ulogic"
o 12
suid 63,0
)
declText (MLText
uid 5457,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,14500,900"
st "SIGNAL writeEnB : std_ulogic
"
)
)
*22 (SaComponent
uid 5605,0
optionalChildren [
*23 (CptPort
uid 5557,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5558,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32250,47625,33000,48375"
)
tg (CPTG
uid 5559,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5560,0
va (VaSet
)
xt "34000,47500,36600,48500"
st "clockA"
blo "34000,48300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "clockA"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*24 (CptPort
uid 5561,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5562,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32250,45625,33000,46375"
)
tg (CPTG
uid 5563,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5564,0
va (VaSet
)
xt "34000,45500,35700,46500"
st "enA"
blo "34000,46300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "enA"
t "std_ulogic"
o 2
suid 3,0
)
)
)
*25 (CptPort
uid 5565,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5566,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32250,41625,33000,42375"
)
tg (CPTG
uid 5567,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5568,0
va (VaSet
)
xt "34000,41500,37400,42500"
st "writeEnA"
blo "34000,42300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "writeEnA"
t "std_ulogic"
o 3
suid 4,0
)
)
)
*26 (CptPort
uid 5569,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5570,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32250,35625,33000,36375"
)
tg (CPTG
uid 5571,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5572,0
va (VaSet
)
xt "34000,35500,37600,36500"
st "addressA"
blo "34000,36300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "addressA"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 4
suid 5,0
)
)
)
*27 (CptPort
uid 5573,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5574,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32250,39625,33000,40375"
)
tg (CPTG
uid 5575,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5576,0
va (VaSet
)
xt "34000,39500,36900,40500"
st "dataInA"
blo "34000,40300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "dataInA"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 5
suid 6,0
)
)
)
*28 (CptPort
uid 5577,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5578,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32250,37625,33000,38375"
)
tg (CPTG
uid 5579,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5580,0
va (VaSet
)
xt "34000,37500,37500,38500"
st "dataOutA"
blo "34000,38300"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "dataOutA"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
posAdd 0
o 6
suid 7,0
)
)
)
*29 (CptPort
uid 5581,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5582,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,47625,49750,48375"
)
tg (CPTG
uid 5583,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5584,0
va (VaSet
)
xt "45400,47500,48000,48500"
st "clockB"
ju 2
blo "48000,48300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "clockB"
t "std_ulogic"
o 7
suid 8,0
)
)
)
*30 (CptPort
uid 5585,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5586,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,45625,49750,46375"
)
tg (CPTG
uid 5587,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5588,0
va (VaSet
)
xt "46300,45500,48000,46500"
st "enB"
ju 2
blo "48000,46300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "enB"
t "std_ulogic"
o 8
suid 10,0
)
)
)
*31 (CptPort
uid 5589,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5590,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,41625,49750,42375"
)
tg (CPTG
uid 5591,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5592,0
va (VaSet
)
xt "44600,41500,48000,42500"
st "writeEnB"
ju 2
blo "48000,42300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "writeEnB"
t "std_ulogic"
o 9
suid 11,0
)
)
)
*32 (CptPort
uid 5593,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5594,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,35625,49750,36375"
)
tg (CPTG
uid 5595,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5596,0
va (VaSet
)
xt "44400,35500,48000,36500"
st "addressB"
ju 2
blo "48000,36300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "addressB"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 10
suid 12,0
)
)
)
*33 (CptPort
uid 5597,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5598,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,39625,49750,40375"
)
tg (CPTG
uid 5599,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5600,0
va (VaSet
)
xt "45100,39500,48000,40500"
st "dataInB"
ju 2
blo "48000,40300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "dataInB"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 11
suid 13,0
)
)
)
*34 (CptPort
uid 5601,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5602,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49000,37625,49750,38375"
)
tg (CPTG
uid 5603,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5604,0
va (VaSet
)
xt "44500,37500,48000,38500"
st "dataOutB"
ju 2
blo "48000,38300"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "dataOutB"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 12
suid 14,0
)
)
)
]
shape (Rectangle
uid 5606,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "33000,32000,49000,50000"
)
oxt "39000,11000,55000,29000"
ttg (MlTextGroup
uid 5607,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*35 (Text
uid 5608,0
va (VaSet
font "courier,8,1"
)
xt "33200,50000,36500,51000"
st "memory"
blo "33200,50800"
tm "BdLibraryNameMgr"
)
*36 (Text
uid 5609,0
va (VaSet
font "courier,8,1"
)
xt "33200,51000,43200,52000"
st "bramDualportWritefirst"
blo "33200,51800"
tm "CptNameMgr"
)
*37 (Text
uid 5610,0
va (VaSet
font "courier,8,1"
)
xt "33200,52000,34200,53000"
st "I0"
blo "33200,52800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5611,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5612,0
text (MLText
uid 5613,0
va (VaSet
font "courier,8,0"
)
xt "33000,53000,69000,55700"
st "addressBitNb = addressBitNb                              ( positive )  
dataBitNb    = dataBitNb                                 ( positive )  
initFile     = \"U:/ELN_board/Simulation/bramInit.txt\"    ( string   )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "initFile"
type "string"
value "\"U:/ELN_board/Simulation/bramInit.txt\""
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
sIVOD 1
)
archFileType "UNKNOWN"
)
*38 (Net
uid 5614,0
lang 11
decl (Decl
n "dataInB"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 6
suid 67,0
)
declText (MLText
uid 5615,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,29000,900"
st "SIGNAL dataInB  : std_ulogic_vector(dataBitNb-1 DOWNTO 0)
"
)
)
*39 (Net
uid 5622,0
lang 11
decl (Decl
n "dataOutB"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 8
suid 68,0
)
declText (MLText
uid 5623,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,29000,900"
st "SIGNAL dataOutB : std_ulogic_vector(dataBitNb-1 DOWNTO 0)
"
)
)
*40 (Net
uid 5630,0
lang 11
decl (Decl
n "addressB"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 2
suid 69,0
)
declText (MLText
uid 5631,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,30500,900"
st "SIGNAL addressB : std_ulogic_vector(addressBitNb-1 DOWNTO 0)
"
)
)
*41 (Net
uid 5638,0
lang 11
decl (Decl
n "dataInA"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 5
suid 70,0
)
declText (MLText
uid 5639,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,29000,900"
st "SIGNAL dataInA  : std_ulogic_vector(dataBitNb-1 DOWNTO 0)
"
)
)
*42 (Net
uid 5646,0
lang 11
decl (Decl
n "dataOutA"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
posAdd 0
o 7
suid 71,0
)
declText (MLText
uid 5647,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,29000,900"
st "SIGNAL dataOutA : std_ulogic_vector(dataBitNb-1 DOWNTO 0)
"
)
)
*43 (Net
uid 5654,0
lang 11
decl (Decl
n "addressA"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 1
suid 72,0
)
declText (MLText
uid 5655,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,30500,900"
st "SIGNAL addressA : std_ulogic_vector(addressBitNb-1 DOWNTO 0)
"
)
)
*44 (Wire
uid 5382,0
shape (OrthoPolyLine
uid 5383,0
va (VaSet
vasetType 3
)
xt "31000,48000,32250,58000"
pts [
"32250,48000"
"31000,48000"
"31000,58000"
]
)
start &23
end &12
sat 32
eat 2
stc 0
st 0
sf 1
tg (WTG
uid 5386,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5387,0
va (VaSet
font "courier,12,0"
)
xt "26250,46600,30450,47900"
st "clockA"
blo "26250,47600"
tm "WireNameMgr"
)
)
on &16
)
*45 (Wire
uid 5390,0
shape (OrthoPolyLine
uid 5391,0
va (VaSet
vasetType 3
)
xt "29000,46000,32250,58000"
pts [
"32250,46000"
"29000,46000"
"29000,58000"
]
)
start &24
end &12
sat 32
eat 2
stc 0
st 0
sf 1
tg (WTG
uid 5394,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5395,0
va (VaSet
font "courier,12,0"
)
xt "28250,44600,30350,45900"
st "enA"
blo "28250,45600"
tm "WireNameMgr"
)
)
on &17
)
*46 (Wire
uid 5398,0
shape (OrthoPolyLine
uid 5399,0
va (VaSet
vasetType 3
)
xt "25000,42000,32250,58000"
pts [
"32250,42000"
"25000,42000"
"25000,58000"
]
)
start &25
end &12
sat 32
eat 2
stc 0
st 0
sf 1
tg (WTG
uid 5402,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5403,0
va (VaSet
font "courier,12,0"
)
xt "25250,40600,30850,41900"
st "writeEnA"
blo "25250,41600"
tm "WireNameMgr"
)
)
on &18
)
*47 (Wire
uid 5442,0
shape (OrthoPolyLine
uid 5443,0
va (VaSet
vasetType 3
)
xt "49750,48000,51000,58000"
pts [
"49750,48000"
"51000,48000"
"51000,58000"
]
)
start &29
end &12
sat 32
eat 2
stc 0
st 0
sf 1
tg (WTG
uid 5446,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5447,0
va (VaSet
font "courier,12,0"
)
xt "51750,46600,55950,47900"
st "clockB"
blo "51750,47600"
tm "WireNameMgr"
)
)
on &19
)
*48 (Wire
uid 5450,0
shape (OrthoPolyLine
uid 5451,0
va (VaSet
vasetType 3
)
xt "49750,46000,53000,58000"
pts [
"49750,46000"
"53000,46000"
"53000,58000"
]
)
start &30
end &12
sat 32
eat 2
stc 0
st 0
sf 1
tg (WTG
uid 5454,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5455,0
va (VaSet
font "courier,12,0"
)
xt "51750,44600,53850,45900"
st "enB"
blo "51750,45600"
tm "WireNameMgr"
)
)
on &20
)
*49 (Wire
uid 5458,0
shape (OrthoPolyLine
uid 5459,0
va (VaSet
vasetType 3
)
xt "49750,42000,57000,58000"
pts [
"49750,42000"
"57000,42000"
"57000,58000"
]
)
start &31
end &12
sat 32
eat 2
stc 0
st 0
sf 1
tg (WTG
uid 5462,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5463,0
va (VaSet
font "courier,12,0"
)
xt "51750,40600,57350,41900"
st "writeEnB"
blo "51750,41600"
tm "WireNameMgr"
)
)
on &21
)
*50 (Wire
uid 5616,0
shape (OrthoPolyLine
uid 5617,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "49750,40000,59000,58000"
pts [
"49750,40000"
"59000,40000"
"59000,58000"
]
)
start &33
end &12
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
tg (WTG
uid 5620,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5621,0
va (VaSet
font "courier,12,0"
)
xt "51750,38600,56650,39900"
st "dataInB"
blo "51750,39600"
tm "WireNameMgr"
)
)
on &38
)
*51 (Wire
uid 5624,0
shape (OrthoPolyLine
uid 5625,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "49750,38000,61000,58000"
pts [
"49750,38000"
"61000,38000"
"61000,58000"
]
)
start &34
end &12
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
tg (WTG
uid 5628,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5629,0
va (VaSet
font "courier,12,0"
)
xt "51750,36600,57350,37900"
st "dataOutB"
blo "51750,37600"
tm "WireNameMgr"
)
)
on &39
)
*52 (Wire
uid 5632,0
shape (OrthoPolyLine
uid 5633,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "49750,36000,63000,58000"
pts [
"49750,36000"
"63000,36000"
"63000,58000"
]
)
start &32
end &12
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
tg (WTG
uid 5636,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5637,0
va (VaSet
font "courier,12,0"
)
xt "51750,34600,57350,35900"
st "addressB"
blo "51750,35600"
tm "WireNameMgr"
)
)
on &40
)
*53 (Wire
uid 5640,0
shape (OrthoPolyLine
uid 5641,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "23000,40000,32250,58000"
pts [
"32250,40000"
"23000,40000"
"23000,58000"
]
)
start &27
end &12
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
tg (WTG
uid 5644,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5645,0
va (VaSet
font "courier,12,0"
)
xt "25250,38600,30150,39900"
st "dataInA"
blo "25250,39600"
tm "WireNameMgr"
)
)
on &41
)
*54 (Wire
uid 5648,0
shape (OrthoPolyLine
uid 5649,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,38000,32250,58000"
pts [
"32250,38000"
"21000,38000"
"21000,58000"
]
)
start &28
end &12
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
tg (WTG
uid 5652,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5653,0
va (VaSet
font "courier,12,0"
)
xt "24250,36600,29850,37900"
st "dataOutA"
blo "24250,37600"
tm "WireNameMgr"
)
)
on &42
)
*55 (Wire
uid 5656,0
shape (OrthoPolyLine
uid 5657,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "19000,36000,32250,58000"
pts [
"32250,36000"
"19000,36000"
"19000,58000"
]
)
start &26
end &12
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
tg (WTG
uid 5660,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5661,0
va (VaSet
font "courier,12,0"
)
xt "24250,34600,29850,35900"
st "addressA"
blo "24250,35600"
tm "WireNameMgr"
)
)
on &43
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "32768,32768,32768"
)
packageList *56 (PackageList
uid 187,0
stg "VerticalLayoutStrategy"
textVec [
*57 (Text
uid 1297,0
va (VaSet
font "courier,12,0"
)
xt "-7000,19600,2500,21000"
st "Package List"
blo "-7000,20800"
)
*58 (MLText
uid 1298,0
va (VaSet
)
xt "-7000,21000,11600,24000"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 190,0
stg "VerticalLayoutStrategy"
textVec [
*59 (Text
uid 191,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "20000,0,31000,1200"
st "Compiler Directives"
blo "20000,1000"
)
*60 (Text
uid 192,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "20000,1400,33000,2600"
st "Pre-module directives:"
blo "20000,2400"
)
*61 (MLText
uid 193,0
va (VaSet
isHidden 1
)
xt "20000,2800,32000,4800"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*62 (Text
uid 194,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "20000,5600,33500,6800"
st "Post-module directives:"
blo "20000,6600"
)
*63 (MLText
uid 195,0
va (VaSet
isHidden 1
)
xt "20000,7000,20000,7000"
tm "BdCompilerDirectivesTextMgr"
)
*64 (Text
uid 196,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "20000,7200,33200,8400"
st "End-module directives:"
blo "20000,8200"
)
*65 (MLText
uid 197,0
va (VaSet
isHidden 1
)
xt "20000,1200,20000,1200"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "7,31,1392,967"
viewArea "-8439,18143,93001,87220"
cachedDiagramExtent "-7000,0,91000,85000"
pageSetupInfo (PageSetupInfo
ptrCmd "Generic PostScript Printer,winspool,"
fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
toPrinter 1
xMargin 48
yMargin 48
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "Letter (8.5\" x 11\")"
windowsPaperName "A4"
scale 75
titlesVisible 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "-7000,19000"
lastUid 5767,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2600,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "courier,8,0"
)
xt "450,2150,1450,3050"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
)
xt "1000,1000,3300,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*66 (Text
va (VaSet
font "courier,12,1"
)
xt "1500,2550,7900,3950"
st "<library>"
blo "1500,3750"
tm "BdLibraryNameMgr"
)
*67 (Text
va (VaSet
font "courier,12,1"
)
xt "1500,3950,7000,5350"
st "<block>"
blo "1500,5150"
tm "BlkNameMgr"
)
*68 (Text
va (VaSet
font "courier,12,1"
)
xt "1500,5350,3000,6750"
st "I0"
blo "1500,6550"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "1500,12550,1500,12550"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-600,0,8600,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*69 (Text
va (VaSet
)
xt "-100,3000,2200,4000"
st "Library"
blo "-100,3800"
)
*70 (Text
va (VaSet
)
xt "-100,4000,5900,5000"
st "MWComponent"
blo "-100,4800"
)
*71 (Text
va (VaSet
)
xt "-100,5000,500,6000"
st "I0"
blo "-100,5800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "-7100,1000,-7100,1000"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-850,0,8850,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*72 (Text
va (VaSet
)
xt "-350,2550,1950,3550"
st "Library"
blo "-350,3350"
tm "BdLibraryNameMgr"
)
*73 (Text
va (VaSet
)
xt "-350,3550,5150,4550"
st "SaComponent"
blo "-350,4350"
tm "CptNameMgr"
)
*74 (Text
va (VaSet
)
xt "-350,4550,250,5550"
st "I0"
blo "-350,5350"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "-7350,550,-7350,550"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-1350,0,9350,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*75 (Text
va (VaSet
)
xt "-850,2550,1450,3550"
st "Library"
blo "-850,3350"
)
*76 (Text
va (VaSet
)
xt "-850,3550,5250,4550"
st "VhdlComponent"
blo "-850,4350"
)
*77 (Text
va (VaSet
)
xt "-850,4550,-250,5550"
st "I0"
blo "-850,5350"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "-7850,550,-7850,550"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-2100,0,10100,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*78 (Text
va (VaSet
)
xt "-1600,2550,700,3550"
st "Library"
blo "-1600,3350"
)
*79 (Text
va (VaSet
)
xt "-1600,3550,5500,4550"
st "VerilogComponent"
blo "-1600,4350"
)
*80 (Text
va (VaSet
)
xt "-1600,4550,-1000,5550"
st "I0"
blo "-1600,5350"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "-8600,550,-8600,550"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*81 (Text
va (VaSet
)
xt "2950,3400,4150,4400"
st "eb1"
blo "2950,4200"
tm "HdlTextNameMgr"
)
*82 (Text
va (VaSet
)
xt "2950,4400,3350,5400"
st "1"
blo "2950,5200"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
font "courier,9,0"
)
xt "200,200,2200,1100"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "-2875,-375,-2875,-375"
ju 2
blo "-2875,-375"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "-2875,-375,-2875,-375"
ju 2
blo "-2875,-375"
tm "SignalTypeMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "2875,-375,2875,-375"
blo "2875,-375"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "2875,-375,2875,-375"
blo "2875,-375"
tm "SignalTypeMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "3000,500,3000,500"
blo "3000,500"
tm "SignalTypeMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "3000,500,3000,500"
blo "3000,500"
tm "SignalTypeMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineStyle 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
font "courier,12,0"
)
xt "0,0,5100,1400"
st "bundle0"
blo "0,1200"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
font "courier,12,0"
)
xt "0,1400,1400,2700"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
font "courier,12,0"
)
xt "0,0,6300,1300"
st "Auto list"
)
second (MLText
va (VaSet
font "courier,12,0"
)
xt "0,1400,12600,2700"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1400,17400,-400"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1750"
)
num (Text
va (VaSet
)
xt "200,300,600,1300"
st "1"
blo "200,1100"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*83 (Text
va (VaSet
font "courier,9,1"
)
xt "11800,20000,22600,21200"
st "Frame Declarations"
blo "11800,21000"
)
*84 (MLText
va (VaSet
)
xt "11800,21200,11800,21200"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1400,10800,-400"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1750"
)
num (Text
va (VaSet
)
xt "200,300,600,1300"
st "1"
blo "200,1100"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*85 (Text
va (VaSet
font "courier,9,1"
)
xt "11800,20000,22600,21200"
st "Frame Declarations"
blo "11800,21000"
)
*86 (MLText
va (VaSet
)
xt "11800,21200,11800,21200"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,750,2600,2150"
st "Port"
blo "0,1950"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,750,2600,2150"
st "Port"
blo "0,1950"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
isHidden 1
font "courier,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "courier,10,1"
)
xt "-7000,25800,1600,27000"
st "Declarations"
blo "-7000,26800"
)
portLabel (Text
uid 3,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "-7000,27000,-2800,28200"
st "Ports:"
blo "-7000,28000"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "courier,10,1"
)
xt "-7000,27000,-1000,28200"
st "Pre User:"
blo "-7000,28000"
)
preUserText (MLText
uid 5,0
va (VaSet
)
xt "-5000,28200,19000,30200"
st "constant addressBitNb : positive := 12;
constant dataBitNb : positive := 16;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "-7000,27000,4000,28200"
st "Diagram Signals:"
blo "-7000,28000"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "-7000,27000,300,28200"
st "Post User:"
blo "-7000,28000"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
)
xt "-5000,41400,-5000,41400"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 72,0
usingSuid 1
emptyRow *87 (LEmptyRow
)
uid 3310,0
optionalChildren [
*88 (RefLabelRowHdr
)
*89 (TitleRowHdr
)
*90 (FilterRowHdr
)
*91 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*92 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*93 (GroupColHdr
tm "GroupColHdrMgr"
)
*94 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*95 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*96 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*97 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*98 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*99 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*100 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "clockA"
t "std_ulogic"
o 3
suid 55,0
)
)
uid 5428,0
)
*101 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "enA"
t "std_ulogic"
o 9
suid 56,0
)
)
uid 5430,0
)
*102 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "writeEnA"
t "std_ulogic"
o 11
suid 57,0
)
)
uid 5432,0
)
*103 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "clockB"
t "std_ulogic"
o 4
suid 61,0
)
)
uid 5488,0
)
*104 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "enB"
t "std_ulogic"
o 10
suid 62,0
)
)
uid 5490,0
)
*105 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "writeEnB"
t "std_ulogic"
o 12
suid 63,0
)
)
uid 5492,0
)
*106 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "dataInB"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 6
suid 67,0
)
)
uid 5662,0
)
*107 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "dataOutB"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 8
suid 68,0
)
)
uid 5664,0
)
*108 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "addressB"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 2
suid 69,0
)
)
uid 5666,0
)
*109 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "dataInA"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 5
suid 70,0
)
)
uid 5668,0
)
*110 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "dataOutA"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
posAdd 0
o 7
suid 71,0
)
)
uid 5670,0
)
*111 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "addressA"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 1
suid 72,0
)
)
uid 5672,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 3323,0
optionalChildren [
*112 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *113 (MRCItem
litem &87
pos 12
dimension 20
)
uid 3325,0
optionalChildren [
*114 (MRCItem
litem &88
pos 0
dimension 20
uid 3326,0
)
*115 (MRCItem
litem &89
pos 1
dimension 23
uid 3327,0
)
*116 (MRCItem
litem &90
pos 2
hidden 1
dimension 20
uid 3328,0
)
*117 (MRCItem
litem &100
pos 0
dimension 20
uid 5429,0
)
*118 (MRCItem
litem &101
pos 1
dimension 20
uid 5431,0
)
*119 (MRCItem
litem &102
pos 2
dimension 20
uid 5433,0
)
*120 (MRCItem
litem &103
pos 3
dimension 20
uid 5489,0
)
*121 (MRCItem
litem &104
pos 4
dimension 20
uid 5491,0
)
*122 (MRCItem
litem &105
pos 5
dimension 20
uid 5493,0
)
*123 (MRCItem
litem &106
pos 6
dimension 20
uid 5663,0
)
*124 (MRCItem
litem &107
pos 7
dimension 20
uid 5665,0
)
*125 (MRCItem
litem &108
pos 8
dimension 20
uid 5667,0
)
*126 (MRCItem
litem &109
pos 9
dimension 20
uid 5669,0
)
*127 (MRCItem
litem &110
pos 10
dimension 20
uid 5671,0
)
*128 (MRCItem
litem &111
pos 11
dimension 20
uid 5673,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
)
uid 3329,0
optionalChildren [
*129 (MRCItem
litem &91
pos 0
dimension 20
uid 3330,0
)
*130 (MRCItem
litem &93
pos 1
dimension 50
uid 3331,0
)
*131 (MRCItem
litem &94
pos 2
dimension 100
uid 3332,0
)
*132 (MRCItem
litem &95
pos 3
dimension 50
uid 3333,0
)
*133 (MRCItem
litem &96
pos 4
dimension 100
uid 3334,0
)
*134 (MRCItem
litem &97
pos 5
dimension 100
uid 3335,0
)
*135 (MRCItem
litem &98
pos 6
dimension 50
uid 3336,0
)
*136 (MRCItem
litem &99
pos 7
dimension 80
uid 3337,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 3324,0
vaOverrides [
]
)
]
)
uid 3309,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *137 (LEmptyRow
)
uid 3339,0
optionalChildren [
*138 (RefLabelRowHdr
)
*139 (TitleRowHdr
)
*140 (FilterRowHdr
)
*141 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*142 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*143 (GroupColHdr
tm "GroupColHdrMgr"
)
*144 (NameColHdr
tm "GenericNameColHdrMgr"
)
*145 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*146 (InitColHdr
tm "GenericValueColHdrMgr"
)
*147 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*148 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 3351,0
optionalChildren [
*149 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *150 (MRCItem
litem &137
pos 0
dimension 20
)
uid 3353,0
optionalChildren [
*151 (MRCItem
litem &138
pos 0
dimension 20
uid 3354,0
)
*152 (MRCItem
litem &139
pos 1
dimension 23
uid 3355,0
)
*153 (MRCItem
litem &140
pos 2
hidden 1
dimension 20
uid 3356,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
)
uid 3357,0
optionalChildren [
*154 (MRCItem
litem &141
pos 0
dimension 20
uid 3358,0
)
*155 (MRCItem
litem &143
pos 1
dimension 50
uid 3359,0
)
*156 (MRCItem
litem &144
pos 2
dimension 100
uid 3360,0
)
*157 (MRCItem
litem &145
pos 3
dimension 100
uid 3361,0
)
*158 (MRCItem
litem &146
pos 4
dimension 50
uid 3362,0
)
*159 (MRCItem
litem &147
pos 5
dimension 50
uid 3363,0
)
*160 (MRCItem
litem &148
pos 6
dimension 80
uid 3364,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 3352,0
vaOverrides [
]
)
]
)
uid 3338,0
type 1
)
activeModelName "BlockDiag"
)