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14 lines
322 B
VHDL
14 lines
322 B
VHDL
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ARCHITECTURE sim OF clockGenerator IS
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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BEGIN
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9.0/10.0;
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END ARCHITECTURE sim;
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