mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-30 04:43:26 +00:00
5 lines
117 B
VHDL
5 lines
117 B
VHDL
|
ARCHITECTURE sim OF and4inv1 IS
|
||
|
|
BEGIN
|
||
|
|
out1 <= (not in1) and in2 and in3 and in4 after delay;
|
||
|
|
END ARCHITECTURE sim;
|