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23 lines
445 B
VHDL
23 lines
445 B
VHDL
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ARCHITECTURE sim OF mux2to1ULogicVector IS
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signal selInt: std_ulogic;
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BEGIN
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selInt <= to_X01(sel);
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muxSelect: process(selInt, in0, in1)
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begin
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if selInt = '0' then
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muxOut <= in0 after delay;
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elsif selInt = '1' then
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muxOut <= in1 after delay;
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elsif in0 = in1 then
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muxOut <= in0 after delay;
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else
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muxOut <= (others => 'X') after delay;
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end if;
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end process muxSelect;
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END ARCHITECTURE sim;
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