mirror of
https://github.com/Klagarge/Cursor.git
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83 lines
3.5 KiB
VHDL
83 lines
3.5 KiB
VHDL
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ARCHITECTURE test OF sdramController_tester IS
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constant clockFrequency: real := 66.0E6;
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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signal ramAddr_int: natural := 0;
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signal ramDataOut_int: natural := 0;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- test sequence
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process
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begin
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ramRd <= '0';
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ramWr <= '0';
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ramEn <= '1';
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-- wait for SDRAM ready
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wait for 154.3 us - now;
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-- write AAAA at address 000010
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ramAddr_int <= 16#000010#;
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ramDataOut_int <= 16#AAAA#;
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ramWr <= '1', '0' after clockPeriod;
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-- wait for SDRAM ready
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wait for 164.5 us - now;
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-- write AAAA at address 000011
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ramAddr_int <= 16#000011#;
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ramDataOut_int <= 16#BBBD#;
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ramWr <= '1', '0' after clockPeriod;
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-- wait for SDRAM ready
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wait for 196.1 us - now;
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-- read back from address 000010
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ramAddr_int <= 16#000010#;
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ramRd <= '1', '0' after clockPeriod;
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-- -- wait for SDRAM ready
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-- wait for 130 us;
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-- -- write AAAA at address 000010
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-- ramAddr_int <= 16#000010#;
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-- ramDataOut_int <= 16#AAAA#;
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-- ramWr <= '1', '0' after clockPeriod;
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-- -- read back from same address
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-- wait for 10*clockPeriod;
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-- ramRd <= '1', '0' after clockPeriod;
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-- -- wait for a refresh
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-- wait for 140.3 us - now;
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-- -- write 5555 at address 600010
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-- ramAddr_int <= 16#600020#;
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-- ramDataOut_int <= 16#5555#;
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-- ramWr <= '1', '0' after clockPeriod;
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-- -- read back from same address
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-- wait for 1*clockPeriod;
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-- ramRd <= '1', '0' after clockPeriod;
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-- -- read back from address 600010
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-- addr_from_up_int <= 16#600010#;
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-- mem_read <= '1', '0' after clockPeriod;
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-- wait for 10*clockPeriod;
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-- -- wait for 3 refresh periods
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-- wait until falling_edge(dram_busy);
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-- wait until falling_edge(dram_busy);
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-- wait until falling_edge(dram_busy);
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-- -- read back from address 000010
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-- addr_from_up_int <= 16#000010#;
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-- mem_read <= '1', '0' after clockPeriod;
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-- wait for 10*clockPeriod;
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-- end of tests
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wait;
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end process;
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------------------------------------------------------------------------------
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-- address and data
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ramAddr <= to_unsigned(ramAddr_int, ramAddr'length);
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ramDataOut <= std_ulogic_vector(to_unsigned(ramDataOut_int, ramDataOut'length));
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END ARCHITECTURE test;
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