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24 lines
448 B
VHDL
24 lines
448 B
VHDL
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ARCHITECTURE sim OF demux1to4 IS
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BEGIN
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process(sel, in1)
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begin
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-- default values
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out0 <= '0';
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out1 <= '0';
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out2 <= '0';
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out3 <= '0';
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-- selection
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case sel is
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when "00" => out0 <= in1 after delay;
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when "01" => out1 <= in1 after delay;
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when "10" => out2 <= in1 after delay;
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when "11" => out3 <= in1 after delay;
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when others => NULL;
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end case;
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end process;
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END ARCHITECTURE sim;
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