1
0
mirror of https://github.com/Klagarge/Cursor.git synced 2024-11-23 18:03:27 +00:00
Cursor/Libs/Gates/hdl/logic1_sim.vhd

5 lines
63 B
VHDL
Raw Normal View History

2021-11-24 09:50:51 +00:00
ARCHITECTURE sim OF logic1 IS
BEGIN
logic_1 <= '1';
END sim;