mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-23 09:53:29 +00:00
5 lines
97 B
VHDL
5 lines
97 B
VHDL
|
ARCHITECTURE sim OF nor2 IS
|
||
|
|
BEGIN
|
||
|
|
out1 <= not( in1 or in2 ) after delay;
|
||
|
|
END ARCHITECTURE sim;
|