mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-23 18:03:27 +00:00
5 lines
101 B
VHDL
5 lines
101 B
VHDL
|
ARCHITECTURE sim OF xor3 IS
|
||
|
|
BEGIN
|
||
|
|
xorOut <= in1 xor in2 xor in3 after delay;
|
||
|
|
END ARCHITECTURE sim;
|