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48 lines
1.7 KiB
VHDL
48 lines
1.7 KiB
VHDL
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ARCHITECTURE test OF lcdController_tester IS
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_ulogic := '1';
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constant testInterval: time := 5 us;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- send sequence
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process
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begin
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ascii <= (others => '0');
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send <= '0';
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wait until falling_edge(busy);
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wait for testInterval;
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-- send single character
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wait until rising_edge(clock_int);
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ascii <= std_ulogic_vector(to_unsigned(character'pos('a'), ascii'length));
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send <= '1', '0' after clockPeriod;
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wait until rising_edge(busy);
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wait until falling_edge(busy);
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wait for testInterval;
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-- send character stream
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for index in character'pos('b') to character'pos('d') loop
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ascii <= std_ulogic_vector(to_unsigned(index, ascii'length));
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send <= '1', '0' after clockPeriod;
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wait until rising_edge(busy);
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wait until falling_edge(busy);
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wait for 1 ns;
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end loop;
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wait for testInterval;
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-- end of simulation
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assert false
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report "End of simulation"
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severity failure;
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wait;
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end process;
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END ARCHITECTURE test;
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