mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-30 04:43:26 +00:00
5 lines
91 B
VHDL
5 lines
91 B
VHDL
|
ARCHITECTURE sim OF and2 IS
|
||
|
|
BEGIN
|
||
|
|
out1 <= in1 and in2 after delay;
|
||
|
|
END ARCHITECTURE sim;
|