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23 lines
456 B
VHDL
23 lines
456 B
VHDL
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ARCHITECTURE RTL OF counterUpDown IS
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signal sCountOut: unsigned(countOut'range);
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BEGIN
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count: process(reset, clock)
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begin
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if reset = '1' then
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sCountOut <= (others => '0');
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elsif rising_edge(clock) then
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if up = '1' then
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sCountOut <= sCountOut + 1;
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elsif down = '1' then
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sCountOut <= sCountOut - 1;
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end if;
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end if;
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end process count;
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countOut <= sCountOut after delay;
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END ARCHITECTURE RTL;
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