diff --git a/Cursor/hds/.hdlsidedata/_compteur_entity.vhg._fpf b/Cursor/hds/.hdlsidedata/_compteur_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor/hds/.hdlsidedata/_compteur_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Cursor/hds/.hdlsidedata/_compteurupdownrsyncall_entity.vhg._fpf b/Cursor/hds/.hdlsidedata/_compteurupdownrsyncall_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor/hds/.hdlsidedata/_compteurupdownrsyncall_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Cursor/hds/.hdlsidedata/_convertissor_position_entity.vhg._fpf b/Cursor/hds/.hdlsidedata/_convertissor_position_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor/hds/.hdlsidedata/_convertissor_position_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Cursor/hds/.hdlsidedata/_cpt1bit_entity.vhg._fpf b/Cursor/hds/.hdlsidedata/_cpt1bit_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor/hds/.hdlsidedata/_cpt1bit_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Cursor/hds/.hdlsidedata/_cpt1bit_struct.vhg._fpf b/Cursor/hds/.hdlsidedata/_cpt1bit_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor/hds/.hdlsidedata/_cpt1bit_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Cursor/hds/.hdlsidedata/_cpt4bit_entity.vhg._fpf b/Cursor/hds/.hdlsidedata/_cpt4bit_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor/hds/.hdlsidedata/_cpt4bit_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Cursor/hds/.hdlsidedata/_cpt4bit_struct.vhg._fpf b/Cursor/hds/.hdlsidedata/_cpt4bit_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor/hds/.hdlsidedata/_cpt4bit_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Cursor/hds/.hdlsidedata/_encoder_encoder.vhg._fpf b/Cursor/hds/.hdlsidedata/_encoder_encoder.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor/hds/.hdlsidedata/_encoder_encoder.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Cursor/hds/.hdlsidedata/_encoder_entity.vhg._fpf b/Cursor/hds/.hdlsidedata/_encoder_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor/hds/.hdlsidedata/_encoder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/errors_simu_1.log b/errors_simu_1.log new file mode 100644 index 0000000..11acee4 --- /dev/null +++ b/errors_simu_1.log @@ -0,0 +1,266 @@ + +Performing generation for single diagram... +Checking which design units need saving +Incrementally generating HDL... + +. +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor_test\hdl\cursor_tb_struct.vhg + +Generation completed successfully. +-------------------------------------------------------- +Comparing HDL files with compiled files ... + + Current working directory is C:/Users/remi/OneDrive/Documents/Cours/05-HEVS/S1fb/electricity/1-EIN/project/cursor/HDLdesigner/Cursor/Scripts + +Executing data preparation plug-in for 10.7c + + +Performing compile... +Library Cursor_test +Model Technology ModelSim SE vmap 10.7c Lib Mapping Utility 2018.08 Aug 18 2018 +vmap -c +Copying C:/eda/MentorGraphics/modelsim/win32/../modelsim.ini to modelsim.ini +Writing temporary output file "C:/Users/remi/AppData/Local/Temp/Files0". +Start time: 21:06:29 on Dec 20,2021 +vcom -work Cursor_test -nologo -2008 -f C:/Users/remi/AppData/Local/Temp/Files0 +-- Loading package STANDARD +-- Compiling entity cursor_tb +-- Loading package TEXTIO +-- Loading package std_logic_1164 +-- Loading package NUMERIC_STD +** Error: C:/Users/remi/OneDrive/Documents/Cours/05-HEVS/S1fb/electricity/1-EIN/project/cursor/HDLdesigner/Cursor/Prefs/../Cursor_test/hdl/cursor_tb_struct.vhg(14): (vcom-1598) Library "cursor" not found. +** Note: C:/Users/remi/OneDrive/Documents/Cours/05-HEVS/S1fb/electricity/1-EIN/project/cursor/HDLdesigner/Cursor/Prefs/../Cursor_test/hdl/cursor_tb_struct.vhg(17): VHDL Compiler exiting +End time: 21:06:29 on Dec 20,2021, Elapsed time: 0:00:00 +Errors: 1, Warnings: 0 + +child process exited abnormally +Failed during ModelSim compile - Error executing "C:/eda/MentorGraphics/modelsim/win32/vcom -work "Cursor_test" -nologo -2008 -f C:/Users/remi/AppData/Local/Temp/Files0" + +Compiled 2 file(s) in 1 compiler invocation(s) with 2 failure(s) + +Data preparation step completed, check transcript... +--------------------------------------------------------------------------------- + +Performing hierarchical generation through components... +Checking which design units need saving +Incrementally generating HDL... + +. + +Cursor/cursorCircuit +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cursorcircuit_entity.vhg + +Cursor/Position +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\position_entity.vhg + +Cursor/Encoder +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\encoder_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\encoder_encoder.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). + +Cursor/Compteur +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\compteur_entity.vhg + +Cursor/compteurUpDownRsyncAll +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\compteurupdownrsyncall_entity.vhg +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\compteurupdownrsyncall_entity.vhg'. +"compteurupdownrsyncall_entity.vhg",line 24: Error, 'integer' requires 0 index values. + +gates/bufferUlogic +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\bufferulogic_entity.vhg + +Cursor/cpt4bit +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_entity.vhg +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_entity.vhg'. +"cpt4bit_entity.vhg",line 23: Error, 'integer' requires 0 index values. + +Cursor/cpt1bit +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt1bit_entity.vhg + +sequential/DFF +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Sequential\hdl\dff_entity.vhg + +gates/xor2 +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\xor2_entity.vhg + +gates/and2 +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\and2_entity.vhg + +gates/inverter +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\inverter_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt1bit_struct.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_struct.vhg +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_entity.vhg'. +"cpt4bit_entity.vhg",line 23: Error, 'integer' requires 0 index values. +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_struct.vhg'. +"cpt4bit_struct.vhg",line 19: Error, attempt to parse architecture body for 'cpt4bit' when a dependency has errors +or before parsing the entity declaration. +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\compteurupdownrsyncall_struct.vhg +Error: The block diagram interface is inconsistent with the interface on the parent block. +Use the Update Interface command. + +gates/or2 +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\or2_entity.vhg + +Cursor/convertissor_position +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\convertissor_position_entity.vhg +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\convertissor_position_entity.vhg'. +"convertissor_position_entity.vhg",line 20: Error, 'integer' requires 0 index values. + +Cursor/Button +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\button_entity.vhg + +Cursor/button_position +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\button_position_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\button_position_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\button_button.vhg +Error: The block diagram interface is inconsistent with the interface on the parent block. +Use the Update Interface command. +Cannot have a slice/element when connected to a Port. + For input ports, please use the entire array with no slice/elements and rip a slice/element from this Signal. + For output ports, please use HDL text to assign the slice/element to an alternative output Signal. +The following port Signals have slices : + button4(3) + +Error: Signal 'button4' connects to Signal 'button', this would produce invalid HDL. +Error: Signal 'dbus0' connects to Signal 'button', this would produce invalid HDL. + +Cursor/Main +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\main_entity.vhg +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\main_entity.vhg'. +"main_entity.vhg",line 25: Error, 'testlinenb' is not declared. + +Cursor/move +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\move_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\move_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\move_fsm.vhg'. +"move_fsm.vhg",line 102: Error, type error at 'power_cruse'. Needed type 'std_ulogic_vector'. +"move_fsm.vhg",line 106: Error, type error at 'power_deceleration'. Needed type 'std_ulogic_vector'. + +Cursor/set_position +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\set_position_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\set_position_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). + +Cursor/process_cruse +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_cruse_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_cruse_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_cruse_fsm.vhg'. +"process_cruse_fsm.vhg",line 113: Error, cannot use a string literal in a scalar expression. +"process_cruse_fsm.vhg",line 117: Error, cannot use a string literal in a scalar expression. +"process_cruse_fsm.vhg",line 120: Error, cannot use a string literal in a scalar expression. +"process_cruse_fsm.vhg",line 124: Error, cannot use a string literal in a scalar expression. + +Cursor/process_deceleration +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_deceleration_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_deceleration_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_deceleration_fsm.vhg'. +"process_deceleration_fsm.vhg",line 103: Error, cannot use a string literal in a scalar expression. +"process_deceleration_fsm.vhg",line 108: Error, cannot use a string literal in a scalar expression. + +Cursor/selector_acceleration +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_acceleration_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_acceleration_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). + +Cursor/selector_cruse +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_cruse_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_cruse_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). + +Cursor/selector_deceleration +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_deceleration_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_deceleration_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). + +Cursor/process_acceleration +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_acceleration_entity.vhg + +Cursor/side_acceleration +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\side_acceleration_entity.vhg +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\side_acceleration_entity.vhg'. +"side_acceleration_entity.vhg",line 15: Error, 'std_ulogic' requires 0 index values. + +Cursor/enable_acceleration +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\enable_acceleration_entity.vhg +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\enable_acceleration_entity.vhg'. +"enable_acceleration_entity.vhg",line 15: Error, 'std_ulogic' requires 0 index values. + +Cursor/accelerator +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\accelerator_entity.vhg +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\accelerator_entity.vhg'. +"accelerator_entity.vhg",line 15: Error, 'std_ulogic' requires 0 index values. + +Cursor/Driver +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\driver_entity.vhg + +Cursor/Counter_Controller +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\counter_controller_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\counter_controller_fsm.vhg +Warning: Ignoring implicit loopback set on State 'reset_counter' with true condition leaving it. +Warning: Ignoring implicit loopback set on State 'add_start' with true condition leaving it. +Warning: Ignoring implicit loopback set on State 'waiting' with true condition leaving it. +Warning: Ignoring implicit loopback set on State 'add_end' with true condition leaving it. +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). + +sequential/counterEnableResetSync +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Sequential\hdl\counterenableresetsync_entity.vhg + +gates/logic1 +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\logic1_entity.vhg + +Cursor/Motor_side +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\motor_side_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\motor_side_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). + +Cursor/PWM +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\pwm_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\pwm_fsm.vhg +Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table. +(Hint: A default value is required for all combinatorial signals (and the internal signals +generated for registered outputs) to avoid implied latches). +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\driver_drivert.vhg +-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\driver_drivert.vhg'. +"driver_drivert.vhg",line 132: Error, type error at 'countOut'. Needed type 'std_ulogic_vector'. +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cursorcircuit_studentversion.vhg +Error: The following component instances are out of date with respect to their symbol interface:- + I3, I2 +Use Update Interface command to resolve differences. +Error: Signal 'reset' connects to Signal 'rst', this would produce invalid HDL. +Error: Signal 'clock' connects to Signal 'clk', this would produce invalid HDL. + +Cursor_test/cursor_tester +Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor_test\hdl\cursor_tester_entity.vhg +Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor_test\hdl\cursor_tb_struct.vhg + +Generation completed with errors. +-------------------------------------------------------- + +