commit c7ba678fbb65b3ef42458e3de30bd78357b54c3b Author: Rémi Heredero <63239207+Klagarge@users.noreply.github.com> Date: Wed Nov 24 10:50:51 2021 +0100 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..67f7228 --- /dev/null +++ b/.gitignore @@ -0,0 +1,30 @@ +# Ignore HDL Designer Folder +Prefs/hds_user/logs/ +Prefs/dc_user/ +Prefs/dp_user/ +Prefs/hds.info/ + +# Ignore HDL Designer Task generated files +Board/concat/concatenated.vhd +Board/concat/eln_cursor.vhd + +# Ignore files automatically generated by HDL Designer +.cache.dat +*.bak +*.lck +*.vhd.info +default_view +*_entity.vhd +*_struct.vhd +*_fsm.vhd +*.vhg +*.DS_STORE +*.xrf/ + +# Ignore verilog and c files +*.v +*.sv +*.svh +*.c +*.cpp +*.psl \ No newline at end of file diff --git a/Board/concat/eln_cursor.ucf b/Board/concat/eln_cursor.ucf new file mode 100644 index 0000000..5a570c1 --- /dev/null +++ b/Board/concat/eln_cursor.ucf @@ -0,0 +1,80 @@ +#------------------------------------------------------------------------------- +# Clock, reset +# +NET "clock" LOC = "A10" ; +NET "reset_n" LOC = "A15" | PULLUP ; +NET "testMode" LOC = "T10"; + +#------------------------------------------------------------------------------- +# Buttons, V1 board +# +#NET "restart_n" LOC = "E8" ; +#NET "go1_n" LOC = "G9" ; +#NET "go2_n" LOC = "F9" ; +#NET "button4_n" LOC = "F7" ; + +#------------------------------------------------------------------------------- +# Buttons, V2 board +# +NET "restart_n" LOC = "G9" ; +NET "go1_n" LOC = "F9" ; +NET "go2_n" LOC = "F7" ; +NET "button4_n" LOC = "F8" ; + +#------------------------------------------------------------------------------- +# Sensors +# +NET "sensor1_n" LOC = "B6" ; +NET "sensor2_n" LOC = "A6" ; +NET "encoderA_n" LOC = "G4" ; +NET "encoderB_n" LOC = "E2" ; +NET "encoderI_n" LOC = "G3" ; + +#------------------------------------------------------------------------------- +# Motor control +# +NET "motorOn" LOC = "B3" ; +NET "side1" LOC = "G6" ; +NET "side2" LOC = "C5" ; + +#------------------------------------------------------------------------------- +# LEDs, V1 board +# +#NET "LED1" LOC = "B16"; +#NET "LED2" LOC = "A16"; +#NET "LEDs_n<1>" LOC = "E7" ; +#NET "LEDs_n<2>" LOC = "B14"; +#NET "LEDs_n<3>" LOC = "B13"; +#NET "LEDs_n<4>" LOC = "B11"; +#NET "LEDs_n<5>" LOC = "A8" ; +#NET "LEDs_n<6>" LOC = "C7" ; +#NET "LEDs_n<7>" LOC = "A14"; +#NET "LEDs_n<8>" LOC = "A11"; + +#------------------------------------------------------------------------------- +# LEDs, V2 board +# +NET "LED1" LOC = "B16"; +NET "LED2" LOC = "A16"; +NET "LEDs<1>" LOC = "E9" ; +NET "LEDs<2>" LOC = "A8"; +NET "LEDs<3>" LOC = "F11"; +NET "LEDs<4>" LOC = "B11"; +NET "LEDs<5>" LOC = "B13"; +NET "LEDs<6>" LOC = "B14"; +NET "LEDs<7>" LOC = "E7" ; +NET "LEDs<8>" LOC = "E8" ; + +#------------------------------------------------------------------------------- +# LCD +# +NET "LCD_CS1_n" LOC = "A11"; +NET "LCD_SCL" LOC = "D7" ; +NET "LCD_SI" LOC = "C7" ; +NET "LCD_A0" LOC = "A14"; +NET "LCD_RST_n" LOC = "A13"; + +#------------------------------------------------------------------------------- +# Globals +# +NET "*" IOSTANDARD = LVCMOS33; diff --git a/Board/hds/.hdlsidedata/_fpga_cursor_entity.vhg._fpf b/Board/hds/.hdlsidedata/_fpga_cursor_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Board/hds/.hdlsidedata/_fpga_cursor_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Board/hds/.hdlsidedata/_fpga_cursor_struct.vhg._fpf b/Board/hds/.hdlsidedata/_fpga_cursor_struct.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Board/hds/.hdlsidedata/_fpga_cursor_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Board/hds/@f@p@g@a_cursor/struct.bd b/Board/hds/@f@p@g@a_cursor/struct.bd new file mode 100644 index 0000000..58d6ef1 --- /dev/null +++ b/Board/hds/@f@p@g@a_cursor/struct.bd @@ -0,0 +1,13173 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "gates" +unitName "gates" +) +(DmPackageRef +library "Common" +unitName "CommonLib" +) +] +instances [ +(Instance +name "I1" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 1661,0 +) +(Instance +name "I2" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 2212,0 +) +(Instance +name "I3" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 2262,0 +) +(Instance +name "I4" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 2306,0 +) +(Instance +name "I5" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 2361,0 +) +(Instance +name "I6" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 2473,0 +) +(Instance +name "I7" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 2576,0 +) +(Instance +name "I8" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 2624,0 +) +(Instance +name "I9" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 2998,0 +) +(Instance +name "I10" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 3024,0 +) +(Instance +name "I11" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 3044,0 +) +(Instance +name "I12" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 3223,0 +) +(Instance +name "I13" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 3243,0 +) +(Instance +name "I14" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 3330,0 +) +(Instance +name "I15" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 3356,0 +) +(Instance +name "I16" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 4087,0 +) +(Instance +name "I17" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 4113,0 +) +(Instance +name "I18" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 4139,0 +) +(Instance +name "I19" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 4159,0 +) +(Instance +name "I20" +duLibraryName "sequential" +duName "DFF" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 4235,0 +) +(Instance +name "I21" +duLibraryName "gates" +duName "inverter" +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +mwi 0 +uid 4261,0 +) +(Instance +name "I0" +duLibraryName "Cursor" +duName "cursorCircuit" +elements [ +(GiElement +name "position0" +type "positive" +value "position0" +) +(GiElement +name "position1" +type "positive" +value "position1" +) +(GiElement +name "position2" +type "positive" +value "position2" +) +(GiElement +name "slopeShiftBitNb" +type "positive" +value "slopeShiftBitNb" +) +(GiElement +name "pwmBitNb" +type "positive" +value "pwmBitNb" +) +(GiElement +name "testLineNb" +type "positive" +value "testLineNb" +) +] +mwi 0 +uid 5636,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +(EmbeddedInstance +name "eb2" +number "2" +) +] +libraryRefs [ +"ieee" +"gates" +"Common" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor" +) +(vvPair +variable "d_logical" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\FPGA_cursor" +) +(vvPair +variable "date" +value "11.11.2019" +) +(vvPair +variable "day" +value "Mon" +) +(vvPair +variable "day_long" +value "Monday" +) +(vvPair +variable "dd" +value "11" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "FPGA_cursor" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "silvan.zahno" +) +(vvPair +variable "graphical_source_date" +value "11.11.2019" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE6996" +) +(vvPair +variable "graphical_source_time" +value "08:13:01" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE6996" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Board" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_Generic_1_file" +value "U:\\ELN_cursor\\Synthesis" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Board/work" +) +(vvPair +variable "library_downstream_SpyGlass" +value "U:\\ELN_cursor\\Synthesis" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "FPGA_cursor" +) +(vvPair +variable "month" +value "Nov" +) +(vvPair +variable "month_long" +value "November" +) +(vvPair +variable "p" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\FPGA_cursor\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\Board\\ise" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "/usr/opt/Modelsim/modeltech/bin" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "08:13:01" +) +(vvPair +variable "unit" +value "FPGA_cursor" +) +(vvPair +variable "user" +value "silvan.zahno" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 198,0 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"2000,9600,16500,10600" +st "button4_n : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "button4_n" +t "std_uLogic" +o 1 +suid 2019,0 +) +) +) +*115 (CptPort +uid 600,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 601,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48000,28625,48750,29375" +) +tg (CPTG +uid 602,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 603,0 +va (VaSet +) +xt "41600,28400,47000,29400" +st "LCD_CS1_n" +ju 2 +blo "47000,29200" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 604,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,22600,17400,23600" +st "LCD_CS1_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "LCD_CS1_n" +t "std_ulogic" +o 14 +suid 2025,0 +) +) +) +*116 (CptPort +uid 605,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 606,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48000,29625,48750,30375" +) +tg (CPTG +uid 607,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 608,0 +va (VaSet +) +xt "42800,29400,47000,30400" +st "LCD_SCL" +ju 2 +blo "47000,30200" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 609,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,24600,16900,25600" +st "LCD_SCL : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "LCD_SCL" +t "std_ulogic" +o 16 +suid 2026,0 +) +) +) +*117 (CptPort +uid 610,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 611,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48000,30625,48750,31375" +) +tg (CPTG +uid 612,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 613,0 +va (VaSet +) +xt "43400,30400,47000,31400" +st "LCD_SI" +ju 2 +blo "47000,31200" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 614,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,25600,16500,26600" +st "LCD_SI : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "LCD_SI" +t "std_ulogic" +o 17 +suid 2027,0 +) +) +) +*118 (CptPort +uid 615,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 616,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48000,31625,48750,32375" +) +tg (CPTG +uid 617,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 618,0 +va (VaSet +) +xt "43400,31400,47000,32400" +st "LCD_A0" +ju 2 +blo "47000,32200" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 619,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,21600,16700,22600" +st "LCD_A0 : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "LCD_A0" +t "std_ulogic" +o 13 +suid 2028,0 +) +) +) +*119 (CptPort +uid 620,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 621,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48000,32625,48750,33375" +) +tg (CPTG +uid 622,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 623,0 +va (VaSet +) +xt "41600,32400,47000,33400" +st "LCD_RST_n" +ju 2 +blo "47000,33200" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 624,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,23600,17400,24600" +st "LCD_RST_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "LCD_RST_n" +t "std_ulogic" +o 15 +suid 2029,0 +) +) +) +*120 (CptPort +uid 1140,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1141,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48000,33625,48750,34375" +) +tg (CPTG +uid 1142,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1143,0 +va (VaSet +) +xt "44600,33400,47000,34400" +st "LEDs" +ju 2 +blo "47000,34200" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1144,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,28600,23300,29600" +st "LEDs : OUT std_uLogic_vector (1 TO 8) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "LEDs" +t "std_uLogic_vector" +b "(1 TO 8)" +o 20 +suid 2031,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "32000,6000,48000,35000" +) +oxt "15000,6000,20000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Verdana,9,1" +) +xt "31950,31900,35450,33100" +st "Board" +blo "31950,32900" +) +second (Text +uid 12,0 +va (VaSet +font "Verdana,9,1" +) +xt "31950,33100,39550,34300" +st "FPGA_cursor" +blo "31950,34100" +) +) +gi *121 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "35000,26600,44700,27600" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVis (PortSigDisplay +disp 1 +sTC 0 +sT 1 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*122 (Grouping +uid 16,0 +optionalChildren [ +*123 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "54000,41000,73000,43000" +) +oxt "45000,22000,64000,24000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "54200,41400,69600,42600" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 18600 +) +position 1 +ignorePrefs 1 +) +*124 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "22000,41000,48000,43000" +) +oxt "13000,22000,39000,24000" +text (MLText +uid 23,0 +va (VaSet +fg "32768,0,0" +font "Verdana,12,1" +) +xt "28150,41300,41850,42700" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 25600 +) +position 1 +ignorePrefs 1 +) +*125 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "27000,47000,48000,49000" +) +oxt "18000,28000,39000,30000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "27200,47400,43400,48600" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 20600 +) +position 1 +ignorePrefs 1 +) +*126 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "48000,41000,54000,43000" +) +oxt "39000,22000,45000,24000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "48200,41400,52900,42600" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 5600 +) +position 1 +ignorePrefs 1 +) +*127 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "27000,43000,48000,45000" +) +oxt "18000,24000,39000,26000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "27200,43400,42400,44600" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 20600 +) +position 1 +ignorePrefs 1 +) +*128 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "22000,43000,27000,45000" +) +oxt "13000,24000,18000,26000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "22200,43400,25600,44600" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 4600 +) +position 1 +ignorePrefs 1 +) +*129 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "22000,45000,27000,47000" +) +oxt "13000,26000,18000,28000" +text (MLText +uid 38,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "22200,45400,25600,46600" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 4600 +) +position 1 +ignorePrefs 1 +) +*130 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "48000,43000,73000,49000" +) +oxt "39000,24000,64000,30000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "48200,43200,62300,44400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 5600 +visibleWidth 24600 +) +ignorePrefs 1 +) +*131 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "27000,45000,48000,47000" +) +oxt "18000,26000,39000,28000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "27200,45400,43300,46600" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 20600 +) +position 1 +ignorePrefs 1 +) +*132 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "22000,47000,27000,49000" +) +oxt "13000,28000,18000,30000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "22200,47400,26500,48600" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 4600 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 1 +) +xt "22000,41000,73000,49000" +) +oxt "13000,22000,64000,30000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "32768,32768,32768" +) +packageList *133 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*134 (Text +uid 52,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,0,6500,900" +st "Package List" +blo "0,700" +) +*135 (MLText +uid 53,0 +va (VaSet +) +xt "0,1000,17500,4600" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all;" +tm "PackageList" +) +] +) +windowSize "101,55,929,731" +viewArea "-3247,-1126,76624,50300" +cachedDiagramExtent "0,0,73000,49000" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +xMargin 49 +yMargin 49 +paperWidth 761 +paperHeight 1077 +windowsPaperWidth 761 +windowsPaperHeight 1077 +paperType "A4" +windowsPaperName "A4" +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "Verdana,8,0" +) +xt "450,2150,1450,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Verdana,9,1" +) +xt "1000,1000,4400,2200" +st "Panel0" +blo "1000,2000" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,20000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "15950,14900,20750,16100" +st "" +blo "15950,15900" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "15950,16100,19250,17300" +st "" +blo "15950,17100" +) +) +gi *136 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVis (PortSigDisplay +sT 1 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *137 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,7800,6500,8700" +st "Declarations" +blo "0,8500" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,8700,3000,9600" +st "Ports:" +blo "0,9400" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,32600,3000,33600" +st "User:" +blo "0,33400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "0,7800,7500,8700" +st "Internal User:" +blo "0,8500" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,33600,2000,33600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,7800,0,7800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 1305,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +) diff --git a/Board/hds/_fpga_cursor._epf b/Board/hds/_fpga_cursor._epf new file mode 100644 index 0000000..59f500d --- /dev/null +++ b/Board/hds/_fpga_cursor._epf @@ -0,0 +1,3 @@ +TOP_MARKER atom 1 +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom @f@p@g@a_cursor/struct.bd diff --git a/Board/ise/eln_cursor.xise b/Board/ise/eln_cursor.xise new file mode 100644 index 0000000..7117083 --- /dev/null +++ b/Board/ise/eln_cursor.xise @@ -0,0 +1,460 @@ + + + +
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b/Cursor/hds/cursor@circuit/student@version.bd new file mode 100644 index 0000000..6102de8 --- /dev/null +++ b/Cursor/hds/cursor@circuit/student@version.bd @@ -0,0 +1,4837 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "31.1" +appVersion "2018.1 (Build 12)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\cursor@circuit\\student@version.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\cursor@circuit\\student@version.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "studentVersion" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\cursor@circuit" +) +(vvPair +variable "d_logical" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\cursorCircuit" +) +(vvPair +variable "date" +value "13.06.2019" +) +(vvPair +variable "day" +value "Thu" +) +(vvPair +variable "day_long" +value "Thursday" +) +(vvPair +variable "dd" +value "13" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "cursorCircuit" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "student@version.bd" +) +(vvPair +variable "f_logical" +value "studentVersion.bd" +) +(vvPair +variable "f_noext" +value "student@version" +) +(vvPair +variable "graphical_source_author" +value "silvan.zahno" +) +(vvPair +variable "graphical_source_date" +value "13.06.2019" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE6996" +) +(vvPair +variable "graphical_source_time" +value "13:07:15" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE6996" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Cursor" +) +(vvPair +variable "library_downstream_Generic_1_file" +value "D:\\Users\\Syslo\\Chronometer\\Synthesis" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../Cursor/designcheck" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Cursor/work" +) +(vvPair +variable "library_downstream_SpyGlass" +value "D:\\Users\\Syslo\\Chronometer\\Synthesis" +) +(vvPair +variable "mm" +value "06" +) +(vvPair +variable "module_name" +value "cursorCircuit" +) +(vvPair +variable "month" +value "Jun" +) +(vvPair +variable "month_long" +value "June" +) +(vvPair +variable "p" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\cursor@circuit\\student@version.bd" +) +(vvPair +variable "p_logical" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\cursorCircuit\\studentVersion.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME/bin/lin64" +) +(vvPair +variable "task_ISEPath" +value "$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME/modeltech/bin" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "student@version" +) +(vvPair +variable "this_file_logical" +value "studentVersion" +) +(vvPair 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+isHidden 1 +font "Verdana,12,0" +) +xt "143000,65300,147200,66700" +st "side2" +blo "143000,66500" +tm "WireNameMgr" +) +s (Text +uid 4276,0 +va (VaSet +font "Verdana,12,0" +) +xt "143000,66700,143000,66700" +blo "143000,66700" +tm "SignalTypeMgr" +) +) +) +*29 (Net +uid 4283,0 +decl (Decl +n "side2" +t "std_uLogic" +o 20 +suid 13,0 +) +declText (MLText +uid 4284,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,800,9700,1800" +st "side2 : std_uLogic +" +) +) +*30 (PortIoIn +uid 4528,0 +shape (CompositeShape +uid 4529,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4530,0 +sl 0 +ro 270 +xt "42000,9625,43500,10375" +) +(Line +uid 4531,0 +sl 0 +ro 270 +xt "43500,10000,44000,10000" +pts [ +"43500,10000" +"44000,10000" +] +) +] +) +tg (WTG +uid 4532,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4533,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "34300,9300,41000,10700" +st "encoderA" +ju 2 +blo "41000,10500" +tm "WireNameMgr" +) +s (Text +uid 4534,0 +va (VaSet +font "Verdana,12,0" +) +xt "34300,10700,34300,10700" +ju 2 +blo "34300,10700" +tm "SignalTypeMgr" +) +) +) +*31 (Net +uid 4541,0 +decl (Decl +n "encoderA" +t "std_uLogic" +o 3 +suid 14,0 +) +declText (MLText +uid 4542,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,800,10400,1800" +st "encoderA : std_uLogic +" +) +) +*32 (PortIoIn +uid 4543,0 +shape (CompositeShape +uid 4544,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4545,0 +sl 0 +ro 270 +xt "42000,11625,43500,12375" +) +(Line +uid 4546,0 +sl 0 +ro 270 +xt "43500,12000,44000,12000" +pts [ +"43500,12000" +"44000,12000" +] +) +] +) +tg (WTG +uid 4547,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4548,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "34300,11300,41000,12700" +st "encoderB" +ju 2 +blo "41000,12500" +tm "WireNameMgr" +) +s (Text +uid 4549,0 +va (VaSet +font "Verdana,12,0" +) +xt "34300,12700,34300,12700" +ju 2 +blo "34300,12700" +tm "SignalTypeMgr" +) +) +) +*33 (Net +uid 4556,0 +decl (Decl +n "encoderB" +t "std_uLogic" +o 4 +suid 15,0 +) +declText (MLText +uid 4557,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,800,10400,1800" +st "encoderB : std_uLogic +" +) +) +*34 (PortIoIn +uid 4558,0 +shape (CompositeShape +uid 4559,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4560,0 +sl 0 +ro 270 +xt "42000,13625,43500,14375" +) +(Line +uid 4561,0 +sl 0 +ro 270 +xt "43500,14000,44000,14000" +pts [ +"43500,14000" +"44000,14000" +] +) +] +) +tg (WTG +uid 4562,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4563,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "34600,13300,41000,14700" +st "encoderI" +ju 2 +blo "41000,14500" +tm "WireNameMgr" +) +s (Text +uid 4564,0 +va (VaSet +font "Verdana,12,0" +) +xt "34600,14700,34600,14700" +ju 2 +blo "34600,14700" +tm "SignalTypeMgr" +) +) +) +*35 (Net +uid 4571,0 +decl (Decl +n "encoderI" +t "std_uLogic" +o 5 +suid 16,0 +) +declText (MLText +uid 4572,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,800,10200,1800" +st "encoderI : std_uLogic +" +) +) +*36 (PortIoIn +uid 4573,0 +shape (CompositeShape +uid 4574,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4575,0 +sl 0 +ro 270 +xt "42000,41625,43500,42375" +) +(Line +uid 4576,0 +sl 0 +ro 270 +xt "43500,42000,44000,42000" +pts [ +"43500,42000" +"44000,42000" +] +) +] +) +tg (WTG +uid 4577,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4578,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "37800,41300,41000,42700" +st "go1" +ju 2 +blo "41000,42500" +tm "WireNameMgr" +) +s (Text +uid 4579,0 +va (VaSet +font "Verdana,12,0" +) +xt "37800,42700,37800,42700" +ju 2 +blo "37800,42700" +tm "SignalTypeMgr" +) +) +) +*37 (Net +uid 4586,0 +decl (Decl +n "go1" +t "std_uLogic" +o 6 +suid 17,0 +) +declText (MLText +uid 4587,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,800,9700,1800" +st "go1 : std_uLogic +" +) +) +*38 (PortIoIn +uid 4588,0 +shape (CompositeShape +uid 4589,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4590,0 +sl 0 +ro 270 +xt "42000,43625,43500,44375" +) +(Line +uid 4591,0 +sl 0 +ro 270 +xt "43500,44000,44000,44000" +pts [ +"43500,44000" +"44000,44000" +] +) +] +) +tg (WTG +uid 4592,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4593,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "37800,43300,41000,44700" +st "go2" +ju 2 +blo "41000,44500" +tm "WireNameMgr" +) +s (Text +uid 4594,0 +va (VaSet +font "Verdana,12,0" +) +xt "37800,44700,37800,44700" +ju 2 +blo "37800,44700" +tm "SignalTypeMgr" +) +) +) +*39 (Net +uid 4601,0 +decl (Decl +n "go2" +t "std_uLogic" +o 7 +suid 18,0 +) +declText (MLText +uid 4602,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,800,9700,1800" +st "go2 : std_uLogic +" +) +) +*40 (PortIoIn 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+(Pentagon +uid 8034,0 +sl 0 +ro 270 +xt "42000,17625,43500,18375" +) +(Line +uid 8035,0 +sl 0 +ro 270 +xt "43500,18000,44000,18000" +pts [ +"43500,18000" +"44000,18000" +] +) +] +) +tg (WTG +uid 8036,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8037,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "37200,17300,41000,18700" +st "clock" +ju 2 +blo "41000,18500" +tm "WireNameMgr" +) +s (Text +uid 8038,0 +va (VaSet +font "Verdana,12,0" +) +xt "37200,18700,37200,18700" +ju 2 +blo "37200,18700" +tm "SignalTypeMgr" +) +) +) +*43 (PortIoIn +uid 8039,0 +shape (CompositeShape +uid 8040,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 8041,0 +sl 0 +ro 270 +xt "42000,19625,43500,20375" +) +(Line +uid 8042,0 +sl 0 +ro 270 +xt "43500,20000,44000,20000" +pts [ +"43500,20000" +"44000,20000" +] +) +] +) +tg (WTG +uid 8043,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8044,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "36900,19300,41000,20700" +st "reset" +ju 2 +blo "41000,20500" +tm "WireNameMgr" +) +s (Text +uid 8045,0 +va (VaSet +font "Verdana,12,0" +) +xt "36900,20700,36900,20700" +ju 2 +blo "36900,20700" +tm "SignalTypeMgr" +) +) +) +*44 (Net +uid 9949,0 +decl (Decl +n "CS1_n" +t "std_ulogic" +o 14 +suid 68,0 +) +declText (MLText +uid 9950,0 +va (VaSet +isHidden 1 +) +xt "0,400,12600,1600" +st "CS1_n : std_ulogic +" +) +) +*45 (Net +uid 9957,0 +decl (Decl +n "SCL" +t "std_ulogic" +o 16 +suid 69,0 +) +declText (MLText +uid 9958,0 +va (VaSet +isHidden 1 +) +xt "0,400,11900,1600" +st "SCL : std_ulogic +" +) +) +*46 (Net +uid 9965,0 +decl (Decl +n "SI" +t "std_ulogic" +o 17 +suid 70,0 +) +declText (MLText +uid 9966,0 +va (VaSet +isHidden 1 +) +xt "0,400,11300,1600" +st "SI : std_ulogic +" +) +) +*47 (Net +uid 9973,0 +decl (Decl +n "A0" +t "std_ulogic" +o 13 +suid 71,0 +) +declText (MLText +uid 9974,0 +va (VaSet +isHidden 1 +) +xt "0,400,11600,1600" +st "A0 : std_ulogic +" +) +) +*48 (Net +uid 9981,0 +decl (Decl +n "RST_n" +t "std_ulogic" +o 15 +suid 72,0 +) +declText (MLText +uid 9982,0 +va (VaSet +isHidden 1 +) +xt "0,400,12500,1600" +st "RST_n : std_ulogic +" +) +) +*49 (PortIoOut +uid 9989,0 +shape (CompositeShape +uid 9990,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 9991,0 +sl 0 +ro 270 +xt "140500,98625,142000,99375" +) +(Line +uid 9992,0 +sl 0 +ro 270 +xt "140000,99000,140500,99000" +pts [ +"140000,99000" +"140500,99000" +] +) +] +) +tg (WTG +uid 9993,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9994,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "143000,98300,147900,99700" +st "CS1_n" +blo "143000,99500" +tm "WireNameMgr" +) +s (Text +uid 9995,0 +va (VaSet +font "Verdana,12,0" +) +xt "143000,99700,143000,99700" +blo "143000,99700" +tm "SignalTypeMgr" +) +) +) +*50 (PortIoOut +uid 9996,0 +shape (CompositeShape +uid 9997,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 9998,0 +sl 0 +ro 270 +xt "140500,100625,142000,101375" +) +(Line +uid 9999,0 +sl 0 +ro 270 +xt "140000,101000,140500,101000" +pts [ +"140000,101000" +"140500,101000" +] +) +] +) +tg (WTG +uid 10000,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10001,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "143000,100300,146200,101700" +st "SCL" +blo "143000,101500" +tm "WireNameMgr" +) +s (Text +uid 10002,0 +va (VaSet +font "Verdana,12,0" +) +xt "143000,101700,143000,101700" +blo "143000,101700" +tm "SignalTypeMgr" +) +) +) +*51 (PortIoOut +uid 10003,0 +shape (CompositeShape +uid 10004,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 10005,0 +sl 0 +ro 270 +xt "140500,102625,142000,103375" +) +(Line +uid 10006,0 +sl 0 +ro 270 +xt "140000,103000,140500,103000" +pts [ +"140000,103000" +"140500,103000" +] +) +] +) +tg (WTG +uid 10007,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10008,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "143000,102300,145100,103700" +st "SI" +blo "143000,103500" +tm "WireNameMgr" +) +s (Text +uid 10009,0 +va (VaSet +font "Verdana,12,0" +) +xt "143000,103700,143000,103700" +blo "143000,103700" +tm "SignalTypeMgr" +) +) +) +*52 (PortIoOut +uid 10010,0 +shape (CompositeShape +uid 10011,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 10012,0 +sl 0 +ro 270 +xt "140500,104625,142000,105375" +) +(Line +uid 10013,0 +sl 0 +ro 270 +xt "140000,105000,140500,105000" +pts [ +"140000,105000" +"140500,105000" +] +) +] +) +tg (WTG +uid 10014,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10015,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "143000,104300,145400,105700" +st "A0" +blo "143000,105500" +tm "WireNameMgr" +) +s (Text +uid 10016,0 +va (VaSet +font "Verdana,12,0" +) +xt "143000,105700,143000,105700" +blo "143000,105700" +tm "SignalTypeMgr" +) +) +) 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(Text +uid 2289,0 +va (VaSet +font "Verdana,12,0" +) +xt "44000,38600,48900,39900" +st "restart" +blo "44000,39600" +tm "WireNameMgr" +) +) +on &15 +) +*55 (Wire +uid 2315,0 +shape (OrthoPolyLine +uid 2316,0 +va (VaSet +vasetType 3 +) +xt "44000,66000,51250,66000" +pts [ +"44000,66000" +"51250,66000" +] +) +start &16 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2319,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2320,0 +va (VaSet +font "Verdana,12,0" +) +xt "44000,64600,49600,65900" +st "testMode" +blo "44000,65600" +tm "WireNameMgr" +) +) +on &17 +) +*56 (Wire +uid 2949,0 +shape (OrthoPolyLine +uid 2950,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "152000,-9000,160000,-9000" +pts [ +"152000,-9000" +"160000,-9000" +] +) +end &18 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2953,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2954,0 +va (VaSet +font "Verdana,12,0" +) +xt "154000,-10400,158900,-9100" +st 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(VaSet +font "Verdana,12,0" +) +xt "41000,10700,41000,10700" +blo "41000,10700" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 178,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16700,19000,17500" +st "go2 : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "go2" +t "std_uLogic" +o 7 +suid 5,0 +) +) +) +*111 (CptPort +uid 194,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 199,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "56000,13625,56750,14375" +) +tg (CPTG +uid 196,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 197,0 +va (VaSet +font "Verdana,12,0" +) +xt "49100,13400,55000,14800" +st "sensor1" +ju 2 +blo "55000,14600" +tm "CptPortNameMgr" +) +s (Text +uid 722,0 +va (VaSet +font "Verdana,12,0" +) +xt "55000,14800,55000,14800" +ju 2 +blo "55000,14800" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 198,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19100,19000,19900" +st "sensor1 : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl 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"RightVerticalLayoutStrategy" +f (Text +uid 208,0 +va (VaSet +font "Verdana,12,0" +) +xt "45000,3000,50600,4400" +st "testOut" +ju 2 +blo "50600,4200" +tm "CptPortNameMgr" +) +s (Text +uid 724,0 +va (VaSet +font "Verdana,12,0" +) +xt "50600,4400,50600,4400" +ju 2 +blo "48500,900" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 209,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27900,30500,28700" +st "testOut : OUT std_uLogic_vector (1 TO testLineNb)" +) +thePort (LogicalPort +m 1 +decl (Decl +n "testOut" +t "std_uLogic_vector" +b "(1 TO testLineNb)" +o 21 +suid 8,0 +) +) +) +*114 (CptPort +uid 210,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 211,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,7625,40000,8375" +) +tg (CPTG +uid 212,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 213,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,7300,44200,8700" +st "go1" +blo "41000,8500" +tm "CptPortNameMgr" +) +s (Text +uid 725,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,8700,41000,8700" +blo "41000,8700" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 214,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15900,19000,16700" +st "go1 : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "go1" +t "std_uLogic" +o 6 +suid 9,0 +) +) +) +*115 (CptPort +uid 215,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 216,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "56000,9625,56750,10375" +) +tg (CPTG +uid 217,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 218,0 +va (VaSet +font "Verdana,12,0" +) +xt "50800,9400,55000,10800" +st "side2" +ju 2 +blo "55000,10600" +tm "CptPortNameMgr" +) +s (Text +uid 726,0 +va (VaSet +font "Verdana,12,0" +) +xt "55000,10800,55000,10800" +ju 2 +blo "55000,10800" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 219,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,27100,19000,27900" +st "side2 : OUT std_uLogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "side2" +t "std_uLogic" +o 20 +suid 10,0 +) +) +) +*116 (CptPort +uid 220,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 221,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "56000,15625,56750,16375" +) +tg (CPTG +uid 222,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 223,0 +va (VaSet +font "Verdana,12,0" +) +xt "49100,15300,55000,16700" +st "sensor2" +ju 2 +blo "55000,16500" +tm "CptPortNameMgr" +) +s (Text +uid 727,0 +va (VaSet +font "Verdana,12,0" +) +xt "55000,16700,55000,16700" +ju 2 +blo "55000,16700" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 224,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19900,19000,20700" +st "sensor2 : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "sensor2" +t "std_uLogic" +o 11 +suid 11,0 +) +) +) +*117 (CptPort +uid 225,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 226,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "56000,5625,56750,6375" +) +tg (CPTG +uid 227,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 228,0 +va (VaSet +font "Verdana,12,0" +) +xt "48700,5400,55000,6800" +st "motorOn" +ju 2 +blo "55000,6600" +tm "CptPortNameMgr" +) +s (Text +uid 728,0 +va (VaSet +font "Verdana,12,0" +) +xt "55000,6800,55000,6800" +ju 2 +blo "55000,6800" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 229,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25500,19000,26300" +st "motorOn : OUT std_uLogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "motorOn" +t "std_uLogic" +o 18 +suid 12,0 +) +) +) +*118 (CptPort +uid 230,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 250,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "56000,19625,56750,20375" +) +tg (CPTG +uid 232,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 233,0 +va (VaSet +font "Verdana,12,0" +) +xt "48300,19400,55000,20800" +st "encoderA" +ju 2 +blo "55000,20600" +tm "CptPortNameMgr" +) +s (Text +uid 729,0 +va (VaSet +font "Verdana,12,0" +) +xt "55000,20800,55000,20800" +ju 2 +blo "55000,20800" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 234,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,13500,19000,14300" +st "encoderA : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "encoderA" +t "std_uLogic" +o 3 +suid 13,0 +) +) +) +*119 (CptPort +uid 235,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 251,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "56000,21625,56750,22375" +) +tg (CPTG +uid 237,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 238,0 +va (VaSet +font "Verdana,12,0" +) +xt "48300,21400,55000,22800" +st "encoderB" +ju 2 +blo "55000,22600" +tm "CptPortNameMgr" +) +s (Text +uid 730,0 +va (VaSet +font "Verdana,12,0" +) +xt "55000,22800,55000,22800" +ju 2 +blo "55000,22800" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 239,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,14300,19000,15100" +st "encoderB : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "encoderB" +t "std_uLogic" +o 4 +suid 14,0 +) +) +) +*120 (CptPort +uid 240,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 252,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "56000,23625,56750,24375" +) +tg (CPTG +uid 242,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 243,0 +va (VaSet +font "Verdana,12,0" +) +xt "48600,23400,55000,24800" +st "encoderI" +ju 2 +blo "55000,24600" +tm "CptPortNameMgr" +) +s (Text +uid 731,0 +va (VaSet +font "Verdana,12,0" +) +xt "55000,24800,55000,24800" +ju 2 +blo "55000,24800" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 244,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15100,19000,15900" +st "encoderI : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "encoderI" +t "std_uLogic" +o 5 +suid 15,0 +) +) +) +*121 (CptPort +uid 245,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 246,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,11625,40000,12375" +) +tg (CPTG +uid 247,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 248,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,11300,46800,12700" +st "button4" +blo "41000,12500" +tm "CptPortNameMgr" +) +s (Text +uid 732,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,12700,41000,12700" +blo "41000,12700" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 249,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,11900,19000,12700" +st "button4 : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "button4" +t "std_uLogic" +o 1 +suid 16,0 +) +) +) +*122 (CptPort +uid 768,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 769,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,15625,40000,16375" +) +tg (CPTG +uid 770,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 771,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,15300,45900,16700" +st "CS1_n" +blo "41000,16500" +tm "CptPortNameMgr" +) +s (Text +uid 772,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,16700,41000,16700" +blo "41000,16700" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 773,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22300,19000,23100" +st "CS1_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CS1_n" +t "std_ulogic" +o 14 +suid 2017,0 +) +) +) +*123 (CptPort +uid 774,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 775,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,17625,40000,18375" +) +tg (CPTG +uid 776,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 777,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,17300,44200,18700" +st "SCL" +blo "41000,18500" +tm "CptPortNameMgr" +) +s (Text +uid 778,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,18700,41000,18700" +blo "41000,18700" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 779,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23900,19000,24700" +st "SCL : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "SCL" +t "std_ulogic" +o 16 +suid 2018,0 +) +) +) +*124 (CptPort +uid 780,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 781,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,19625,40000,20375" +) +tg (CPTG +uid 782,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 783,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,19300,43100,20700" +st "SI" +blo "41000,20500" +tm "CptPortNameMgr" +) +s (Text +uid 784,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,20700,41000,20700" +blo "41000,20700" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 785,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24700,19000,25500" +st "SI : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "SI" +t "std_ulogic" +o 17 +suid 2019,0 +) +) +) +*125 (CptPort +uid 786,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 787,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,21625,40000,22375" +) +tg (CPTG +uid 788,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 789,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,21300,43400,22700" +st "A0" +blo "41000,22500" +tm "CptPortNameMgr" +) +s (Text +uid 790,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,22700,41000,22700" +blo "41000,22700" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 791,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21500,19000,22300" +st "A0 : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "A0" +t "std_ulogic" +o 13 +suid 2020,0 +) +) +) +*126 (CptPort +uid 792,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 793,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "39250,23625,40000,24375" +) +tg (CPTG +uid 794,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 795,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,23300,45700,24700" +st "RST_n" +blo "41000,24500" +tm "CptPortNameMgr" +) +s (Text +uid 796,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,24700,41000,24700" +blo "41000,24700" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 797,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23100,19000,23900" +st "RST_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RST_n" +t "std_ulogic" +o 15 +suid 2021,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "40000,2000,56000,34000" +) +oxt "15000,6000,47000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Verdana,8,1" +) +xt "40100,33700,43800,34700" +st "Cursor" +blo "40100,34500" +) +second (Text +uid 12,0 +va (VaSet +font "Verdana,8,1" +) +xt "40100,34700,47400,35700" +st "cursorCircuit" +blo "40100,35500" +) +) +gi *127 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "40000,37200,57500,43600" +st "Generic Declarations + +position0 positive 128 +position1 positive 32000 +position2 positive 64000 +slopeShiftBitNb positive 6 +pwmBitNb positive 8 +testLineNb positive 16 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "position0" +type "positive" +value "128" +) +(GiElement +name "position1" +type "positive" +value "32000" +) +(GiElement +name "position2" +type "positive" +value "64000" +) +(GiElement +name "slopeShiftBitNb" +type "positive" +value "6" +) +(GiElement +name "pwmBitNb" +type "positive" +value "8" +) +(GiElement +name "testLineNb" +type "positive" +value "16" +) +] +) +portInstanceVis (PortSigDisplay +sTC 0 +sT 1 +) +portVis (PortSigDisplay +disp 1 +sTC 0 +) +) +*128 (Grouping +uid 136,0 +optionalChildren [ +*129 (CommentText +uid 138,0 +shape (Rectangle +uid 139,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 140,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48500,36200,48500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*130 (CommentText +uid 141,0 +shape (Rectangle +uid 142,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 143,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44500,53200,44500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*131 (CommentText +uid 144,0 +shape (Rectangle +uid 145,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 146,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46500,36200,46500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*132 (CommentText +uid 147,0 +shape (Rectangle +uid 148,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 149,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46500,32200,46500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*133 (CommentText +uid 150,0 +shape (Rectangle +uid 151,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 152,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,67300,46400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*134 (CommentText +uid 153,0 +shape (Rectangle +uid 154,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 155,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44500,57200,44500" +st " + +" +tm "CommentText" +wrapOption 3 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"32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 164,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48500,32200,48500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*138 (CommentText +uid 165,0 +shape (Rectangle +uid 166,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 167,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47500,36200,47500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 137,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 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"C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "fsm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\lcd@display" +) +(vvPair +variable "d_logical" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\lcdDisplay" +) +(vvPair +variable "date" +value "11.11.2019" +) +(vvPair +variable "day" +value "Mon" +) +(vvPair +variable "day_long" +value "Monday" +) +(vvPair +variable "dd" +value "11" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "lcdDisplay" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "fsm.sm" +) +(vvPair +variable "f_logical" +value "fsm.sm" +) +(vvPair +variable "f_noext" +value "fsm" +) +(vvPair +variable "graphical_source_author" +value "silvan.zahno" +) +(vvPair +variable "graphical_source_date" +value "11.11.2019" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE6996" +) +(vvPair +variable "graphical_source_time" +value "08:13:13" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE6996" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Cursor" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Cursor/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "lcdDisplay" +) +(vvPair +variable "month" +value "Nov" +) +(vvPair +variable "month_long" +value "November" +) +(vvPair +variable "p" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\lcd@display\\fsm.sm" +) +(vvPair +variable "p_logical" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor\\hds\\lcdDisplay\\fsm.sm" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\Board\\ise" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "this_ext" +value "sm" +) +(vvPair +variable "this_file" +value "fsm" +) +(vvPair +variable "this_file_logical" +value "fsm" +) +(vvPair +variable "time" +value "08:13:13" +) +(vvPair +variable "unit" +value "lcdDisplay" +) +(vvPair +variable "user" +value "silvan.zahno" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "fsm" +) +(vvPair +variable "year" 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+sl 0 +xt "77100,8100,78900,9900" +radius 900 +) +(Line +uid 92,0 +sl 0 +va (VaSet +vasetType 3 +lineColor "65535,65535,0" +lineWidth 1 +) +xt "77574,8574,78426,9426" +pts [ +"77574,9426" +"78426,8574" +] +) +(Line +uid 93,0 +sl 0 +va (VaSet +vasetType 3 +lineColor "65535,65535,0" +lineWidth 1 +) +xt "77574,8574,78426,9426" +pts [ +"78426,9426" +"77574,8574" +] +) +] +) +) +*7 (Link +uid 94,0 +shape (CompositeShape +uid 95,0 +va (VaSet +vasetType 1 +fg "65535,65535,0" +bg "0,0,0" +) +optionalChildren [ +(Pentagon +uid 96,0 +sl 0 +ro 270 +xt "87500,8500,89750,9500" +) +(Line +uid 97,0 +sl 0 +ro 270 +xt "87000,9000,87500,9000" +pts [ +"87000,9000" +"87500,9000" +] +) +] +) +name (TextAssociate +uid 98,0 +ps "CenterOffsetStrategy" +text (Text +uid 99,0 +va (VaSet +font "Verdana,8,1" +) +xt "90250,8500,92450,9500" +st "init" +blo "90250,9300" +tm "LinkName" +) +) +) +*8 (Grouping +uid 173,0 +optionalChildren [ +*9 (CommentText +uid 175,0 +shape (Rectangle +uid 176,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "78000,56000,97000,58000" +) +oxt "45000,22000,64000,24000" +text (MLText +uid 177,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "78200,56400,93600,57600" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 18600 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +uid 178,0 +shape (Rectangle +uid 179,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "46000,56000,72000,58000" +) +oxt "13000,22000,39000,24000" +text (MLText +uid 180,0 +va (VaSet +fg "32768,0,0" +font "Arial,12,1" +) +xt "53250,56250,64750,57750" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 25600 +) +position 1 +ignorePrefs 1 +) +*11 (CommentText +uid 181,0 +shape (Rectangle +uid 182,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,62000,72000,64000" +) +oxt "18000,28000,39000,30000" +text (MLText +uid 183,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,62400,67500,63600" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 20600 +) +position 1 +ignorePrefs 1 +) +*12 (CommentText +uid 184,0 +shape (Rectangle +uid 185,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "72000,56000,78000,58000" +) +oxt "39000,22000,45000,24000" +text (MLText +uid 186,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "72200,56400,76900,57600" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 5600 +) +position 1 +ignorePrefs 1 +) +*13 (CommentText +uid 187,0 +shape (Rectangle +uid 188,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,58000,72000,60000" +) +oxt "18000,24000,39000,26000" +text (MLText +uid 189,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,58400,66400,59600" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 20600 +) +position 1 +ignorePrefs 1 +) +*14 (CommentText +uid 190,0 +shape (Rectangle +uid 191,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "46000,58000,51000,60000" +) +oxt "13000,24000,18000,26000" +text (MLText +uid 192,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "46200,58400,49600,59600" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 4600 +) +position 1 +ignorePrefs 1 +) +*15 (CommentText +uid 193,0 +shape (Rectangle +uid 194,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "46000,60000,51000,62000" +) +oxt "13000,26000,18000,28000" +text (MLText +uid 195,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "46200,60400,49600,61600" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 4600 +) +position 1 +ignorePrefs 1 +) +*16 (CommentText +uid 196,0 +shape (Rectangle +uid 197,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "72000,58000,97000,64000" +) +oxt "39000,24000,64000,30000" +text (MLText +uid 198,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "72200,58200,86300,59400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 5600 +visibleWidth 24600 +) +ignorePrefs 1 +) +*17 (CommentText +uid 199,0 +shape (Rectangle +uid 200,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,60000,72000,62000" +) +oxt "18000,26000,39000,28000" +text (MLText +uid 201,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,60400,64600,61600" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 20600 +) +position 1 +ignorePrefs 1 +) +*18 (CommentText +uid 202,0 +shape (Rectangle +uid 203,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "46000,62000,51000,64000" +) +oxt "13000,28000,18000,30000" +text (MLText +uid 204,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "46200,62400,50500,63600" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 4600 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 174,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 1 +) +xt "46000,56000,97000,64000" +) +oxt "13000,22000,64000,30000" +) +*19 (State +uid 205,0 +shape (Circle +uid 206,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "21977,10977,28023,17023" +radius 3023 +) +name (Text +uid 207,0 +va (VaSet +font "Verdana,10,1" +) +xt "23050,13400,26950,14600" +st "home" +ju 0 +blo "25000,14400" +tm "ONodeName" +) +wait (TextAssociate +uid 208,0 +ps "CenterOffsetStrategy" +text (Text +uid 209,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "25000,14300,29100,15500" +st "wait 2" +blo "25000,15300" +tm "SmWaitText" +) +) +encoding (Text +uid 210,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "25000,15000,25000,15000" +blo "25000,15000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 213,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 214,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "12950,16900,45050,19100" +) +autoResize 1 +tline (Line +uid 215,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "13050,16800,44950,16800" +pts [ +"13050,16800" +"44950,16800" +] +) +bline (Line +uid 216,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "13050,16900,44950,16900" +pts [ +"13050,16900" +"44950,16900" +] +) +ttri (Triangle +uid 217,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "12600,16425,12950,16775" +) +btri (Triangle +uid 218,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "12600,14625,12950,14975" +) +entryActions (MLText +uid 219,0 +va (VaSet +) +xt "13050,16600,13050,16600" +tm "Actions" +) +inActions (MLText +uid 220,0 +va (VaSet +) +xt "13050,17000,53050,19400" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos(stx), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 221,0 +va (VaSet +) +xt "25000,14800,25000,14800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 211,0 +ps "CenterOffsetStrategy" +text (MLText +uid 212,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "22950,15000,29050,16000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*20 (State +uid 222,0 +shape (Circle +uid 223,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "9977,22977,16023,29023" +radius 3023 +) +name (Text +uid 224,0 +va (VaSet +font "Verdana,10,1" +) +xt "12250,25400,13750,26600" +st "H" +ju 0 +blo "13000,26400" +tm "ONodeName" +) +wait (TextAssociate +uid 225,0 +ps "CenterOffsetStrategy" +text (Text +uid 226,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "13000,26300,17100,27500" +st "wait 2" +blo "13000,27300" +tm "SmWaitText" +) +) +encoding (Text +uid 227,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "13000,27000,13000,27000" +blo "13000,27000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 230,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 231,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "1050,28100,32950,30300" +) +autoResize 1 +tline (Line +uid 232,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "1150,28000,32850,28000" +pts [ +"1150,28000" +"32850,28000" +] +) +bline (Line +uid 233,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "1150,28100,32850,28100" +pts [ +"1150,28100" +"32850,28100" +] +) +ttri (Triangle +uid 234,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "700,27625,1050,27975" +) +btri (Triangle +uid 235,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "700,25825,1050,26175" +) +entryActions (MLText +uid 236,0 +va (VaSet +) +xt "1150,27800,1150,27800" +tm "Actions" +) +inActions (MLText +uid 237,0 +va (VaSet +) +xt "1150,28200,40950,30600" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('H'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 238,0 +va (VaSet +) +xt "13000,26000,13000,26000" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 228,0 +ps "CenterOffsetStrategy" +text (MLText +uid 229,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "10950,27000,17050,28000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*21 (State +uid 239,0 +shape (Circle +uid 240,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "21977,22977,28023,29023" +radius 3023 +) +name (Text +uid 241,0 +va (VaSet +font "Verdana,10,1" +) +xt "24300,25400,25700,26600" +st "e" +ju 0 +blo "25000,26400" +tm "ONodeName" +) +wait (TextAssociate +uid 242,0 +ps "CenterOffsetStrategy" +text (Text +uid 243,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "25000,26300,29100,27500" +st "wait 2" +blo "25000,27300" +tm "SmWaitText" +) +) +encoding (Text +uid 244,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "25000,27000,25000,27000" +blo "25000,27000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 247,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 248,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "13100,28900,44900,31100" +) +autoResize 1 +tline (Line +uid 249,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "13200,28800,44800,28800" +pts [ +"13200,28800" +"44800,28800" +] +) +bline (Line +uid 250,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "13200,28900,44800,28900" +pts [ +"13200,28900" +"44800,28900" +] +) +ttri (Triangle +uid 251,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "12750,28425,13100,28775" +) +btri (Triangle +uid 252,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "12750,26625,13100,26975" +) +entryActions (MLText +uid 253,0 +va (VaSet +) +xt "13200,28600,13200,28600" +tm "Actions" +) +inActions (MLText +uid 254,0 +va (VaSet +) +xt "13200,29000,52800,31400" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('e'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 255,0 +va (VaSet +) +xt "25000,26800,25000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 245,0 +ps "CenterOffsetStrategy" +text (MLText +uid 246,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "22950,27000,29050,28000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*22 (State +uid 286,0 +shape (Circle +uid 287,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "33977,22977,40023,29023" +radius 3023 +) +name (Text +uid 288,0 +va (VaSet +font "Verdana,10,1" +) +xt "36500,25400,37500,26600" +st "l" +ju 0 +blo "37000,26400" +tm "ONodeName" +) +wait (TextAssociate +uid 289,0 +ps "CenterOffsetStrategy" +text (Text +uid 290,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "37000,26300,41100,27500" +st "wait 2" +blo "37000,27300" +tm "SmWaitText" +) +) +encoding (Text +uid 291,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "37000,27000,37000,27000" +blo "37000,27000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 294,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 295,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "25250,29900,56750,32100" +) +autoResize 1 +tline (Line +uid 296,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "25350,29800,56650,29800" +pts [ +"25350,29800" +"56650,29800" +] +) +bline (Line +uid 297,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "25350,29900,56650,29900" +pts [ +"25350,29900" +"56650,29900" +] +) +ttri (Triangle +uid 298,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24900,29425,25250,29775" +) +btri (Triangle +uid 299,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24900,27625,25250,27975" +) +entryActions (MLText +uid 300,0 +va (VaSet +) +xt "25350,29600,25350,29600" +tm "Actions" +) +inActions (MLText +uid 301,0 +va (VaSet +) +xt "25350,30000,64650,32400" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('l'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 302,0 +va (VaSet +) +xt "37000,27800,37000,27800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 292,0 +ps "CenterOffsetStrategy" +text (MLText +uid 293,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "34950,27000,41050,28000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*23 (State +uid 303,0 +shape (Circle +uid 304,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "45977,22977,52023,29023" +radius 3023 +) +name (Text +uid 305,0 +va (VaSet +font "Verdana,10,1" +) +xt "48150,25400,49850,26600" +st "l2" +ju 0 +blo "49000,26400" +tm "ONodeName" +) +wait (TextAssociate +uid 306,0 +ps "CenterOffsetStrategy" +text (Text +uid 307,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "49000,26300,53100,27500" +st "wait 2" +blo "49000,27300" +tm "SmWaitText" +) +) +encoding (Text +uid 308,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "49000,27000,49000,27000" +blo "49000,27000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 311,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 312,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "37250,28100,68750,30300" +) +autoResize 1 +tline (Line +uid 313,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "37350,28000,68650,28000" +pts [ +"37350,28000" +"68650,28000" +] +) +bline (Line +uid 314,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "37350,28100,68650,28100" +pts [ +"37350,28100" +"68650,28100" +] +) +ttri (Triangle +uid 315,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "36900,27625,37250,27975" +) +btri (Triangle +uid 316,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "36900,25825,37250,26175" +) +entryActions (MLText +uid 317,0 +va (VaSet +) +xt "37350,27800,37350,27800" +tm "Actions" +) +inActions (MLText +uid 318,0 +va (VaSet +) +xt "37350,28200,76650,30600" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('l'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 319,0 +va (VaSet +) +xt "49000,26000,49000,26000" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 309,0 +ps "CenterOffsetStrategy" +text (MLText +uid 310,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "46950,27000,53050,28000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*24 (State +uid 330,0 +shape (Circle +uid 331,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "57977,22977,64023,29023" +radius 3023 +) +name (Text +uid 332,0 +va (VaSet +font "Verdana,10,1" +) +xt "60300,25400,61700,26600" +st "o" +ju 0 +blo "61000,26400" +tm "ONodeName" +) +wait (TextAssociate +uid 333,0 +ps "CenterOffsetStrategy" +text (Text +uid 334,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "61000,26300,65100,27500" +st "wait 2" +blo "61000,27300" +tm "SmWaitText" +) +) +encoding (Text +uid 335,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "61000,27000,61000,27000" +blo "61000,27000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 338,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 339,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "49100,28900,80900,31100" +) +autoResize 1 +tline (Line +uid 340,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "49200,28800,80800,28800" +pts [ +"49200,28800" +"80800,28800" +] +) +bline (Line +uid 341,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "49200,28900,80800,28900" +pts [ +"49200,28900" +"80800,28900" +] +) +ttri (Triangle +uid 342,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "48750,28425,49100,28775" +) +btri (Triangle +uid 343,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "48750,26625,49100,26975" +) +entryActions (MLText +uid 344,0 +va (VaSet +) +xt "49200,28600,49200,28600" +tm "Actions" +) +inActions (MLText +uid 345,0 +va (VaSet +) +xt "49200,29000,88800,31400" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('o'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 346,0 +va (VaSet +) +xt "61000,26800,61000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 336,0 +ps "CenterOffsetStrategy" +text (MLText +uid 337,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "58950,27000,65050,28000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*25 (State +uid 347,0 +shape (Circle +uid 348,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "69977,22977,76023,29023" +radius 3023 +) +name (Text +uid 349,0 +va (VaSet +font "Verdana,10,1" +) +xt "72100,25400,73900,26600" +st "cr" +ju 0 +blo "73000,26400" +tm "ONodeName" +) +wait (TextAssociate +uid 350,0 +ps "CenterOffsetStrategy" +text (Text +uid 351,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "73000,26300,77100,27500" +st "wait 2" +blo "73000,27300" +tm "SmWaitText" +) +) +encoding (Text +uid 352,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "73000,27000,73000,27000" +blo "73000,27000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 355,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 356,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "61200,29900,92800,32100" +) +autoResize 1 +tline (Line +uid 357,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "61300,29800,92700,29800" +pts [ +"61300,29800" +"92700,29800" +] +) +bline (Line +uid 358,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "61300,29900,92700,29900" +pts [ +"61300,29900" +"92700,29900" +] +) +ttri (Triangle +uid 359,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "60850,29425,61200,29775" +) +btri (Triangle +uid 360,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "60850,27625,61200,27975" +) +entryActions (MLText +uid 361,0 +va (VaSet +) +xt "61300,29600,61300,29600" +tm "Actions" +) +inActions (MLText +uid 362,0 +va (VaSet +) +xt "61300,30000,100700,32400" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos(cr), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 363,0 +va (VaSet +) +xt "73000,27800,73000,27800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 353,0 +ps "CenterOffsetStrategy" +text (MLText +uid 354,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "70950,27000,77050,28000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*26 (State +uid 394,0 +shape (Circle +uid 395,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "81977,22977,88023,29023" +radius 3023 +) +name (Text +uid 396,0 +va (VaSet +font "Verdana,10,1" +) +xt "84250,25400,85750,26600" +st "lf" +ju 0 +blo "85000,26400" +tm "ONodeName" +) +wait (TextAssociate +uid 397,0 +ps "CenterOffsetStrategy" +text (Text +uid 398,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "85000,26300,89100,27500" +st "wait 2" +blo "85000,27300" +tm "SmWaitText" +) +) +encoding (Text +uid 399,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "85000,27000,85000,27000" +blo "85000,27000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 402,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 403,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "73300,28100,104700,30300" +) +autoResize 1 +tline (Line +uid 404,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73400,28000,104600,28000" +pts [ +"73400,28000" +"104600,28000" +] +) +bline (Line +uid 405,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73400,28100,104600,28100" +pts [ +"73400,28100" +"104600,28100" +] +) +ttri (Triangle +uid 406,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "72950,27625,73300,27975" +) +btri (Triangle +uid 407,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "72950,25825,73300,26175" +) +entryActions (MLText +uid 408,0 +va (VaSet +) +xt "73400,27800,73400,27800" +tm "Actions" +) +inActions (MLText +uid 409,0 +va (VaSet +) +xt "73400,28200,112400,30600" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos(lf), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 410,0 +va (VaSet +) +xt "85000,26000,85000,26000" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 400,0 +ps "CenterOffsetStrategy" +text (MLText +uid 401,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "82950,27000,89050,28000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*27 (State +uid 421,0 +shape (Circle +uid 422,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "9977,34977,16023,41023" +radius 3023 +) +name (Text +uid 423,0 +va (VaSet +font "Verdana,10,1" +) +xt "12050,37400,13950,38600" +st "W" +ju 0 +blo "13000,38400" +tm "ONodeName" +) +wait (TextAssociate +uid 424,0 +ps "CenterOffsetStrategy" +text (Text +uid 425,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "13000,38300,17100,39500" +st "wait 2" +blo "13000,39300" +tm "SmWaitText" +) +) +encoding (Text +uid 426,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "13000,39000,13000,39000" +blo "13000,39000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 429,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 430,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "950,40100,33050,42300" +) +autoResize 1 +tline (Line +uid 431,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "1050,40000,32950,40000" +pts [ +"1050,40000" +"32950,40000" +] +) +bline (Line +uid 432,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "1050,40100,32950,40100" +pts [ +"1050,40100" +"32950,40100" +] +) +ttri (Triangle +uid 433,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "600,39625,950,39975" +) +btri (Triangle +uid 434,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "600,37825,950,38175" +) +entryActions (MLText +uid 435,0 +va (VaSet +) +xt "1050,39800,1050,39800" +tm "Actions" +) +inActions (MLText +uid 436,0 +va (VaSet +) +xt "1050,40200,40950,42600" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('W'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 437,0 +va (VaSet +) +xt "13000,38000,13000,38000" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 427,0 +ps "CenterOffsetStrategy" +text (MLText +uid 428,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "10950,39000,17050,40000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*28 (State +uid 438,0 +shape (Circle +uid 439,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "21977,34977,28023,41023" +radius 3023 +) +name (Text +uid 440,0 +va (VaSet +font "Verdana,10,1" +) +xt "23950,37400,26050,38600" +st "o2" +ju 0 +blo "25000,38400" +tm "ONodeName" +) +wait (TextAssociate +uid 441,0 +ps "CenterOffsetStrategy" +text (Text +uid 442,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "25000,38300,29100,39500" +st "wait 2" +blo "25000,39300" +tm "SmWaitText" +) +) +encoding (Text +uid 443,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "25000,39000,25000,39000" +blo "25000,39000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 446,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 447,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "13100,40900,44900,43100" +) +autoResize 1 +tline (Line +uid 448,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "13200,40800,44800,40800" +pts [ +"13200,40800" +"44800,40800" +] +) +bline (Line +uid 449,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "13200,40900,44800,40900" +pts [ +"13200,40900" +"44800,40900" +] +) +ttri (Triangle +uid 450,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "12750,40425,13100,40775" +) +btri (Triangle +uid 451,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "12750,38625,13100,38975" +) +entryActions (MLText +uid 452,0 +va (VaSet +) +xt "13200,40600,13200,40600" +tm "Actions" +) +inActions (MLText +uid 453,0 +va (VaSet +) +xt "13200,41000,52800,43400" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('o'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 454,0 +va (VaSet +) +xt "25000,38800,25000,38800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 444,0 +ps "CenterOffsetStrategy" +text (MLText +uid 445,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "22950,39000,29050,40000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*29 (State +uid 455,0 +shape (Circle +uid 456,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "33977,34977,40023,41023" +radius 3023 +) +name (Text +uid 457,0 +va (VaSet +font "Verdana,10,1" +) +xt "36400,37400,37600,38600" +st "r" +ju 0 +blo "37000,38400" +tm "ONodeName" +) +wait (TextAssociate +uid 458,0 +ps "CenterOffsetStrategy" +text (Text +uid 459,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "37000,38300,41100,39500" +st "wait 2" +blo "37000,39300" +tm "SmWaitText" +) +) +encoding (Text +uid 460,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "37000,39000,37000,39000" +blo "37000,39000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 463,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 464,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "25200,41900,56800,44100" +) +autoResize 1 +tline (Line +uid 465,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "25300,41800,56700,41800" +pts [ +"25300,41800" +"56700,41800" +] +) +bline (Line +uid 466,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "25300,41900,56700,41900" +pts [ +"25300,41900" +"56700,41900" +] +) +ttri (Triangle +uid 467,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24850,41425,25200,41775" +) +btri (Triangle +uid 468,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24850,39625,25200,39975" +) +entryActions (MLText +uid 469,0 +va (VaSet +) +xt "25300,41600,25300,41600" +tm "Actions" +) +inActions (MLText +uid 470,0 +va (VaSet +) +xt "25300,42000,64700,44400" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('r'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 471,0 +va (VaSet +) +xt "37000,39800,37000,39800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 461,0 +ps "CenterOffsetStrategy" +text (MLText +uid 462,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "34950,39000,41050,40000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*30 (State +uid 472,0 +shape (Circle +uid 473,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "45977,34977,52023,41023" +radius 3023 +) +name (Text +uid 474,0 +va (VaSet +font "Verdana,10,1" +) +xt "48150,37400,49850,38600" +st "l3" +ju 0 +blo "49000,38400" +tm "ONodeName" +) +wait (TextAssociate +uid 475,0 +ps "CenterOffsetStrategy" +text (Text +uid 476,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "49000,38300,53100,39500" +st "wait 2" +blo "49000,39300" +tm "SmWaitText" +) +) +encoding (Text +uid 477,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "49000,39000,49000,39000" +blo "49000,39000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 480,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 481,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "37250,40100,68750,42300" +) +autoResize 1 +tline (Line +uid 482,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "37350,40000,68650,40000" +pts [ +"37350,40000" +"68650,40000" +] +) +bline (Line +uid 483,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "37350,40100,68650,40100" +pts [ +"37350,40100" +"68650,40100" +] +) +ttri (Triangle +uid 484,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "36900,39625,37250,39975" +) +btri (Triangle +uid 485,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "36900,37825,37250,38175" +) +entryActions (MLText +uid 486,0 +va (VaSet +) +xt "37350,39800,37350,39800" +tm "Actions" +) +inActions (MLText +uid 487,0 +va (VaSet +) +xt "37350,40200,76650,42600" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('l'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 488,0 +va (VaSet +) +xt "49000,38000,49000,38000" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 478,0 +ps "CenterOffsetStrategy" +text (MLText +uid 479,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "46950,39000,53050,40000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*31 (State +uid 489,0 +shape (Circle +uid 490,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "57977,34977,64023,41023" +radius 3023 +) +name (Text +uid 491,0 +va (VaSet +font "Verdana,10,1" +) +xt "60300,37400,61700,38600" +st "d" +ju 0 +blo "61000,38400" +tm "ONodeName" +) +wait (TextAssociate +uid 492,0 +ps "CenterOffsetStrategy" +text (Text +uid 493,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "61000,38300,65100,39500" +st "wait 2" +blo "61000,39300" +tm "SmWaitText" +) +) +encoding (Text +uid 494,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "61000,39000,61000,39000" +blo "61000,39000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 497,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 498,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "49100,40900,80900,43100" +) +autoResize 1 +tline (Line +uid 499,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "49200,40800,80800,40800" +pts [ +"49200,40800" +"80800,40800" +] +) +bline (Line +uid 500,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "49200,40900,80800,40900" +pts [ +"49200,40900" +"80800,40900" +] +) +ttri (Triangle +uid 501,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "48750,40425,49100,40775" +) +btri (Triangle +uid 502,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "48750,38625,49100,38975" +) +entryActions (MLText +uid 503,0 +va (VaSet +) +xt "49200,40600,49200,40600" +tm "Actions" +) +inActions (MLText +uid 504,0 +va (VaSet +) +xt "49200,41000,88800,43400" +st "ascii <= std_ulogic_vector(to_unsigned(character'pos('d'), ascii'length)); +send <= not busy;" +tm "Actions" +) +exitActions (MLText +uid 505,0 +va (VaSet +) +xt "61000,38800,61000,38800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 495,0 +ps "CenterOffsetStrategy" +text (MLText +uid 496,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "58950,39000,65050,40000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*32 (State +uid 602,0 +shape (Circle +uid 603,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "9977,46977,16023,53023" +radius 3023 +) +name (Text +uid 604,0 +va (VaSet +font "Verdana,10,1" +) +xt "11650,49400,14350,50600" +st "idle" +ju 0 +blo "13000,50400" +tm "ONodeName" +) +wait (TextAssociate +uid 605,0 +ps "CenterOffsetStrategy" +text (Text +uid 606,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "13000,50300,17100,51500" +st "wait 2" +blo "13000,51300" +tm "SmWaitText" +) +) +encoding (Text +uid 607,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "13000,51000,13000,51000" +blo "13000,51000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 610,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 611,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "16900,53900,17100,54100" +) +autoResize 1 +tline (Line +uid 612,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "1200,52800,32800,52800" +pts [ +"1200,52800" +"32800,52800" +] +) +bline (Line +uid 613,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "1200,52900,32800,52900" +pts [ +"1200,52900" +"32800,52900" +] +) +ttri (Triangle +uid 614,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "12550,52425,12900,52775" +) +btri (Triangle +uid 615,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "12550,50625,12900,50975" +) +entryActions (MLText +uid 616,0 +va (VaSet +) +xt "1200,52600,1200,52600" +tm "Actions" +) +inActions (MLText +uid 617,0 +va (VaSet +) +xt "1200,53000,32800,55000" +tm "Actions" +) +exitActions (MLText +uid 618,0 +va (VaSet +) +xt "13000,50800,13000,50800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 608,0 +ps "CenterOffsetStrategy" +text (MLText +uid 609,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "10950,51000,17050,52000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*33 (Transition +uid 100,0 +shape (Spline +uid 101,0 +va (VaSet +vasetType 3 +) +xt "79500,7000,87000,7000" +pts [ +"79500,7000" +"87000,7000" +] +) +start &4 +end &5 +ss 0 +es 0 +cond "reset = '1'" +tb (TransitionBlock +uid 102,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 103,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "80900,6000,88500,8200" +) +autoResize 1 +lineShape (Line +uid 104,0 +va (VaSet +vasetType 3 +) +xt "81400,7600,88000,7600" +pts [ +"81400,7600" +"88000,7600" +] +) +condition (MLText +uid 105,0 +va (VaSet +) +xt "81400,6000,88000,7200" +st "reset = '1'" +tm "Condition" +) +actions (MLText +uid 106,0 +va (VaSet +isHidden 1 +) +xt "80400,8000,89000,9200" +st "< Automatic >" +tm "Actions" +) +) +tp (TransitionPriority +uid 107,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 108,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "79261,6011,81239,7989" +radius 989 +) +pr (Text +uid 109,0 +va (VaSet +isHidden 1 +) +xt "79750,6500,80750,7500" +st "1" +ju 0 +blo "80250,7300" +tm "TransitionPriority" +) +padding "200,200" +) +) +*34 (Transition +uid 110,0 +shape (Spline +uid 111,0 +va (VaSet +vasetType 3 +) +xt "78900,9000,87000,9000" +pts [ +"78900,9000" +"87000,9000" +] +) +start &6 +end &7 +ss 0 +es 0 +tb (TransitionBlock +uid 112,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 113,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "80400,8495,85500,9505" +) +autoResize 1 +lineShape (Line +uid 114,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "82950,9900,82950,9900" +pts [ +"82950,9900" +"82950,9900" +] +) +condition (MLText +uid 115,0 +va (VaSet +) +xt "80900,8500,85000,9500" +tm "Condition" +) +actions (MLText +uid 116,0 +va (VaSet +) +xt "82950,9900,82950,9900" +tm "Actions" +) +) +tp (TransitionPriority +uid 117,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 118,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "78721,8011,80699,9989" +radius 989 +) +pr (Text +uid 119,0 +va (VaSet +isHidden 1 +) +xt "79210,8500,80210,9500" +st "1" +ju 0 +blo "79710,9300" +tm "TransitionPriority" +) +padding "200,200" +) +) +*35 (Transition +uid 256,0 +shape (Spline +uid 257,0 +va (VaSet +vasetType 3 +) +xt "16023,14017,21977,14021" +pts [ +"16023,14017" +"21977,14021" +] +arrow 1 +) +start &2 +end &19 +cond "busy = '0'" +tb (TransitionBlock +uid 258,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 259,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "15950,12000,22050,14000" +) +autoResize 1 +lineShape (Line +uid 260,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "18500,13900,18500,13900" +pts [ +"18500,13900" +"18500,13900" +] +) +condition (MLText +uid 261,0 +va (VaSet +) +xt "16450,12500,22850,13700" +st "busy = '0'" +tm "Condition" +) +actions (MLText +uid 262,0 +va (VaSet +) +xt "19000,13900,19000,13900" +tm "Actions" +) +) +tp (TransitionPriority +uid 263,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 264,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "15629,13028,17607,15006" +radius 989 +) +pr (Text +uid 265,0 +va (VaSet +isHidden 1 +) +xt "16118,13517,17118,14517" +st "1" +ju 0 +blo "16618,14317" +tm "TransitionPriority" +) +padding "200,200" +) +) +*36 (Transition +uid 266,0 +shape (Spline +uid 267,0 +va (VaSet +vasetType 3 +) +xt "14825,15917,22662,23591" +pts [ +"22662,15917" +"14825,23591" +] +arrow 1 +) +start &19 +end &20 +cond "busy = '0'" +tb (TransitionBlock +uid 268,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 269,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "18243,19254,24343,21254" +) +autoResize 1 +lineShape (Line +uid 270,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "20793,21154,20793,21154" +pts [ +"20793,21154" +"20793,21154" +] +) +condition (MLText +uid 271,0 +va (VaSet +) +xt "18743,19754,25143,20954" +st "busy = '0'" +tm "Condition" +) +actions (MLText +uid 272,0 +va (VaSet +) +xt "21293,21154,21293,21154" +tm "Actions" +) +) +tp (TransitionPriority +uid 273,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 274,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "20889,15694,22867,17672" +radius 989 +) +pr (Text +uid 275,0 +va (VaSet +isHidden 1 +) +xt "21378,16183,22378,17183" +st "1" +ju 0 +blo "21878,16983" +tm "TransitionPriority" +) +padding "200,200" +) +) +*37 (Transition +uid 276,0 +shape (Spline +uid 277,0 +va (VaSet +vasetType 3 +) +xt "16023,25972,21977,25974" +pts [ +"16023,25974" +"21977,25972" +] +arrow 1 +) +start &20 +end &21 +cond "busy = '0'" +tb (TransitionBlock +uid 278,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 279,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "15950,24000,22050,26000" +) +autoResize 1 +lineShape (Line +uid 280,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "18500,25900,18500,25900" +pts [ +"18500,25900" +"18500,25900" +] +) +condition (MLText +uid 281,0 +va (VaSet +) +xt "16450,24500,22850,25700" +st "busy = '0'" +tm "Condition" +) +actions (MLText +uid 282,0 +va (VaSet +) +xt "19000,25900,19000,25900" +tm "Actions" +) +) +tp (TransitionPriority +uid 283,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 284,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "15629,24984,17607,26962" +radius 989 +) +pr (Text +uid 285,0 +va (VaSet +isHidden 1 +) +xt "16118,25473,17118,26473" +st "1" +ju 0 +blo "16618,26273" +tm "TransitionPriority" +) +padding "200,200" +) +) +*38 (Transition +uid 320,0 +shape (Spline +uid 321,0 +va (VaSet +vasetType 3 +) +xt "40023,25972,45977,25974" +pts [ +"40023,25974" +"45977,25972" +] +arrow 1 +) +start &22 +end &23 +cond "busy = '0'" +tb (TransitionBlock +uid 322,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 323,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "39950,24000,46050,26000" +) +autoResize 1 +lineShape (Line +uid 324,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "42500,25900,42500,25900" +pts [ +"42500,25900" +"42500,25900" +] +) +condition (MLText +uid 325,0 +va (VaSet +) +xt "40450,24500,46850,25700" +st "busy = '0'" +tm "Condition" +) +actions (MLText +uid 326,0 +va (VaSet +) +xt "43000,25900,43000,25900" +tm "Actions" +) +) +tp (TransitionPriority +uid 327,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 328,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "39629,24984,41607,26962" +radius 989 +) +pr (Text +uid 329,0 +va (VaSet +isHidden 1 +) +xt "40118,25473,41118,26473" +st "1" +ju 0 +blo "40618,26273" +tm "TransitionPriority" +) +padding "200,200" +) +) +*39 (Transition +uid 364,0 +shape (Spline +uid 365,0 +va (VaSet +vasetType 3 +) +xt "64023,25972,69977,25974" +pts [ +"64023,25974" +"69977,25972" +] +arrow 1 +) +start &24 +end &25 +cond "busy = '0'" +tb (TransitionBlock +uid 366,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 367,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "63950,24000,70050,26000" +) +autoResize 1 +lineShape (Line +uid 368,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "66500,25900,66500,25900" +pts [ +"66500,25900" +"66500,25900" +] +) +condition (MLText +uid 369,0 +va (VaSet +) +xt "64450,24500,70850,25700" +st "busy = '0'" +tm "Condition" +) +actions (MLText +uid 370,0 +va (VaSet +) +xt "67000,25900,67000,25900" +tm "Actions" +) +) +tp (TransitionPriority +uid 371,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 372,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "63629,24984,65607,26962" +radius 989 +) +pr (Text +uid 373,0 +va (VaSet +isHidden 1 +) +xt "64118,25473,65118,26473" +st "1" +ju 0 +blo "64618,26273" +tm "TransitionPriority" +) +padding "200,200" +) +) +*40 (Transition +uid 374,0 +shape (Spline +uid 375,0 +va (VaSet +vasetType 3 +) +xt "28023,25971,33977,25975" +pts [ +"28023,25975" +"33977,25971" +] +arrow 1 +) +start &21 +end &22 +cond "busy = '0'" +tb (TransitionBlock +uid 376,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 377,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "27950,24000,34050,26000" +) +autoResize 1 +lineShape (Line +uid 378,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "30500,25900,30500,25900" +pts [ +"30500,25900" +"30500,25900" +] +) +condition (MLText +uid 379,0 +va (VaSet +) +xt "28450,24500,34850,25700" +st "busy = '0'" +tm "Condition" +) +actions (MLText +uid 380,0 +va (VaSet +) +xt "31000,25900,31000,25900" +tm "Actions" +) +) +tp (TransitionPriority +uid 381,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 382,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "27629,24985,29607,26963" +radius 989 +) +pr (Text +uid 383,0 +va (VaSet +isHidden 1 +) +xt "28118,25474,29118,26474" +st "1" +ju 0 +blo "28618,26274" +tm "TransitionPriority" +) +padding "200,200" +) +) +*41 (Transition +uid 384,0 +shape (Spline +uid 385,0 +va (VaSet +vasetType 3 +) +xt "52023,26030,57977,26030" +pts [ +"52023,26030" +"57977,26030" +] +arrow 1 +) +start &23 +end &24 +cond "busy = '0'" +tb (TransitionBlock +uid 386,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 387,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "51950,24000,58050,26000" +) +autoResize 1 +lineShape (Line +uid 388,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "54500,25900,54500,25900" +pts [ +"54500,25900" +"54500,25900" +] +) +condition (MLText +uid 389,0 +va (VaSet +) +xt "52450,24500,58850,25700" +st "busy = '0'" +tm "Condition" +) +actions (MLText +uid 390,0 +va (VaSet +) +xt "55000,25900,55000,25900" +tm "Actions" +) +) +tp (TransitionPriority +uid 391,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 392,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "51629,25041,53607,27019" +radius 989 +) +pr (Text +uid 393,0 +va (VaSet +isHidden 1 +) +xt "52118,25530,53118,26530" +st "1" +ju 0 +blo "52618,26330" +tm "TransitionPriority" +) +padding "200,200" +) +) +*42 (Transition +uid 411,0 +shape (Spline +uid 412,0 +va (VaSet +vasetType 3 +) +xt "76023,25971,81977,25975" +pts [ +"76023,25975" +"81977,25971" +] +arrow 1 +) +start &25 +end &26 +cond "busy = '0'" +tb (TransitionBlock +uid 413,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 414,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "75950,24000,82050,26000" +) +autoResize 1 +lineShape (Line +uid 415,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "78500,25900,78500,25900" +pts [ +"78500,25900" +"78500,25900" +] +) +condition (MLText +uid 416,0 +va (VaSet +) +xt "76450,24500,82850,25700" +st "busy = '0'" +tm "Condition" +) +actions (MLText +uid 417,0 +va (VaSet +) +xt "79000,25900,79000,25900" +tm "Actions" +) +) +tp (TransitionPriority +uid 418,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 419,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "75629,24985,77607,26963" +radius 989 +) +pr (Text +uid 420,0 +va (VaSet +isHidden 1 +) +xt "76118,25474,77118,26474" +st "1" +ju 0 +blo "76618,26274" +tm "TransitionPriority" +) +padding "200,200" +) +) +*43 (Transition +uid 506,0 +shape (Spline +uid 507,0 +va (VaSet +vasetType 3 +) +xt "40023,37972,45977,37974" +pts [ +"40023,37974" +"45977,37972" +] +arrow 1 +) +start &29 +end &30 +cond "busy = '0'" +tb (TransitionBlock +uid 508,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 509,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "39950,36000,46050,38000" +) +autoResize 1 +lineShape (Line +uid 510,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "42500,37900,42500,37900" +pts [ +"42500,37900" +"42500,37900" +] +) +condition (MLText +uid 511,0 +va (VaSet +) +xt "40450,36500,46850,37700" +st "busy = '0'" +tm "Condition" +) +actions (MLText +uid 512,0 +va (VaSet +) +xt "43000,37900,43000,37900" +tm "Actions" +) +) +tp (TransitionPriority +uid 513,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 514,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "39629,36984,41607,38962" +radius 989 +) +pr (Text +uid 515,0 +va (VaSet +isHidden 1 +) +xt "40118,37473,41118,38473" +st "1" +ju 0 +blo "40618,38273" +tm "TransitionPriority" +) +padding "200,200" +) +) +*44 (Transition +uid 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constant pwmLowpassAddBitNb: positive :=8; + constant voltageToSpeedBitNb: positive := 8; + signal side1Acc: unsigned(pwmReadBitNb+pwmLowpassAddBitNb-1 downto 0) := (others => '0'); + signal side2Acc: unsigned(pwmReadBitNb+pwmLowpassAddBitNb-1 downto 0) := (others => '0'); + signal side1M: unsigned(pwmReadBitNb-1 downto 0); + signal side2M: unsigned(pwmReadBitNb-1 downto 0); + signal position: signed(pwmReadBitNb+voltageToSpeedBitNb-1 downto 0) := (others => '0'); + signal stepCount: unsigned(1 downto 0); + +BEGIN + + ------------------------------------------------------------------------------ + -- clock and reset + -- + reset <= '1', '0' after 2*clockPeriod; + + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + + + ------------------------------------------------------------------------------ + -- test sequence + -- + process + begin + + testMode_int <= '1'; + + restart <= '0'; + go1 <= '0'; + go2 <= '0'; + button4 <= '0'; + + sensor1 <= '0'; + sensor2 <= '0'; + + wait for 0.1 ms; + + ---------------------------------------------------------------------------- + -- restart + restart <= '1', '0' after buttonsPulseWidth; + wait for 0.25 ms; + sensor1 <= '1', '0' after buttonsPulseWidth; + wait for 0.25 ms; + + ---------------------------------------------------------------------------- + -- advance to first stop point + go1 <= '1', '0' after buttonsPulseWidth; + wait for 2 ms; + + ---------------------------------------------------------------------------- + -- advance to second stop point + go2 <= '1', '0' after buttonsPulseWidth; + wait for 2 ms; + + ---------------------------------------------------------------------------- + -- go back to first stop point + go1 <= '1', '0' after buttonsPulseWidth; + wait for 2 ms; + + ---------------------------------------------------------------------------- + -- back to start with sensor reset + restart <= '1', '0' after buttonsPulseWidth; + wait for 0.5 ms; + sensor1 <= '1', '0' after buttonsPulseWidth; + wait for 0.5 ms; + + ---------------------------------------------------------------------------- + -- advance to second stop point + go2 <= '1', '0' after buttonsPulseWidth; + wait for 3 ms; + + ---------------------------------------------------------------------------- + -- back to start with counter stop + restart <= '1', '0' after buttonsPulseWidth; + wait for 2 ms; + sensor1 <= '1', '0' after buttonsPulseWidth; + wait for 1 ms; + + ---------------------------------------------------------------------------- + -- quit test mode + testMode_int <= '0'; + + ---------------------------------------------------------------------------- + -- advance to first stop point + go1 <= '1', '0' after buttonsPulseWidth; + wait for 2 ms; + + wait; + end process; + + testMode <= testMode_int; + + ------------------------------------------------------------------------------ + -- PWM lowpass + -- + process(sClock) + begin + if rising_edge(sClock) then + if side1 = '1' then + side1Acc <= side1Acc + 2**pwmReadBitNb-1 - shift_right(side1Acc, pwmLowpassAddBitNb); + else + side1Acc <= side1Acc - shift_right(side1Acc, pwmLowpassAddBitNb); + end if; + if side2 = '1' then + side2Acc <= side2Acc + 2**pwmReadBitNb-1 - shift_right(side2Acc, pwmLowpassAddBitNb); + else + side2Acc <= side2Acc - shift_right(side2Acc, pwmLowpassAddBitNb); + end if; + end if; + end process; + + side1M <= resize(shift_right(side1Acc, pwmLowpassAddBitNb), side1M'length); + side2M <= resize(shift_right(side2Acc, pwmLowpassAddBitNb), side2M'length); + + ------------------------------------------------------------------------------ + -- motor feedback + -- + count: process (sClock) + begin + if motorOn = '1' then + if testMode_int = '0' then + position <= position + to_integer(side1M) - to_integer(side2M); + else + position <= position + (to_integer(side1M) - to_integer(side2M)) * 5; + end if; + end if; + end process count; + + stepCount <= resize(shift_right(unsigned(position), position'length-stepCount'length), stepCount'length); + + encoderA <= stepCount(1); + encoderB <= not stepCount(1) xor stepCount(0); + encoderI <= '1' when stepCount = pulsesPerTurn-1 else '0'; + +END ARCHITECTURE test; diff --git a/Cursor_test/hdl/divider_tester_test.vhd b/Cursor_test/hdl/divider_tester_test.vhd new file mode 100644 index 0000000..c1c8ae5 --- /dev/null +++ b/Cursor_test/hdl/divider_tester_test.vhd @@ -0,0 +1,22 @@ +ARCHITECTURE test OF divider_tester IS + + constant clockFrequency: real := 66.0E6; + constant clockPeriod: time := 1.0/clockFrequency * 1 sec; + signal sClock: std_uLogic := '1'; + +BEGIN + + reset <= '1', '0' after clockPeriod/4; + + sClock <= not sClock after clockPeriod/2; + clock <= sClock after clockPeriod/10; + + testMode <= '1', '0' after 10000*clockPeriod; + +-- start <= '0', +-- '1' after 210 us, +-- '0' after 210 us + clockPeriod, +-- '1' after 2.1 ms, +-- '0' after 2.1 ms + clockPeriod; + +END ARCHITECTURE test; diff --git a/Cursor_test/hdl/positioncounter_tester_generatedinstance.vhd b/Cursor_test/hdl/positioncounter_tester_generatedinstance.vhd new file mode 100644 index 0000000..62def87 --- /dev/null +++ b/Cursor_test/hdl/positioncounter_tester_generatedinstance.vhd @@ -0,0 +1,8 @@ +-- +-- Auto generated dummy architecture for leaf level instance. +-- +ARCHITECTURE generatedInstance OF positionCounter_tester IS +BEGIN + + +END generatedInstance; diff --git a/Cursor_test/hds/.hdlsidedata/_cursor_tb_entity.vhg._fpf b/Cursor_test/hds/.hdlsidedata/_cursor_tb_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Cursor_test/hds/.hdlsidedata/_cursor_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Cursor_test/hds/.hdlsidedata/_cursor_tb_struct.vhg._fpf b/Cursor_test/hds/.hdlsidedata/_cursor_tb_struct.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Cursor_test/hds/.hdlsidedata/_cursor_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Cursor_test/hds/.hdlsidedata/_cursor_tester_entity.vhg._fpf b/Cursor_test/hds/.hdlsidedata/_cursor_tester_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Cursor_test/hds/.hdlsidedata/_cursor_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Cursor_test/hds/.hdlsidedata/_cursor_tester_test.vhd._fpf b/Cursor_test/hds/.hdlsidedata/_cursor_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Cursor_test/hds/.hdlsidedata/_cursor_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Cursor_test/hds/.hdlsidedata/_divider_tester_test.vhd._fpf b/Cursor_test/hds/.hdlsidedata/_divider_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Cursor_test/hds/.hdlsidedata/_divider_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Cursor_test/hds/.hdlsidedata/_positioncounter_tester_generatedinstance.vhd._fpf b/Cursor_test/hds/.hdlsidedata/_positioncounter_tester_generatedinstance.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Cursor_test/hds/.hdlsidedata/_positioncounter_tester_generatedinstance.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Cursor_test/hds/_cursor_tb._epf b/Cursor_test/hds/_cursor_tb._epf new file mode 100644 index 0000000..cbaae57 --- /dev/null +++ b/Cursor_test/hds/_cursor_tb._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom cursor_tb/struct.bd diff --git a/Cursor_test/hds/_divider_tb._epf b/Cursor_test/hds/_divider_tb._epf new file mode 100644 index 0000000..6cd38ec --- /dev/null +++ b/Cursor_test/hds/_divider_tb._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom divider_tb/struct.bd diff --git a/Cursor_test/hds/_positioncounter_tb._epf b/Cursor_test/hds/_positioncounter_tb._epf new file mode 100644 index 0000000..cfbd84e --- /dev/null +++ b/Cursor_test/hds/_positioncounter_tb._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom position@counter_tb/struct.bd diff --git a/Cursor_test/hds/cursor_tb/struct.bd b/Cursor_test/hds/cursor_tb/struct.bd new file mode 100644 index 0000000..804e25a --- /dev/null +++ b/Cursor_test/hds/cursor_tb/struct.bd @@ -0,0 +1,4174 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "Cursor_test" +duName "cursor_tester" +elements [ +] +mwi 0 +uid 1774,0 +) +(Instance +name "I_DUT" +duLibraryName "Cursor" +duName "cursorCircuit" +elements [ +(GiElement +name "position0" +type "positive" +value "position0" +) +(GiElement +name "position1" +type "positive" +value "position1" +) +(GiElement +name "position2" +type "positive" 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"26368,26368,26368" +lineStyle 1 +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (MLText +va (VaSet +) +xt "0,-1400,11000,-200" +st "b0: BLOCK (guard)" +tm "FrameTitleTextMgr" +) +) +seqNum (FrameSequenceNumber +ps "TopLeftStrategy" +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "50,50,1050,1750" +) +num (Text +va (VaSet +) +xt "200,300,600,1300" +st "1" +blo "200,1100" +tm "FrameSeqNumMgr" +) +) +decls (MlTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*100 (Text +va (VaSet +font "Verdana,9,1" +) +xt "11800,20000,22600,21200" +st "Frame Declarations" +blo "11800,21000" +) +*101 (MLText +va (VaSet +) +xt "11800,21200,11800,21200" +tm "BdFrameDeclTextMgr" +) +] +) +style 3 +) +defaultSaCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f 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"-7000,25400,-1600,26400" +st "Pre User:" +blo "-7000,26200" +) +preUserText (MLText +uid 5,0 +va (VaSet +) +xt "-5000,26400,38900,36000" +st "constant stepsPerTurn : positive := 500 * 4; +constant mmPerTurn : real:= 1.75; +constant position0 : positive := integer(3.0 * real(stepsPerTurn) / mmPerTurn ); +constant position1 : positive := integer(8.0 * real(stepsPerTurn) / mmPerTurn ); +constant position2 : positive := integer(12.0 * real(stepsPerTurn) / mmPerTurn ); +constant slopeShiftBitNb : positive := 2; +constant pwmBitNb : positive := 8; +constant testLineNb : positive := 16;" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,10,1" +) +xt "-7000,25600,3200,26600" +st "Diagram Signals:" +blo "-7000,26400" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,10,1" +) +xt "-7000,25600,-400,26600" +st "Post User:" +blo "-7000,26400" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +) +xt "-5000,40000,-5000,40000" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +suid 16,0 +usingSuid 1 +emptyRow *102 (LEmptyRow +) +uid 3264,0 +optionalChildren [ +*103 (RefLabelRowHdr +) +*104 (TitleRowHdr +) +*105 (FilterRowHdr +) +*106 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*107 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*108 (GroupColHdr +tm "GroupColHdrMgr" +) +*109 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*110 (ModeColHdr +tm "BlockDiagramModeColHdrMgr" +) +*111 (TypeColHdr +tm "BlockDiagramTypeColHdrMgr" +) +*112 (BoundsColHdr +tm "BlockDiagramBoundsColHdrMgr" +) +*113 (InitColHdr +tm "BlockDiagramInitColHdrMgr" +) +*114 (EolColHdr +tm "BlockDiagramEolColHdrMgr" +) +*115 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "reset" +t "std_ulogic" +o 9 +suid 1,0 +) +) +uid 3233,0 +) +*116 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 2,0 +) +) +uid 3235,0 +) +*117 (LeafLogPort +port (LogicalPort +m 4 +decl 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0000000..ac3f457 --- /dev/null +++ b/Cursor_test/hds/cursor_tb/symbol.sb @@ -0,0 +1,1230 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2001,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 107,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 108,0 +optionalChildren [ +*14 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" 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"C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "interface" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester" +) +(vvPair +variable "d_logical" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester" +) +(vvPair +variable "date" +value "11.11.2019" +) +(vvPair +variable "day" +value "Mon" +) +(vvPair +variable "day_long" +value "Monday" +) +(vvPair +variable "dd" +value "11" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "cursor_tester" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "interface" +) +(vvPair +variable "f_logical" +value "interface" +) +(vvPair +variable "f_noext" +value "interface" +) +(vvPair +variable "graphical_source_author" +value "silvan.zahno" +) +(vvPair +variable "graphical_source_date" +value "11.11.2019" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE6996" +) +(vvPair +variable "graphical_source_time" +value "08:13:23" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE6996" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Cursor_test" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Cursor_test/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "cursor_tester" +) +(vvPair +variable "month" +value "Nov" +) +(vvPair +variable "month_long" +value "November" +) +(vvPair +variable "p" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester\\interface" +) +(vvPair +variable "p_logical" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester\\interface" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "/usr/opt/Modelsim/modeltech/bin" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "" +) +(vvPair +variable "this_file" +value "interface" +) +(vvPair +variable "this_file_logical" +value "interface" +) +(vvPair +variable "time" +value "08:13:23" +) +(vvPair +variable "unit" +value "cursor_tester" +) +(vvPair +variable "user" +value "silvan.zahno" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "interface" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 106,0 +optionalChildren [ +*81 (SymbolBody +uid 8,0 +optionalChildren [ +*82 (CptPort +uid 902,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 903,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "28625,5250,29375,6000" +) +tg (CPTG +uid 904,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f 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"Verdana,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,3600,1950" +st "Buffer0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Verdana,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *113 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,0,48500,900" +st "Declarations" +blo "42000,700" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,900,45000,1800" +st "Ports:" +blo "42000,1600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,13800,44500,14700" +st "User:" +blo "42000,14500" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "42000,0,49500,900" +st "Internal User:" +blo "42000,700" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Verdana,8,0" +) +xt "44000,14700,44000,14700" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 1006,0 +) diff --git a/Cursor_test/hds/cursor_tester/test.vhd b/Cursor_test/hds/cursor_tester/test.vhd new file mode 100644 index 0000000..f0beb44 --- /dev/null +++ b/Cursor_test/hds/cursor_tester/test.vhd @@ -0,0 +1,118 @@ +ARCHITECTURE test OF cursor_tester IS + + constant clockPeriod: time := 50 ns; + signal sClock: std_uLogic := '1'; + + constant pulsesPerTurn: integer := 200; + constant stepPeriodNb: positive := 8; + signal stepEn: std_uLogic := '0'; + signal direction: std_uLogic; + signal turning: std_uLogic; + signal stepCount: unsigned(10 downto 0) := (others => '0'); + +BEGIN + + ------------------------------------------------------------------------------ + -- clock and reset + -- + reset <= '1', '0' after clockPeriod/4; + + sClock <= not sClock after clockPeriod/2; + clock <= sClock after clockPeriod/10; + + + ------------------------------------------------------------------------------ + -- test sequence + -- + process + begin + + testMode <= '1'; + + restart <= '0'; + go1 <= '0'; + go2 <= '0'; + setPoint <= '0'; + + sensor1 <= '0'; + sensor2 <= '0'; + + wait for 1 us; + + ---------------------------------------------------------------------------- + -- advance to first stop point + go1 <= '1', '0' after 1 us; + wait for 4 ms; + + ---------------------------------------------------------------------------- + -- advance to second stop point + go2 <= '1', '0' after 1 us; + wait for 4 ms; + + ---------------------------------------------------------------------------- + -- back to start with sensor reset + restart <= '1', '0' after 1 us; + wait for 0.5 ms; + sensor1 <= '1', '0' after 1 us; + wait for 0.5 ms; + + ---------------------------------------------------------------------------- + -- advance to second stop point + go2 <= '1', '0' after 1 us; + wait for 7 ms; + + ---------------------------------------------------------------------------- + -- go back to first stop point + go1 <= '1', '0' after 1 us; + wait for 4 ms; + + ---------------------------------------------------------------------------- + -- back to start with counter stop + restart <= '1', '0' after 1 us; + wait for 4 ms; + sensor1 <= '1', '0' after 1 us; + wait for 1 ms; + + wait; + end process; + + ------------------------------------------------------------------------------ + -- motor feedback + -- + turning <= motorOn; + + findDirection: process(side1, side2) + begin + if (side1 = '1') and (side2 = '0') then + direction <= '1'; + elsif (side1 = '0') and (side2 = '1') then + direction <= '0'; + end if; + end process findDirection; + + stepEn <= not stepEn after (stepPeriodNb/4)*clockPeriod; + + count: process (stepEn) + begin + if turning = '1' then + if direction = '1' then + if stepCount < pulsesPerTurn-1 then + stepCount <= stepCount + 1; + else + stepCount <= to_unsigned(0, stepCount'length); + end if; + else + if stepCount > 0 then + stepCount <= stepCount - 1; + else + stepCount <= to_unsigned(pulsesPerTurn-1, stepCount'length); + end if; + end if; + end if; + end process count; + + encoderA <= stepCount(1); + encoderB <= not stepCount(1) xor stepCount(0); + encoderI <= '1' when stepCount = pulsesPerTurn-1 else '0'; + +END test; diff --git a/Cursor_test/hds/divider_tb/struct.bd b/Cursor_test/hds/divider_tb/struct.bd new file mode 100644 index 0000000..1346ab1 --- /dev/null +++ b/Cursor_test/hds/divider_tb/struct.bd @@ -0,0 +1,2770 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I1" +duLibraryName "Cursor_test" +duName "divider_tester" +elements [ +] +mwi 0 +uid 1774,0 +) +(Instance +name "I0" +duLibraryName "Cursor" +duName "divider" +elements [ +] +mwi 0 +uid 2524,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value 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clockPeriod: time := 50 ns; + signal sClock: std_uLogic := '1'; + +BEGIN + + reset <= '1', '0' after clockPeriod/4; + + sClock <= not sClock after clockPeriod/2; + clock <= sClock after clockPeriod/10; + + testMode <= '1', '0' after 10000*clockPeriod; + + start <= '0', + '1' after 210 us, + '0' after 210 us + clockPeriod, + '1' after 2.1 ms, + '0' after 2.1 ms + clockPeriod; + +END test; diff --git a/Cursor_test/hds/position@counter_tb/struct.bd b/Cursor_test/hds/position@counter_tb/struct.bd new file mode 100644 index 0000000..8e54756 --- /dev/null +++ b/Cursor_test/hds/position@counter_tb/struct.bd @@ -0,0 +1,3009 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I1" +duLibraryName "Cursor_test" +duName "positionCounter_tester" +elements [ +(GiElement +name "counterBitNb" +type "positive" +value "counterBitNb" +) +] +mwi 0 +uid 1774,0 +) +(Instance +name "I0" +duLibraryName "Cursor" +duName "positionCounter" +elements [ +(GiElement +name "counterBitNb" +type "positive" +value "counterBitNb" +) +] +mwi 0 +uid 2179,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\position@counter_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\position@counter_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\position@counter_tb" +) +(vvPair +variable "d_logical" +value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\positionCounter_tb" +) +(vvPair +variable "date" +value "11.11.2019" +) +(vvPair +variable "day" +value "Mon" +) +(vvPair +variable "day_long" +value "Monday" +) +(vvPair +variable "dd" +value "11" +) +(vvPair +variable "entity_name" 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sClock <= not sClock after clockPeriod/2; + clock <= sClock after clockPeriod/10; + + ------------------------------------------------------------------------------ + -- encoder signals + -- + direction <= '1', '0' after 2000*clockPeriod; + + stepEn <= not stepEn after (stepPeriodNb/4)*clockPeriod; + + count: process (stepEn) + begin + if direction = '1' then + if stepCount < pulsesPerTurn-1 then + stepCount <= stepCount + 1; + else + stepCount <= to_unsigned(0, stepCount'length); + end if; + else + if stepCount > 0 then + stepCount <= stepCount - 1; + else + stepCount <= to_unsigned(pulsesPerTurn-1, stepCount'length); + end if; + end if; + end process count; + + encoderA <= stepCount(1); + encoderB <= stepCount(1) xor stepCount(0); + encoderI <= '1' when stepCount = pulsesPerTurn-1 else '0'; + + ------------------------------------------------------------------------------ + -- control signals + -- + clear <= '0', + '1' after 100*clockPeriod, + '0' after 101*clockPeriod; + +END test; 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------------------------------------------------------------------------------ + -- clock and reset + -- + reset <= '1', '0' after clockPeriod/4; + + sClock <= not sClock after clockPeriod/2; + clock <= sClock after clockPeriod/10; + + ------------------------------------------------------------------------------ + -- control signals + -- + amplitude <= to_unsigned( 64, amplitude'length), + to_unsigned(128, amplitude'length) after 10*256*enPeriodNb*clockPeriod, + to_unsigned(192, amplitude'length) after 20*256*enPeriodNb*clockPeriod; + + sEn <= '1' after (enPeriodNb-1)*clockPeriod when sEn = '0' else '0' after clockPeriod; + en <= sEn; + +END test; diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..fdf8bfa --- /dev/null +++ b/LICENSE @@ -0,0 +1,11 @@ +All Rights Reserved + +Copyright (c) 2019 - HES-SO Valais Wallis + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. \ No newline at end of file diff --git a/Libs/Common/hdl/blinker_arch.vhd b/Libs/Common/hdl/blinker_arch.vhd new file mode 100644 index 0000000..3d29f7e --- /dev/null +++ b/Libs/Common/hdl/blinker_arch.vhd @@ -0,0 +1,89 @@ +-- filename: blinker.vhd +-- kind: vhdl file +-- first created: 18.06.2012 +-- created by: zas +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : zas 18.06.2012 -- Initial Version +-------------------------------------------------------------------------------- +-- Description: +-- For let blinking a LED with an signal event +-- Mode = 0 (reactive on rising edge) +-- ___________________________________________ +-- input ____/ +-- ___________________ +-- output ____/ \_______________________ +-- time 0s 0.5s 1s +-- +-- _ +-- input ____/ \_________________________________________ +-- ___________________ +-- output ____/ \_______________________ +-- time 0s 0.5s 1s +---- +-- Mode = 1 (reactive on falling edge) +-- _____ +-- input \__________________________________________ +-- ___________________ +-- output ______/ \_____________________ +-- time 0s 0.5s 1s +-- +-- _ +-- input ____/ \_________________________________________ +-- ___________________ +-- output ______ / \____________________ +-- time 0s 0.5s 1s +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.NUMERIC_STD.all; + +LIBRARY Common; +USE Common.CommonLib.all; + + +ARCHITECTURE arch OF blinker IS + + constant c : integer := clockFrequency/2; -- 500ms blink + + signal cnt : unsigned(requiredBitNb(c)-1 downto 0); + signal en_delay : std_ulogic; + signal blink_int : std_ulogic; + +BEGIN + + process(reset, clock) + begin + if reset = '1' then + en_delay <= '0'; + blink_int <= '0'; + cnt <= (others => '0'); + elsif rising_edge(clock) then + en_delay <= en; + -- detect rising_edge + if mode = 0 then + if blink_int = '0' and en_delay = '0' and en = '1' then + blink_int <= '1'; + end if; + else + -- detect falling edge + if blink_int = '0' and en_delay = '1' and en = '0' then + blink_int <= '1'; + end if; + end if; + -- blink + if blink_int = '1' then + if (cnt < c) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + blink_int <= '0'; + end if; + end if; + end if; + end process; + + -- Set output + blink <= blink_int; +END ARCHITECTURE arch; diff --git a/Libs/Common/hdl/commonLib.vhd b/Libs/Common/hdl/commonLib.vhd new file mode 100644 index 0000000..f56b0e9 --- /dev/null +++ b/Libs/Common/hdl/commonLib.vhd @@ -0,0 +1,68 @@ +-------------------------------------------------------------------------------- +-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch) +-------------------------------------------------------------------------------- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-- ----------------------------------------------------------------------------- +-- Common Lib +-- +-- ----------------------------------------------------------------------------- +-- Authors: +-- cof: [Franois Corthay](francois.corthay@hevs.ch) +-- guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +-- ----------------------------------------------------------------------------- +-- Changelog: +-- 2016-06 : guo +-- added function sel +-- 2015-06 : guo +-- added counterBitNb +-- added documentation +-- ----------------------------------------------------------------------------- +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + +PACKAGE CommonLib IS + + ------------------------------------------------------------------------------ + -- Returns the number of bits needed to represent the given val + -- Examples: + -- requiredBitNb(1) = 1 (1) + -- requiredBitNb(2) = 2 (10) + -- requiredBitNb(3) = 2 (11) + function requiredBitNb(val : integer) return integer; + + ------------------------------------------------------------------------------ + -- Returns the number of bits needed to count val times (0 to val-1) + -- Examples: + -- counterBitNb(1) = 1 (0) + -- counterBitNb(2) = 1 (0->1) + -- counterBitNb(3) = 2 (0->1->10) + function counterBitNb(val : integer) return integer; + + ------------------------------------------------------------------------------ + -- Functions to return one or the other input based on a boolean. + -- Can be used to build conditional constants. + -- Example: + -- constant bonjour_c : string := sel(ptpRole = master, "fpga20", "fpga02"); + function sel(Cond : BOOLEAN; If_True, If_False : integer) + return integer; + function sel(Cond : BOOLEAN; If_True, If_False : string) + return string; + function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector) + return std_ulogic_vector; + function sel(Cond : BOOLEAN; If_True, If_False : unsigned) + return unsigned; + function sel(Cond : BOOLEAN; If_True, If_False : signed) + return signed; + +END CommonLib; diff --git a/Libs/Common/hdl/commonLib_body.vhd b/Libs/Common/hdl/commonLib_body.vhd new file mode 100644 index 0000000..34bda09 --- /dev/null +++ b/Libs/Common/hdl/commonLib_body.vhd @@ -0,0 +1,105 @@ +-------------------------------------------------------------------------------- +-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch) +-------------------------------------------------------------------------------- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-- ----------------------------------------------------------------------------- +-- Often used functions +-- +-- ----------------------------------------------------------------------------- +-- Authors: +-- cof: [Franois Corthay](francois.corthay@hevs.ch) +-- guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +-- ----------------------------------------------------------------------------- +-- Changelog: +-- 2016-06 : guo +-- added function sel +-- 2015-06 : guo +-- added counterBitNb +-- ----------------------------------------------------------------------------- +PACKAGE BODY CommonLib IS + + function requiredBitNb (val : integer) return integer is + variable powerOfTwo, bitNb : integer; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo <= val loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end requiredBitNb; + + function counterBitNb (val : integer) return integer is + variable powerOfTwo, bitNb : integer; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo < val loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end counterBitNb; + + function sel(Cond : BOOLEAN; If_True, If_False : integer) + return integer is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : string) + return string is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector) + return std_ulogic_vector is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : unsigned) + return unsigned is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : signed) + return signed is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + +END CommonLib; diff --git a/Libs/Common/hdl/debouncerULogicVector_RTL.vhd b/Libs/Common/hdl/debouncerULogicVector_RTL.vhd new file mode 100644 index 0000000..734485e --- /dev/null +++ b/Libs/Common/hdl/debouncerULogicVector_RTL.vhd @@ -0,0 +1,97 @@ +-- filename: debouncer.vhd +-- kind: vhdl file +-- first created: 05.03.2012 +-- created by: zas +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : zas 05.03.2012 -- Initial Version +-- v0.2 : cof 22.01.2013 -- synchronization to clock +-------------------------------------------------------------------------------- +-- Description: +-- Debounces a button on both edges. +-- _ _ ____________________ _ _ +-- input ____/ \_/ \_/ \_/ \_/ \______ +-- _____________________________ +-- output _____/ \____________ +-- +-------------------------------------------------------------------------------- + +ARCHITECTURE rtl OF debouncerULogicVector IS + + signal inputNormal : std_ulogic_vector(input'range); + signal inputSynch, inputDelayed, inputChanged : std_ulogic; + signal debounceCounter : unsigned(counterBitNb-1 downto 0); + +BEGIN + ------------------------------------------------------------------------------ + -- adapt polarity + adaptPolarity: process(input) + begin + for index in input'range loop + inputNormal(index) <= input(index) xor invertInput; + end loop; + end process adaptPolarity; + + ------------------------------------------------------------------------------ + -- Synchronize input to clock + synchInput: process(reset, clock) + variable inputOr : std_ulogic; + begin + if reset = '1' then + inputSynch <= '0'; + elsif rising_edge(clock) then + inputOr := '0'; + for index in input'range loop + inputOr := inputOr or inputNormal(index); + end loop; + inputSynch <= inputOr; + end if; + end process synchInput; + + ------------------------------------------------------------------------------ + -- Find edge on input + delayInput: process(reset, clock) + begin + if reset = '1' then + inputDelayed <= '0'; + elsif rising_edge(clock) then + inputDelayed <= inputSynch; + end if; + end process delayInput; + + inputChanged <= '1' when inputDelayed /= inputSynch + else '0'; + + ------------------------------------------------------------------------------ + -- Debounce counter + countDeadTime: process(reset, clock) + begin + if reset = '1' then + debounceCounter <= (others => '0'); + elsif rising_edge(clock) then + if debounceCounter = 0 then + if inputChanged = '1' then + debounceCounter <= debounceCounter - 1; + end if; + else + debounceCounter <= debounceCounter - 1; + end if; + end if; + end process countDeadTime; + + ------------------------------------------------------------------------------ + -- Update output + updateOutput: process(reset, clock) + begin + if reset = '1' then + debounced <= (others => '0'); + elsif rising_edge(clock) then + if (inputChanged = '1') and (debounceCounter = 0) then + debounced <= inputNormal; + elsif debounceCounter = 1 then + debounced <= inputNormal; + end if; + end if; + end process updateOutput; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hdl/debouncer_RTL.vhd b/Libs/Common/hdl/debouncer_RTL.vhd new file mode 100644 index 0000000..a74c383 --- /dev/null +++ b/Libs/Common/hdl/debouncer_RTL.vhd @@ -0,0 +1,83 @@ +-- filename: debouncer.vhd +-- kind: vhdl file +-- first created: 05.03.2012 +-- created by: zas +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : zas 05.03.2012 -- Initial Version +-- v0.2 : cof 22.01.2013 -- synchronization to clock +-- -- direct reaction on both edges +-------------------------------------------------------------------------------- +-- Description: +-- Debounces a button on both edges. +-- _ _ ____________________ _ _ +-- input ____/ \_/ \_/ \_/ \_/ \______ +-- _____________________________ +-- output _____/ \____________ +-- +-------------------------------------------------------------------------------- + +ARCHITECTURE rtl OF debouncer IS + + signal debounceCounter : unsigned(counterBitNb-1 downto 0); + signal inputSynch, inputDelayed, inputChanged : std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- Synchronize input to clock + synchInput: process(reset, clock) + begin + if reset = '1' then + inputSynch <= '0'; + elsif rising_edge(clock) then + inputSynch <= input xor invertInput; + end if; + end process synchInput; + + ------------------------------------------------------------------------------ + -- Find edge on input + delayInput: process(reset, clock) + begin + if reset = '1' then + inputDelayed <= '0'; + elsif rising_edge(clock) then + inputDelayed <= inputSynch; + end if; + end process delayInput; + + inputChanged <= '1' when inputDelayed /= inputSynch + else '0'; + + ------------------------------------------------------------------------------ + -- Debounce counter + countDeadTime: process(reset, clock) + begin + if reset = '1' then + debounceCounter <= (others => '0'); + elsif rising_edge(clock) then + if debounceCounter = 0 then + if inputChanged = '1' then + debounceCounter <= debounceCounter - 1; + end if; + else + debounceCounter <= debounceCounter - 1; + end if; + end if; + end process countDeadTime; + + ------------------------------------------------------------------------------ + -- Update output + updateOutput: process(reset, clock) + begin + if reset = '1' then + debounced <= '0'; + elsif rising_edge(clock) then + if (inputChanged = '1') and (debounceCounter = 0) then + debounced <= input; + elsif debounceCounter = 1 then + debounced <= input; + end if; + end if; + end process updateOutput; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hdl/edgeDetector_rtl.vhd b/Libs/Common/hdl/edgeDetector_rtl.vhd new file mode 100644 index 0000000..a9ae99a --- /dev/null +++ b/Libs/Common/hdl/edgeDetector_rtl.vhd @@ -0,0 +1,48 @@ +-------------------------------------------------------------------------------- +-- Copyright 2014 HES-SO Valais Wallis (www.hevs.ch) +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-------------------------------------------------------------------------------- +-- EdgeDetector +-- Detect rising and falling edges of a signal. +-- +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : guo 2014-04-02 -- Initial version +-- v1.0 : cof 2019-10-02 -- Updated symbol +-------------------------------------------------------------------------------- +ARCHITECTURE RTL OF edgeDetector IS + + SIGNAL pulse_delayed : std_ulogic; + SIGNAL rising_detected_s : std_ulogic; + SIGNAL falling_detected_s : std_ulogic; + +BEGIN + + -- delay pulse + reg : PROCESS (reset, clock) + BEGIN + IF reset = '1' THEN + pulse_delayed <= '0'; + ELSIF rising_edge(clock) THEN + pulse_delayed <= pulse; + END IF; + END PROCESS reg ; + + -- edge detection + rising <= '1' when (pulse = '1') and (pulse_delayed = '0') + else '0'; + falling <= '1' when (pulse = '0') and (pulse_delayed = '1') + else '0'; + +END ARCHITECTURE RTL; diff --git a/Libs/Common/hdl/rotaryToUnsigned_rtl.vhd b/Libs/Common/hdl/rotaryToUnsigned_rtl.vhd new file mode 100644 index 0000000..8f1a378 --- /dev/null +++ b/Libs/Common/hdl/rotaryToUnsigned_rtl.vhd @@ -0,0 +1,76 @@ +ARCHITECTURE rtl OF rotaryToUnsigned IS + + signal rotaryDelayed1, rotaryDelayed2, rotaryStable : unsigned(rotary'range); + signal rotary_changed : std_ulogic; + signal glitchDelayCounter : unsigned(counterBitNb-1 downto 0); + signal rotaryStableDelayed : unsigned(rotary'range); + signal numberMsbs : unsigned(number'length-rotary'length-1 downto 0); + +BEGIN + ------------------------------------------------------------------------------ + -- synchronize input and detect changes + delayRotary: process(reset, clock) + begin + if reset = '1' then + rotaryDelayed1 <= (others => '0'); + rotaryDelayed2 <= (others => '0'); + elsif rising_edge(clock) then + rotaryDelayed1 <= rotary; + rotaryDelayed2 <= rotaryDelayed1; + end if; + end process delayRotary; + + rotary_changed <= '1' when rotaryDelayed1 /= rotaryDelayed2 + else '0'; + -- count dead time + countDeadTime: process(reset, clock) + begin + if reset = '1' then + glitchDelayCounter <= (others => '1'); + elsif rising_edge(clock) then + if rotary_changed = '1' then + glitchDelayCounter <= (others => '1'); + elsif glitchDelayCounter > 0 then + glitchDelayCounter <= glitchDelayCounter - 1; + end if; + end if; + end process countDeadTime; + -- store new rotary button value + storeRotary: process(reset, clock) + begin + if reset = '1' then + rotaryStable <= (others => '0'); + elsif rising_edge(clock) then + if glitchDelayCounter = 0 then + rotaryStable <= rotaryDelayed2; + end if; + end if; + end process storeRotary; + + ------------------------------------------------------------------------------ + -- keep previous value of stablilzed rotary + delayRotaryStable: process(reset, clock) + begin + if reset = '1' then + rotaryStableDelayed <= (others => '0'); + elsif rising_edge(clock) then + rotaryStableDelayed <= rotaryStable; + end if; + end process delayRotaryStable; + -- synchronize input and detect changes + updateMsbs: process(reset, clock) + begin + if reset = '1' then + numberMsbs <= (others => '0'); + elsif rising_edge(clock) then + if (rotaryStable = 0) and (rotaryStableDelayed+1 = 0) then + numberMsbs <= numberMsbs + 1; + elsif (rotaryStable+1 = 0) and (rotaryStableDelayed = 0) then + numberMsbs <= numberMsbs - 1; + end if; + end if; + end process updateMsbs; + + number <= numberMsbs & rotaryStableDelayed; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hdl/spikeFilter_RTL.vhd b/Libs/Common/hdl/spikeFilter_RTL.vhd new file mode 100644 index 0000000..b176aa8 --- /dev/null +++ b/Libs/Common/hdl/spikeFilter_RTL.vhd @@ -0,0 +1,82 @@ +-------------------------------------------------------------------------------- +-- Description: +-- Filters short time spikes. +-- _ _ ____________________ _ _ +-- input ____/ \_/ \_/ \_/ \_/ \_________________ +-- _____________________________ +-- output ________________/ \____________ +-- +-------------------------------------------------------------------------------- + +ARCHITECTURE rtl OF spikeFilter IS + + signal filterCounter : unsigned(counterBitNb-1 downto 0); + signal inputSynch, inputDelayed, inputChanged : std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- Synchronize input to clock + synchInput: process(reset, clock) + begin + if reset = '1' then + inputSynch <= '0'; + elsif rising_edge(clock) then + inputSynch <= input xor invertInput; + end if; + end process synchInput; + + ------------------------------------------------------------------------------ + -- Find edge on input + delayInput: process(reset, clock) + begin + if reset = '1' then + inputDelayed <= '0'; + elsif rising_edge(clock) then + inputDelayed <= inputSynch; + end if; + end process delayInput; + + inputChanged <= '1' when inputDelayed /= inputSynch + else '0'; + + ------------------------------------------------------------------------------ + -- Debounce counter + countDeadTime: process(reset, clock) + begin + if reset = '1' then + filterCounter <= (others => '0'); + elsif rising_edge(clock) then + if filterCounter = 0 then + if inputChanged = '1' then + filterCounter <= filterCounter + 1; + end if; + elsif signed(filterCounter)+1 = 0 then + if inputChanged = '1' then + filterCounter <= filterCounter - 1; + end if; + else + if inputSynch = '0' then + filterCounter <= filterCounter - 1; + else + filterCounter <= filterCounter + 1; + end if; + end if; + end if; + end process countDeadTime; + + ------------------------------------------------------------------------------ + -- Update output + updateOutput: process(reset, clock) + begin + if reset = '1' then + filtered <= '0'; + elsif rising_edge(clock) then + if filterCounter = 0 then + filtered <= '0'; + elsif signed(filterCounter)+1 = 0 then + filtered <= '1'; + end if; + end if; + end process updateOutput; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hdl/toggler_RTL.vhd b/Libs/Common/hdl/toggler_RTL.vhd new file mode 100644 index 0000000..1b47128 --- /dev/null +++ b/Libs/Common/hdl/toggler_RTL.vhd @@ -0,0 +1,90 @@ +-- filename: toggler.vhd +-- kind: vhdl file +-- first created: 05.03.2012 +-- created by: zas +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : cof 22.01.2013 -- Initial version +-------------------------------------------------------------------------------- +-- Description: +-- Debounces a button on both edges. +-- _ _ +-- input ____/ \__________________________/ \____________ +-- _____________________________ +-- output _____/ \____________ +-- +-- If the generic "counterBitNb" is greater than zero, a debouncer is placed on +-- the input signal. +-- +-------------------------------------------------------------------------------- + +ARCHITECTURE rtl OF toggler IS + + signal inputDebounced : std_ulogic; + signal inputDelayed, inputChangedTo1 : std_ulogic; + signal toggle_int : std_ulogic; + + COMPONENT debouncer + GENERIC ( + counterBitNb : positive := 18; + invertInput : std_ulogic := '0' + ); + PORT ( + reset : IN std_ulogic ; + clock : IN std_ulogic ; + input : IN std_ulogic ; + debounced : OUT std_ulogic + ); + END COMPONENT; + +BEGIN + ------------------------------------------------------------------------------ + -- Debounce input + useInputDirectly: if counterBitNb = 0 generate + inputDebounced <= input; + end generate useInputDirectly; + + debounceInput: if counterBitNb > 0 generate + I_debouncer : debouncer + GENERIC MAP ( + counterBitNb => counterBitNb, + invertInput => invertInput + ) + PORT MAP ( + reset => reset, + clock => clock, + input => input, + debounced => inputDebounced + ); + end generate debounceInput; + + ------------------------------------------------------------------------------ + -- Find edge on input + delayInput: process(reset, clock) + begin + if reset = '1' then + inputDelayed <= '0'; + elsif rising_edge(clock) then + inputDelayed <= inputDebounced; + end if; + end process delayInput; + + inputChangedTo1 <= '1' when (inputDebounced = '1') and (inputDelayed = '0') + else '0'; + + ------------------------------------------------------------------------------ + -- Toggle output + toggleOutput: process(reset, clock) + begin + if reset = '1' then + toggle_int <= '0'; + elsif rising_edge(clock) then + if inputChangedTo1 = '1' then + toggle_int <= not toggle_int; + end if; + end if; + end process toggleOutput; + + toggle <= toggle_int; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hds/.hdlsidedata/_blinker_arch.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_blinker_arch.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_blinker_arch.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_blinker_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_blinker_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_blinker_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_commonLib.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_commonLib.vhd._fpf new file mode 100644 index 0000000..2acce3d --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_commonLib.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_87 diff --git a/Libs/Common/hds/.hdlsidedata/_commonLib_body.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_commonLib_body.vhd._fpf new file mode 100644 index 0000000..2acce3d --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_commonLib_body.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_87 diff --git a/Libs/Common/hds/.hdlsidedata/_debounce_rtl.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_debounce_rtl.vhd._fpf new file mode 100644 index 0000000..19d6635 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debounce_rtl.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2002 diff --git a/Libs/Common/hds/.hdlsidedata/_debouncerULogicVector_RTL.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_debouncerULogicVector_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncerULogicVector_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_debouncer_RTL.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_debouncer_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncer_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_debouncer_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_debouncer_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncer_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_edgeDetector_rtl.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_edgeDetector_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_edgeDetector_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_edgedetector_entity.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_edgedetector_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_edgedetector_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_rotaryToUnsigned_rtl.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_rotaryToUnsigned_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_rotaryToUnsigned_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_rotarytounsigned_entity.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_rotarytounsigned_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_rotarytounsigned_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_spikeFilter_RTL.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_spikeFilter_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_spikeFilter_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_toggler_RTL.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_toggler_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_toggler_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_toggler_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_toggler_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_toggler_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/_blinker._epf b/Libs/Common/hds/_blinker._epf new file mode 100644 index 0000000..87ea3e1 --- /dev/null +++ b/Libs/Common/hds/_blinker._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom arch +DEFAULT_FILE atom blinker_arch.vhd diff --git a/Libs/Common/hds/_debounce._epf b/Libs/Common/hds/_debounce._epf new file mode 100644 index 0000000..ec8784d --- /dev/null +++ b/Libs/Common/hds/_debounce._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom rtl +DEFAULT_FILE atom debounce_rtl.vhd diff --git a/Libs/Common/hds/_debouncer._epf b/Libs/Common/hds/_debouncer._epf new file mode 100644 index 0000000..641b0cc --- /dev/null +++ b/Libs/Common/hds/_debouncer._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom debouncer_RTL.vhd +DEFAULT_ARCHITECTURE atom rtl diff --git a/Libs/Common/hds/_edgedetector._epf b/Libs/Common/hds/_edgedetector._epf new file mode 100755 index 0000000..218e0ce --- /dev/null +++ b/Libs/Common/hds/_edgedetector._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom edgeDetector_rtl.vhd diff --git a/Libs/Common/hds/_rotarytounsigned._epf b/Libs/Common/hds/_rotarytounsigned._epf new file mode 100755 index 0000000..7c92a28 --- /dev/null +++ b/Libs/Common/hds/_rotarytounsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom rotaryToUnsigned_rtl.vhd +DEFAULT_ARCHITECTURE atom rtl diff --git a/Libs/Common/hds/_toggler._epf b/Libs/Common/hds/_toggler._epf new file mode 100644 index 0000000..ee14298 --- /dev/null +++ b/Libs/Common/hds/_toggler._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom toggler_RTL.vhd +DEFAULT_ARCHITECTURE atom rtl diff --git a/Libs/Common/hds/blinker/symbol.sb b/Libs/Common/hds/blinker/symbol.sb new file mode 100644 index 0000000..887db7c --- /dev/null +++ b/Libs/Common/hds/blinker/symbol.sb @@ -0,0 +1,1557 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "NUMERIC_STD" +) +(DmPackageRef +library "Common" +unitName "CommonLib" +) +] +libraryRefs [ +"ieee" +"Common" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 5,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) 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+litem &13 +pos 7 +dimension 80 +uid 80,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 67,0 +vaOverrides [ +] +) +] +) +uid 52,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *35 (LEmptyRow +) +uid 82,0 +optionalChildren [ +*36 (RefLabelRowHdr +) +*37 (TitleRowHdr +) +*38 (FilterRowHdr +) +*39 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*40 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*41 (GroupColHdr +tm "GroupColHdrMgr" +) +*42 (NameColHdr +tm "GenericNameColHdrMgr" +) +*43 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*44 (InitColHdr +tm "GenericValueColHdrMgr" +) +*45 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*46 (EolColHdr +tm "GenericEolColHdrMgr" +) +*47 (LogGeneric +generic (GiElement +name "clockFrequency" +type "positive" +value "106e6" +e "in Hz" +) +uid 131,0 +) +*48 (LogGeneric +generic (GiElement +name "mode" +type "integer" +value "0" +) +uid 165,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 94,0 +optionalChildren [ +*49 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *50 (MRCItem +litem &35 +pos 2 +dimension 20 +) +uid 96,0 +optionalChildren [ +*51 (MRCItem +litem &36 +pos 0 +dimension 20 +uid 97,0 +) +*52 (MRCItem +litem &37 +pos 1 +dimension 23 +uid 98,0 +) +*53 (MRCItem +litem &38 +pos 2 +hidden 1 +dimension 20 +uid 99,0 +) +*54 (MRCItem +litem &47 +pos 0 +dimension 20 +uid 132,0 +) +*55 (MRCItem +litem &48 +pos 1 +dimension 20 +uid 166,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +textAngle 90 +) +uid 100,0 +optionalChildren [ +*56 (MRCItem +litem &39 +pos 0 +dimension 20 +uid 101,0 +) +*57 (MRCItem +litem &41 +pos 1 +dimension 50 +uid 102,0 +) +*58 (MRCItem +litem &42 +pos 2 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"/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "blinker" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/28/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "13:43:32" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Common" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libs/Common/work" +) +(vvPair +variable "mm" +value "08" +) +(vvPair +variable "module_name" +value "blinker" +) +(vvPair +variable "month" +value "Aug" +) +(vvPair +variable "month_long" +value "August" +) +(vvPair +variable "p" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker/symbol.sb" +) +(vvPair +variable "p_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker/symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "13:43:32" +) +(vvPair +variable "unit" +value "blinker" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2018.1 (Build 12)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 51,0 +optionalChildren [ +*63 (SymbolBody +uid 8,0 +optionalChildren [ +*64 (CptPort +uid 116,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 117,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,9625,15000,10375" +) +tg (CPTG +uid 118,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 119,0 +va (VaSet +) +xt "16000,9500,18100,10500" +st "clock" +blo "16000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 120,0 +va (VaSet +font "courier,8,0" +) +xt "44000,2000,58500,2900" +st "clock : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 1,0 +) +) +) +*65 (CptPort +uid 121,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 122,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,7625,15000,8375" +) +tg (CPTG +uid 123,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 124,0 +va (VaSet +) +xt "16000,7500,17200,8500" +st "en" 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+xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *84 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,7800,5400,8800" +st "Declarations" +blo "0,8600" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,8800,2700,9800" +st "Ports:" +blo "0,9600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,13400,2500,14300" +st "User:" +blo "0,14100" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,7800,5800,8800" +st "Internal User:" +blo "0,8600" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,14300,2000,14300" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,7800,0,7800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 302,0 +activeModelName "Symbol" +) diff --git a/Libs/Common_test/hdl/clockGenerator_sim.vhd b/Libs/Common_test/hdl/clockGenerator_sim.vhd new file mode 100644 index 0000000..b2e94be --- /dev/null +++ b/Libs/Common_test/hdl/clockGenerator_sim.vhd @@ -0,0 +1,13 @@ +ARCHITECTURE sim OF clockGenerator IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + +BEGIN + + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9.0/10.0; + +END ARCHITECTURE sim; diff --git a/Libs/Common_test/hdl/commonLib_tb_test.vhd b/Libs/Common_test/hdl/commonLib_tb_test.vhd new file mode 100644 index 0000000..40a1b77 --- /dev/null +++ b/Libs/Common_test/hdl/commonLib_tb_test.vhd @@ -0,0 +1,26 @@ +LIBRARY Common; + USE Common.commonLib.all; +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF commonLib_tb IS + constant maxPowOf2: positive := 10; + constant indent: string(1 to 2) := (others => ' '); +BEGIN + + process + variable value, bitNb: positive; + BEGIN + print("testing function " & '"' & "requiredBitNb" & '"'); + for index in 1 to maxPowOf2 loop + for offset in -1 to 1 loop + value := 2**index + offset; + bitNb := requiredBitNb(value); + print(indent & "requiredBitNb(" & sprintf("%d", value) & ") = " & sprintf("%d", bitNb)); + end loop; + print(""); + end loop; + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/debouncerULogicVector_tester_RTL.vhd b/Libs/Common_test/hdl/debouncerULogicVector_tester_RTL.vhd new file mode 100644 index 0000000..bca8093 --- /dev/null +++ b/Libs/Common_test/hdl/debouncerULogicVector_tester_RTL.vhd @@ -0,0 +1,57 @@ +ARCHITECTURE RTL OF debouncerULogicVector_tester IS + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + + constant longDelay : time := 2**(counterBitNb+1) * clockPeriod; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + process + begin + input <= (others => '0'); + wait for longDelay; + -- transition 0 to 1 + input(1) <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod, + '1' after 10*clockPeriod; + wait for longDelay; + -- transition to other bit + -- transition 1 to 0 + input(1) <= '0'; + wait for longDelay; + input(2) <= '1'; + wait for longDelay; + -- transition 1 to 0 + input(2) <= '0', + '1' after 1*clockPeriod, + '0' after 3*clockPeriod, + '1' after 5*clockPeriod, + '0' after 6*clockPeriod, + '1' after 8*clockPeriod, + '0' after 10*clockPeriod; + wait for longDelay; + -- short 1 pulse + input(3) <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod; + -- end of simulation + wait; + end process; + +END ARCHITECTURE RTL; diff --git a/Libs/Common_test/hdl/debouncer_tester_test.vhd b/Libs/Common_test/hdl/debouncer_tester_test.vhd new file mode 100644 index 0000000..b319ae6 --- /dev/null +++ b/Libs/Common_test/hdl/debouncer_tester_test.vhd @@ -0,0 +1,49 @@ +ARCHITECTURE test OF debouncer_tester IS + + constant clockFrequency : real := 66.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + process + begin + input <= '0'; + wait for 10*clockPeriod; + -- transition 0 to 1 + input <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod, + '1' after 10*clockPeriod; + wait for 50*clockPeriod; + -- transition 1 to 0 + input <= '0', + '1' after 1*clockPeriod, + '0' after 3*clockPeriod, + '1' after 5*clockPeriod, + '0' after 6*clockPeriod, + '1' after 8*clockPeriod, + '0' after 10*clockPeriod; + wait for 50*clockPeriod; + -- short 1 pulse + input <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod; + -- end of simulation + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/requiredBitNb.txt b/Libs/Common_test/hdl/requiredBitNb.txt new file mode 100644 index 0000000..5015db3 --- /dev/null +++ b/Libs/Common_test/hdl/requiredBitNb.txt @@ -0,0 +1,40 @@ +# testing function "requiredBitNb" +# requiredBitNb(1) = 1 +# requiredBitNb(2) = 2 +# requiredBitNb(3) = 2 +# +# requiredBitNb(3) = 2 +# requiredBitNb(4) = 3 +# requiredBitNb(5) = 3 +# +# requiredBitNb(7) = 3 +# requiredBitNb(8) = 4 +# requiredBitNb(9) = 4 +# +# requiredBitNb(15) = 4 +# requiredBitNb(16) = 5 +# requiredBitNb(17) = 5 +# +# requiredBitNb(31) = 5 +# requiredBitNb(32) = 6 +# requiredBitNb(33) = 6 +# +# requiredBitNb(63) = 6 +# requiredBitNb(64) = 7 +# requiredBitNb(65) = 7 +# +# requiredBitNb(127) = 7 +# requiredBitNb(128) = 8 +# requiredBitNb(129) = 8 +# +# requiredBitNb(255) = 8 +# requiredBitNb(256) = 9 +# requiredBitNb(257) = 9 +# +# requiredBitNb(511) = 9 +# requiredBitNb(512) = 10 +# requiredBitNb(513) = 10 +# +# requiredBitNb(1023) = 10 +# requiredBitNb(1024) = 11 +# requiredBitNb(1025) = 11 \ No newline at end of file diff --git a/Libs/Common_test/hdl/rotaryToUnsigned_tester_test.vhd b/Libs/Common_test/hdl/rotaryToUnsigned_tester_test.vhd new file mode 100644 index 0000000..70a3fbf --- /dev/null +++ b/Libs/Common_test/hdl/rotaryToUnsigned_tester_test.vhd @@ -0,0 +1,47 @@ +ARCHITECTURE test OF rotaryToUnsigned_tester IS + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + + constant stepPeriod : time := 100*clockPeriod; + signal rotary_int : unsigned(rotary'range); + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + turnRotary: process + begin + rotary_int <= (others => '0'); + wait for 10*stepPeriod; + -- count over max value + for index in 1 to 2**outputBitNb+2 loop + rotary_int <= rotary_int + 1; + wait for stepPeriod; + end loop; + -- count down again + for index in 1 to 2**outputBitNb+2 loop + rotary_int <= rotary_int - 1; + wait for stepPeriod; + end loop; + -- end of simulation + wait; + end process turnRotary; + + addGlitches: process + begin + wait on rotary_int; + rotary <= (others => '0'); + wait for clockPeriod; + rotary <= (others => '1'); + wait for clockPeriod; + rotary <= rotary_int; + end process addGlitches; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/spikeFilter_tester_test.vhd b/Libs/Common_test/hdl/spikeFilter_tester_test.vhd new file mode 100644 index 0000000..cd5468f --- /dev/null +++ b/Libs/Common_test/hdl/spikeFilter_tester_test.vhd @@ -0,0 +1,47 @@ +ARCHITECTURE test OF spikeFilter_tester IS + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + process + begin + input <= '0'; + wait for 10*clockPeriod; + -- loop on pulse width + for pulseWidth in 1 to 10 loop + -- send positive pulses train + for index in 1 to 8 loop + input <= '1'; + wait for pulseWidth * clockPeriod; + input <= '0'; + wait for pulseWidth * clockPeriod; + end loop; + -- set input high + input <= '1'; + wait for 100*clockPeriod; + -- send negative pulses train + for index in 1 to 8 loop + input <= '0'; + wait for pulseWidth * clockPeriod; + input <= '1'; + wait for pulseWidth * clockPeriod; + end loop; + -- set input low + input <= '0'; + wait for 100*clockPeriod; + end loop; + -- end of simulation + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/testUtils_pkg.vhd b/Libs/Common_test/hdl/testUtils_pkg.vhd new file mode 100644 index 0000000..4d275b9 --- /dev/null +++ b/Libs/Common_test/hdl/testUtils_pkg.vhd @@ -0,0 +1,127 @@ +LIBRARY std; + USE std.textio.all; +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +PACKAGE testUtils IS + + --============================================================================ + -- console output + -- + + procedure print(value : string); + + + --============================================================================ + -- string manipulation + -- + + -- conversion to lowercase + function lc(value : string) return string; + procedure lc(value : inout line); + -- conversion to uppercase + function uc(value : string) return string; + procedure uc(value : inout line); + -- expand a string to a given length + function pad( + value : string; + string_length : natural; + fill_char : character := ' '; + right_justify : boolean := false + ) return string; + -- remove separator characters at beginning and end of line + procedure rm_side_separators( + value : inout line; + separators : in string + ); + procedure rm_side_separators( + value : inout line + ); + -- remove multiple occurences of separator characters + procedure trim_line( + value : inout line; + separators : in string + ); + + procedure trim_line( + value : inout line + ); + -- remove all occurences of separator characters + procedure rm_all_separators( + value : inout line; + separators : in string + ); + + procedure rm_all_separators( + value : inout line + ); + -- find and remove first word + procedure read_first( + value : inout line; + separators : in string; + first : out line + ); + + procedure read_first( + value : inout line; + first : out line + ); + -- find and remove last word + procedure read_last( + value : inout line; + separators : in string; + last : out line + ); + + procedure read_last( + value : inout line; + last : out line + ); + + + --============================================================================ + -- formatted string output + -- + -- format codes: + -- code integer real std_logic std_(u)logic_vector (un)signed time + -- b v v v v binary + -- c character + -- d v v v v v decimal + -- e real numbers, with power of 10 exponent + -- f v v fixed point real numbers + -- s string + -- ts v time in seconds + -- tm v time in milliseconds + -- tu v time in microseconds + -- tn v time in nanoseconds + -- tp v time in picoseconds + -- x v v v v hexadecimal + -- X v v v v hexadecimal with upper-case letters + + function sprintf(format : string; value : integer ) return string; + function sprintf(format : string; value : real ) return string; + function sprintf(format : string; value : std_logic ) return string; + function sprintf(format : string; value : std_ulogic_vector) return string; + function sprintf(format : string; value : std_logic_vector ) return string; + function sprintf(format : string; value : unsigned ) return string; + function sprintf(format : string; value : signed ) return string; + function sprintf(format : string; value : time ) return string; + + --============================================================================ + -- formatted string input + -- + subtype nibbleUlogicType is std_ulogic_vector(3 downto 0); + subtype nibbleUnsignedType is unsigned(3 downto 0); + + function sscanf(value : character) return natural; + function sscanf(value : character) return nibbleUlogicType; + function sscanf(value : character) return nibbleUnsignedType; + function sscanf(value : string ) return natural; + function sscanf(value : string ) return unsigned; + function sscanf(value : string ) return std_ulogic_vector; + function sscanf(value : string ) return time; + + procedure sscanf(value : inout line; time_val : out time); + +END testUtils; diff --git a/Libs/Common_test/hdl/testUtils_pkg_body.vhd b/Libs/Common_test/hdl/testUtils_pkg_body.vhd new file mode 100644 index 0000000..88c6205 --- /dev/null +++ b/Libs/Common_test/hdl/testUtils_pkg_body.vhd @@ -0,0 +1,924 @@ +PACKAGE BODY testUtils IS + + --============================================================================ + -- console output + -- + + procedure print(value : string) is + variable my_line : line; + begin + write(my_line, value); + writeLine(output, my_line); + deallocate(my_line); + end print; + + + --============================================================================ + -- string manipulation + -- + + ------------------------------------------------------------------------------ + -- change to lowercase + ------------------------------------------------------------------------------ + procedure lc(value: inout line) is + variable out_line: line; + begin + for index in value'range loop + if (value(index) >= 'A') and (value(index) <= 'Z') then + value(index) := character'val(character'pos(value(index)) + - character'pos('A') + + character'pos('a') + ); + end if; + end loop; + end lc; + + function lc(value: string) return string is + variable out_line: line; + begin + write(out_line, value); + lc(out_line); + return(out_line.all); + end lc; + + ------------------------------------------------------------------------------ + -- change to uppercase + ------------------------------------------------------------------------------ + procedure uc(value: inout line) is + variable out_line: line; + begin + for index in value'range loop + if (value(index) >= 'a') and (value(index) <= 'z') then + value(index) := character'val(character'pos(value(index)) + - character'pos('a') + + character'pos('A') + ); + end if; + end loop; + end uc; + + function uc(value: string) return string is + variable out_line: line; + begin + write(out_line, value); + uc(out_line); + return(out_line.all); + end uc; + + ------------------------------------------------------------------------------ + -- formatted string output: padding and justifying + ------------------------------------------------------------------------------ + function pad( + value : string; + string_length : natural; + fill_char : character := ' '; + right_justify : boolean := false + ) return string is + variable value_line : line; + variable out_line : line; + variable value_length : natural; + variable shift_sign : boolean; + begin + write(value_line, value); + value_length := value_line.all'length; + if string_length = 0 then + write(out_line, value_line.all); + elsif string_length > value_length then + if right_justify then + if (value_line.all(value_line.all'left) <= '-') and not(fill_char = ' ') then + shift_sign := true; + write(out_line, value_line.all(value_line.all'left)); + end if; + for index in 1 to string_length-value_length loop + write(out_line, fill_char); + end loop; + end if; + if shift_sign then + write(out_line, value_line.all(value_line.all'left+1 to value_line.all'right)); + else + write(out_line, value_line.all); + end if; + if not right_justify then + for index in 1 to string_length-value_length loop + write(out_line, fill_char); + end loop; + end if; + elsif string_length < value_length then + write(out_line, '#'); + write(out_line, value_line.all(value_length-string_length+2 to value_length)); + else + write(out_line, value_line.all); + end if; + deallocate(value_line); + return(out_line.all); + end pad; + + ------------------------------------------------------------------------------ + -- remove separator characters at beginning and end of line + ------------------------------------------------------------------------------ + procedure rm_side_separators( + value : inout line; + separators : in string + ) is + variable input_line : line := value; + variable found : boolean := false; + variable position : integer := 0; + begin + -- remove all separators in the beginning + position := -1; + for character_index in input_line'range loop + found := false; + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + found := true; + end if; + end loop; + if found then + position := character_index; + else + exit; + end if; + end loop; + if position > -1 then + input_line := new string'( input_line(position+1 to input_line'right) ); + end if; + + -- remove all separators in the end + position := -1; + for character_index in input_line'reverse_range loop + found := false; + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + found := true; + end if; + end loop; + if found then + position := character_index; + else + exit; + end if; + end loop; + if position > -1 then + input_line := new string'( input_line(input_line'left to position-1) ); + end if; + + value := input_line; + end; + + procedure rm_side_separators(value : inout line) is + begin + rm_side_separators(value, " :" & ht); + end; + + ------------------------------------------------------------------------------ + -- remove multiple occurences of separator characters, keeping one single + ------------------------------------------------------------------------------ + procedure trim_line( + value : inout line; + separators : in string + ) is + variable input_line: line := value; + variable output_line: line := new string'(""); + variable is_separator, was_separator : boolean := false; + begin + rm_side_separators(input_line); + for character_index in input_line'range loop + is_separator := false; + for separator_index in separators'range loop + if input_line.all(character_index) = separators(separator_index) then + is_separator := true; + end if; + end loop; + if not (is_separator and was_separator) then + write(output_line, input_line.all(character_index)); + end if; + was_separator := is_separator; + end loop; + + value := output_line; + end; + + procedure trim_line(value : inout line) is + begin + trim_line(value, " :" & ht); + end; + + ------------------------------------------------------------------------------ + -- remove all occurences of separator characters + ------------------------------------------------------------------------------ + procedure rm_all_separators( + value : inout line; + separators : in string + ) is + variable input_line : line := value; + variable is_separator : boolean := false; + begin + + -- remove separators from beginn and end of the line + -- rm_separator_be(value, separators); + + -- empty output line + value := new string'(""); + + -- find all separator symbols + for character_index in input_line'range loop + is_separator := false; + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + is_separator := true; + end if; + end loop; + if not is_separator then + write(value, input_line.all(character_index)); + end if; + end loop; + + end; + + procedure rm_all_separators(value : inout line) is + begin + rm_all_separators(value, " _." & ht); + end; + + ------------------------------------------------------------------------------ + -- read first "word" out of a line + ------------------------------------------------------------------------------ + procedure read_first( + value : inout line; + separators : in string; + first : out line + ) is + variable input_line: line; + variable position: natural := 0; + begin + input_line := value; + for character_index in input_line.all'reverse_range loop + for separator_index in separators'range loop + if input_line.all(character_index) = separators(separator_index) then + position := character_index; + end if; + end loop; + end loop; + if position > 1 then + first := new string'(input_line.all(input_line'left to position-1)); + value := new string'(input_line(position+1 to input_line'right)); + else + first := new string'(input_line.all); + value := new string'(""); + end if; + end; + + procedure read_first(value : inout line; first : out line) is + begin + read_first(value, " :" & ht, first); + end; + + ------------------------------------------------------------------------------ + -- read last "word" out of a line + ------------------------------------------------------------------------------ + procedure read_last( + value : inout line; + separators : in string; + last : out line + ) is + variable input_line: line := value; + variable position: natural := 0; + begin + for character_index in input_line'range loop + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + position := character_index; + end if; + end loop; + end loop; + if position <= input_line'right and + position > 0 then + value := new string'(input_line(input_line'left to position-1)); + last := new string'(input_line(position+1 to input_line'right)); + else + last := new string'(input_line.all); + end if; + end; + + procedure read_last(value : inout line; last : out line) is + begin + read_last(value, " :" & ht, last); + end; + + + --============================================================================ + -- formatted string output, internal functions + -- + + ------------------------------------------------------------------------------ + -- get format specification + ------------------------------------------------------------------------------ + procedure get_format_items( + format : string; + right_justify : out boolean; + add_sign : out boolean; + fill_char : out character; + total_length : out natural; + point_precision : out natural; + format_type : inout line + ) is + variable find_sign : boolean := false; + variable find_padding : boolean := false; + variable find_length : boolean := false; + variable find_precision : boolean := false; + variable find_type : boolean := false; + variable right_justify_int : boolean := true; + variable total_length_int : natural := 0; + variable point_precision_int : natural := 0; + begin + add_sign := false; + fill_char := ' '; + for index in 1 to format'length loop + if find_type then + write(format_type, format(index)); + end if; + if find_precision then + if (format(index) >= '0') and (format(index) <= '9') then + point_precision_int := 10*point_precision_int + character'pos(format(index)) - character'pos('0'); + if format(index+1) >= 'A' then + find_precision := false; + find_type := true; + end if; + end if; + end if; + if find_length then + if (format(index) >= '0') and (format(index) <= '9') then + total_length_int := 10*total_length_int + character'pos(format(index)) - character'pos('0'); + end if; + if format(index) = '.' then + find_length := false; + find_precision := true; + elsif format(index+1) >= 'A' then + find_length := false; + find_type := true; + end if; + end if; + if find_padding then + if format(index) = '0' then + if right_justify_int then + fill_char := '0'; + end if; + end if; + find_padding := false; + if format(index+1) >= 'A' then + find_type := true; + else + find_length := true; + end if; + end if; + if find_sign then + if format(index) = '-' then + right_justify_int := false; + end if; + if format(index) = '+' then + add_sign := true; + end if; + find_sign := false; + if format(index+1) <= '-' then + find_sign := true; + elsif format(index+1) = '0' then + find_padding := true; + elsif format(index+1) >= 'A' then + find_type := true; + else + find_length := true; + end if; + end if; + if format(index) = '%' then + if format(index+1) <= '-' then + find_sign := true; + elsif format(index+1) = '0' then + find_padding := true; + elsif format(index+1) >= 'A' then + find_type := true; + else + find_length := true; + end if; + end if; + end loop; + right_justify := right_justify_int; + total_length := total_length_int; + point_precision := point_precision_int; + end get_format_items; + + + ------------------------------------------------------------------------------ + -- formatted string output: converting std_ulogic to character + ------------------------------------------------------------------------------ + function to_character(value: std_ulogic) return character is + variable out_value: character; + begin + case value is + when 'U' => out_value := 'U'; + when 'X' => out_value := 'X'; + when '0' => out_value := '0'; + when '1' => out_value := '1'; + when 'Z' => out_value := 'Z'; + when 'W' => out_value := 'W'; + when 'L' => out_value := 'L'; + when 'H' => out_value := 'H'; + when '-' => out_value := '-'; + end case; + return(out_value); + end to_character; + + ------------------------------------------------------------------------------ + -- formatted string output: binary integer + ------------------------------------------------------------------------------ + function sprintf_b(value: std_ulogic_vector) return string is + variable out_line : line; + begin + for index in value'range loop + write(out_line, to_character(value(index))); + end loop; + return(out_line.all); + end sprintf_b; + + ------------------------------------------------------------------------------ + -- formatted string output: decimal integer + ------------------------------------------------------------------------------ + function sprintf_d( + right_justify : boolean; + add_sign : boolean; + fill_char : character; + string_length : natural; + value : integer + ) return string is + variable value_line : line; + begin + if add_sign and (value >= 0) then + write(value_line, '+'); + end if; + write(value_line, value); + if string_length = 0 then + return(value_line.all); + else + return(pad(value_line.all, string_length, fill_char, right_justify)); + end if; + end sprintf_d; + + ------------------------------------------------------------------------------ + -- formatted string output: fixed point real + ------------------------------------------------------------------------------ + function sprintf_f( + right_justify : boolean; + add_sign : boolean; + fill_char : character; + string_length : natural; + point_precision : natural; + value : real + ) return string is + variable point_precision_int : natural; + variable integer_part : integer; + variable decimal_part : natural; + variable value_line : line; + begin + if point_precision = 0 then + point_precision_int := 6; + else + point_precision_int := point_precision; + end if; + if value >= 0.0 then + integer_part := integer(value-0.5); + else + integer_part := - integer(-value-0.5); + end if; + decimal_part := abs(integer((value-real(integer_part))*(10.0**point_precision_int))); + if add_sign and (value >= 0.0) then + write(value_line, '+'); + end if; + write(value_line, integer_part); + write(value_line, '.'); + write(value_line, sprintf_d(true, false, '0', point_precision_int, decimal_part)); + if string_length = 0 then + return(value_line.all); + else + return(pad(value_line.all, string_length, fill_char, right_justify)); + end if; + end sprintf_f; + + ------------------------------------------------------------------------------ + -- formatted string output: hexadecimal integer + ------------------------------------------------------------------------------ + function sprintf_X( + extend_unsigned : boolean; + value : std_ulogic_vector + ) return string is + variable bit_count : positive; + variable value_line : line; + variable out_line : line; + variable nibble: string(1 to 4); + begin + bit_count := value'length; + while (bit_count mod 4) /= 0 loop + if extend_unsigned then + write(value_line, to_character('0')); + else + write(value_line, to_character(value(value'high))); + end if; + bit_count := bit_count + 1; + end loop; + write(value_line, sprintf_b(value)); + for index in value_line.all'range loop + if (index mod 4) = 0 then + nibble := value_line.all(index-3 to index); + case nibble is + when "0000" => write(out_line, 0); + when "0001" => write(out_line, 1); + when "0010" => write(out_line, 2); + when "0011" => write(out_line, 3); + when "0100" => write(out_line, 4); + when "0101" => write(out_line, 5); + when "0110" => write(out_line, 6); + when "0111" => write(out_line, 7); + when "1000" => write(out_line, 8); + when "1001" => write(out_line, 9); + when "1010" => write(out_line, 'A'); + when "1011" => write(out_line, 'B'); + when "1100" => write(out_line, 'C'); + when "1101" => write(out_line, 'D'); + when "1110" => write(out_line, 'E'); + when "1111" => write(out_line, 'F'); + when others => write(out_line, 'X'); + end case; + end if; + end loop; + return(out_line.all); + end sprintf_X; + + + --============================================================================ + -- formatted string output, interface functions + -- + + ------------------------------------------------------------------------------ + -- integer + ------------------------------------------------------------------------------ + function sprintf(format : string; value : integer) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if format_type.all = "b" then + if string_length = 0 then + string_length := 8; + end if; + return(sprintf_b(std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0)))); + elsif format_type.all = "d" then + return(sprintf_d(right_justify, add_sign, fill_char, string_length, value)); + elsif format_type.all = "f" then + return(sprintf_f(right_justify, add_sign, fill_char, + string_length, point_precision, real(value))); + elsif (format_type.all = "X") or (format_type.all = "x") then + if string_length = 0 then + string_length := 8; + end if; + string_length := 4*string_length; + if format_type.all = "X" then + return(sprintf_X(false, std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0)))); + else + return(lc(sprintf_X(false, std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0))))); + end if; + else + return("Unhandled format type: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- real + ------------------------------------------------------------------------------ + function sprintf(format : string; value : real) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "d") or (point_precision = 0) then + return(sprintf_d(right_justify, add_sign, fill_char, + string_length, integer(value))); + elsif format_type.all = "f" then + return(sprintf_f(right_justify, add_sign, fill_char, + string_length, point_precision, value)); + else + return("Unhandled format type: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- std_logic + ------------------------------------------------------------------------------ + function sprintf(format : string; value : std_logic) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + variable logic_vector: std_logic_vector(1 to 1); + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "b") or (format_type.all = "d") or + (format_type.all = "X") or (format_type.all = "x") then + logic_vector(1) := value; + return(sprintf(format, std_ulogic_vector(logic_vector))); + else + return("Not a std_logic format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- std_ulogic_vector + ------------------------------------------------------------------------------ + function sprintf(format : string; value : std_ulogic_vector) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable bit_string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + bit_string_length, point_precision, format_type); + if format_type.all = "b" then + return(pad(sprintf_b(value), bit_string_length, fill_char, right_justify)); + elsif format_type.all = "d" then + return(sprintf_d(right_justify, add_sign, fill_char, bit_string_length, to_integer(unsigned(value)))); + elsif (format_type.all = "X") or (format_type.all = "x") then + if format_type.all = "X" then + return(pad(sprintf_X(true, value), bit_string_length, fill_char, right_justify)); + else + return(lc(pad(sprintf_X(true, value), bit_string_length, fill_char, right_justify))); + end if; + else + return("Not a std_ulogic_vector format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- std_logic_vector + ------------------------------------------------------------------------------ + function sprintf(format : string; value : std_logic_vector) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "b") or (format_type.all = "d") or + (format_type.all = "X") or (format_type.all = "x") then + return(sprintf(format, std_ulogic_vector(value))); + else + return("Not a std_logic_vector format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- unsigned + ------------------------------------------------------------------------------ + function sprintf(format : string; value : unsigned) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "b") or (format_type.all = "d") or + (format_type.all = "X") or (format_type.all = "x") then + return(sprintf(format, std_ulogic_vector(value))); + else + return("Not an unsigned format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- signed + ------------------------------------------------------------------------------ + function sprintf(format : string; value : signed) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable bit_string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + bit_string_length, point_precision, format_type); + if (fill_char = '0') and (value(value'left) = '1') then + fill_char := '1'; + end if; + if format_type.all = "b" then + return(pad(sprintf_b(std_ulogic_vector(value)), bit_string_length, fill_char, right_justify)); + elsif format_type.all = "d" then + return(sprintf_d(right_justify, add_sign, fill_char, bit_string_length, to_integer(signed(value)))); + elsif (format_type.all = "X") or (format_type.all = "x") then + if fill_char = '1' then + fill_char := 'F'; + end if; + if format_type.all = "X" then + return(pad(sprintf_X(true, std_ulogic_vector(value)), bit_string_length, fill_char, right_justify)); + else + return(lc(pad(sprintf_X(true, std_ulogic_vector(value)), bit_string_length, fill_char, right_justify))); + end if; + else + return("Not a signed format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- time + ------------------------------------------------------------------------------ + function sprintf(format : string; value : time) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + variable scaling : real; + variable base_time : time; + variable unit : string(1 to 3); + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if format_type.all(format_type.all'left) = 't' then + scaling := 10.0**point_precision; + if format_type.all = "tp" then + base_time := 1 ps; + unit := " ps"; + elsif format_type.all = "tn" then + base_time := 1 ns; + unit := " ns"; + elsif format_type.all = "tu" then + base_time := 1 us; + unit := " us"; + elsif format_type.all = "tm" then + base_time := 1 ms; + unit := " ms"; + elsif format_type.all = "ts" then + base_time := 1 sec; + unit := " s."; + else + return("Undefined time format: '" & format_type.all & "'"); + end if; + if point_precision = 0 then + return(sprintf_d(right_justify, add_sign, fill_char, + string_length, value/base_time) & unit); + else + return(sprintf_f(right_justify, add_sign, fill_char, string_length, + point_precision, real(scaling*value/base_time)/scaling) & unit); + end if; + else + return("Not a time format: '" & format_type.all & "'"); + end if; + end sprintf; + + + --============================================================================ + -- formatted string input + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- read a nibble out of a character + ------------------------------------------------------------------------------ + function sscanf(value : character) return natural is + begin + if (value >= '0') and (value <= '9') then + return(character'pos(value) - character'pos('0')); + elsif (value >= 'a') and (value <= 'f') then + return(character'pos(value) - character'pos('a') + 10); + elsif (value >= 'A') and (value <= 'F') then + return(character'pos(value) - character'pos('A') + 10); + else + return(0); + end if; + end sscanf; + + function sscanf(value : character) return nibbleUnsignedType is + begin + return(to_unsigned(sscanf(value), nibbleUnsignedType'length)); + end sscanf; + + function sscanf(value : character) return nibbleUlogicType is + variable unsigned_value : nibbleUnsignedType; + begin + unsigned_value := sscanf(value); + return(std_ulogic_vector(unsigned_value)); + end sscanf; + + ------------------------------------------------------------------------------ + -- read an binary word out of a string + ------------------------------------------------------------------------------ + function sscanf(value : string) return natural is + variable integer_value : natural; + begin + integer_value := 0; + for index in value'left to value'right loop + integer_value := integer_value*16 + sscanf(value(index)); + end loop; + return(integer_value); + end; + + function sscanf(value : string) return unsigned is + variable unsigned_value : unsigned(4*value'length-1 downto 0); + begin + unsigned_value := to_unsigned(0,unsigned_value'length); + for index in value'left to value'right loop + unsigned_value := shift_left(unsigned_value,4) + to_unsigned(sscanf(value(index)),4); + end loop; + return(unsigned_value); + end; + + function sscanf(value : string) return std_ulogic_vector is + variable unsigned_value : unsigned(4*value'length-1 downto 0); + begin + unsigned_value := sscanf(value); + return(std_ulogic_vector(unsigned_value)); + end; + + ------------------------------------------------------------------------------ + -- read time from a string + -- time can be formated as follows: + -- "1ps" or "1 ps" or " 1 ps " or " 1ps" + -- possible time units are: hr, min, sec, ms, us, ns, ps, fs + ------------------------------------------------------------------------------ + procedure sscanf( + value : inout line; + time_val : out time + ) is + variable time_line : line := value; + variable time_base : string(1 to 3); + variable time_value : integer; + variable time_int : time; + begin + -- remove all spaces and tabs + rm_all_separators(time_line); + + -- strip time base (3 last characters) + time_base := time_line(time_line'right-2 to time_line'right); + + -- separate time value and base + if time_base(2 to 3) = "hr" then + time_int := 1 hr; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base = "min" then + time_int := 1 min; + time_value := integer'value(time_line(time_line'left to time_line'right -3)); + elsif time_base = "sec" then + time_int := 1 sec; + time_value := integer'value(time_line(time_line'left to time_line'right -3)); + elsif time_base(2 to 3) = "ms" then + time_int := 1 ms; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "us" then + time_int := 1 us; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "ns" then + time_int := 1 ns; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "ps" then + time_int := 1 ps; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "fs" then + time_int := 1 fs; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + else + time_int := 0 ps; + time_value := 1; + end if; + + -- build time from value and base + time_val := time_int * time_value; + + end; + + function sscanf(value : string) return time is + variable value_line : line; + variable time_val : time; + begin + value_line := new string'(value); + sscanf(value_line, time_val); + return(time_val); + end; + +END testUtils; diff --git a/Libs/Common_test/hdl/testUtils_tb_test.vhd b/Libs/Common_test/hdl/testUtils_tb_test.vhd new file mode 100644 index 0000000..23d0239 --- /dev/null +++ b/Libs/Common_test/hdl/testUtils_tb_test.vhd @@ -0,0 +1,102 @@ +LIBRARY std; + USE std.textio.all; +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF testUtils_tb IS +BEGIN + + process + variable test_line, result_line : LINE; + begin + + print("Integers, right justified"); + print(" |" & sprintf("%6d", 12) & "| 12|"); + print(" |" & sprintf("%06d", 12) & "|000012|"); + print(" |" & sprintf("%+6d", 12) & "| +12|"); + print(" |" & sprintf("%+06d", 12) & "|+00012|"); + print(" |" & sprintf("%6d", -12) & "| -12|"); + print(" |" & sprintf("%06d", -12) & "|-00012|"); + print("Integers, left justified"); + print(" |" & sprintf("%-6d", 12) & "|12 |"); + print(" |" & sprintf("%-06d", 12) & "|12 |"); + print(" |" & sprintf("%-+6d", 12) & "|+12 |"); + print(" |" & sprintf("%-+06d", 12) & "|+12 |"); + print(" |" & sprintf("%-6d", -12) & "|-12 |"); + print(" |" & sprintf("%-06d", -12) & "|-12 |"); + print("Integers, others"); + print(" |" & sprintf("%d", 12) & "|12|"); + print(" |" & sprintf("%6tu", 12) & "|"); + print(" |" & sprintf("%6d", 123456) & "|123456|"); + print(" |" & sprintf("%6d", 12345678) & "|#45678|"); + print(" |" & sprintf("%f", 12) & "|12.000000|"); + print(" |" & sprintf("%10f", 12) & "| 12.000000|"); + print(" |" & sprintf("%8.3f", 12) & "| 12.000|"); + print(" |" & sprintf("%b", 12) & "|00001100|"); + print(" |" & sprintf("%4b", 12) & "|1100|"); + print(" |" & sprintf("%6b", 12) & "|001100|"); + print(" |" & sprintf("%X", 12) & "|0000000C|"); + print(" |" & sprintf("%4x", 12) & "|000c|"); + print(" |" & sprintf("%2X", 12) & "|0C|"); + + print(cr & "Reals, integer rounding"); + print(" |" & sprintf("%6d", 1.3) & "| 1|"); + print(" |" & sprintf("%6d", 1.5) & "| 2|"); + print(" |" & sprintf("%6d", 1.7) & "| 2|"); + print("Reals, right justified"); + print(" |" & sprintf("%8.3f", 1.03) & "| 1.030|"); + print(" |" & sprintf("%8.3f", 1.07) & "| 1.070|"); + print(" |" & sprintf("%08.3f", 1.03) & "|0001.030|"); + print(" |" & sprintf("%+08.3f", 1.03) & "|+001.030|"); + print(" |" & sprintf("%8.3f", -1.03) & "| -1.030|"); + print(" |" & sprintf("%8.3f", -1.07) & "| -1.070|"); + print("Reals, left justified"); + print(" |" & sprintf("%-8.3f", 1.3) & "|1.300 |"); + print(" |" & sprintf("%-8.3f", 1.7) & "|1.700 |"); + print(" |" & sprintf("%-08.3f", 1.3) & "|1.300 |"); + print(" |" & sprintf("%-+08.3f", 1.3) & "|+1.300 |"); + print(" |" & sprintf("%-8.3f", -1.3) & "|-1.300 |"); + print(" |" & sprintf("%-8.3f", -1.7) & "|-1.700 |"); + + print(cr & "Logic values"); + print(" |" & sprintf("%b", '0') & "|0|"); + print(" |" & sprintf("%3b", '1') & "| 1|"); + print(" |" & sprintf("%-3d", '0') & "|0 |"); + print(" |" & sprintf("%3X", '1') & "| 1|"); + + print(cr & "Logic vectors, binary"); + print(" |" & sprintf("%b", std_ulogic_vector'("1100")) & "|1100|"); + print(" |" & sprintf("%3b", std_logic_vector'("1100")) & "|#00|"); + print(" |" & sprintf("%4b", unsigned'("1100")) & "|1100|"); + print(" |" & sprintf("%8b", signed'("1100")) & "| 1100|"); + print(" |" & sprintf("%-8b", signed'("1100")) & "|1100 |"); + print(" |" & sprintf("%08b", unsigned'("1100")) & "|00001100|"); + print(" |" & sprintf("%08b", signed'("1100")) & "|11111100|"); + print("Logic vectors, hexadecimal"); + print(" |" & sprintf("%X", std_ulogic_vector'("1100101011111110")) & "|CAFE|"); + print(" |" & sprintf("%3X", std_logic_vector'("1100101011111110")) & "|#FE|"); + print(" |" & sprintf("%4x", unsigned'("1100101011111110")) & "|cafe|"); + print(" |" & sprintf("%8X", signed'("1100101011111110")) & "| CAFE|"); + print(" |" & sprintf("%02X", unsigned'("1100")) & "|0C|"); + print(" |" & sprintf("%02X", signed'("1100")) & "|FC|"); + print("Logic vectors, decimal"); + print(" |" & sprintf("%d", std_ulogic_vector'("1100")) & "|12|"); + print(" |" & sprintf("%d", unsigned'("1100")) & "|12|"); + print(" |" & sprintf("%d", signed'("1100")) & "|-4|"); + print("Logic vectors, others"); + print(" |" & sprintf("%8tu", std_ulogic_vector'("1100")) & "|"); + + print(cr & "Time"); + print(" |" & sprintf("%9tu", 1.3 us) & "| 1 us|"); + print(" |" & sprintf("%9.3tu", 1.3 us) & "| 1.300 us|"); + print(" |" & sprintf("%10tu", 1.3 us) & "| 1 us|"); + + print(cr & "Lines"); + test_line := new string'("Hello brave new world!"); + read_first(test_line, result_line); + print(" |" & result_line.all & ""& test_line.all & "|Hellobrave new world!|"); + + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/toggler_tester_test.vhd b/Libs/Common_test/hdl/toggler_tester_test.vhd new file mode 100644 index 0000000..ba76bc0 --- /dev/null +++ b/Libs/Common_test/hdl/toggler_tester_test.vhd @@ -0,0 +1,56 @@ +ARCHITECTURE test OF toggler_tester IS + + constant clockFrequency : real := 66.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + process + begin + input <= '0'; + wait for 10*clockPeriod; + -- transition 0 to 1 + input <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod, + '1' after 10*clockPeriod; + wait for 50*clockPeriod; + -- transition 1 to 0 + input <= '0', + '1' after 1*clockPeriod, + '0' after 3*clockPeriod, + '1' after 5*clockPeriod, + '0' after 6*clockPeriod, + '1' after 8*clockPeriod, + '0' after 10*clockPeriod; + wait for 50*clockPeriod; + -- short 1 pulse + input <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod; + wait for 50*clockPeriod; + -- further toggle commands + input <= '1', '0' after clockPeriod; + wait for 50*clockPeriod; + input <= '1', '0' after clockPeriod; + wait for 50*clockPeriod; + -- short 1 pulse + -- end of simulation + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hds/.hdlsidedata/_clockGenerator_sim.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_clockGenerator_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_clockGenerator_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_commonLib_tb_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_commonLib_tb_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_commonLib_tb_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_debouncerULogicVector_tester_RTL.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_debouncerULogicVector_tester_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_debouncerULogicVector_tester_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_debouncer_tester_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_debouncer_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_debouncer_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_rotaryToUnsigned_tester_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_rotaryToUnsigned_tester_test.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_rotaryToUnsigned_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_entity.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_struct.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tester_entity.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tester_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tester_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_spikeFilter_tester_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_spikeFilter_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_spikeFilter_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg.vhd._fpf new file mode 100644 index 0000000..b606e20 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2002 diff --git a/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg_body.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg_body.vhd._fpf new file mode 100644 index 0000000..b606e20 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg_body.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2002 diff --git a/Libs/Common_test/hds/.hdlsidedata/_testUtils_tb_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_testUtils_tb_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_testUtils_tb_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_toggler_tester_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_toggler_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_toggler_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/_clockgenerator._epf b/Libs/Common_test/hds/_clockgenerator._epf new file mode 100644 index 0000000..8b8ac62 --- /dev/null +++ b/Libs/Common_test/hds/_clockgenerator._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom clockGenerator_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Common_test/hds/_commonlib_tb._epf b/Libs/Common_test/hds/_commonlib_tb._epf new file mode 100644 index 0000000..092da9c --- /dev/null +++ b/Libs/Common_test/hds/_commonlib_tb._epf @@ -0,0 +1,3 @@ +TOP_MARKER atom 1 +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom commonLib_tb_test.vhd diff --git a/Libs/Common_test/hds/_debouncer_tb._epf b/Libs/Common_test/hds/_debouncer_tb._epf new file mode 100644 index 0000000..1c7f3f7 --- /dev/null +++ b/Libs/Common_test/hds/_debouncer_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom debouncer_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_debouncer_tester._epf b/Libs/Common_test/hds/_debouncer_tester._epf new file mode 100644 index 0000000..967ba8a --- /dev/null +++ b/Libs/Common_test/hds/_debouncer_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom debouncer_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Common_test/hds/_debouncerulogicvector_tb._epf b/Libs/Common_test/hds/_debouncerulogicvector_tb._epf new file mode 100644 index 0000000..2101ec7 --- /dev/null +++ b/Libs/Common_test/hds/_debouncerulogicvector_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom debouncer@u@logic@vector_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_debouncerulogicvector_tester._epf b/Libs/Common_test/hds/_debouncerulogicvector_tester._epf new file mode 100644 index 0000000..89828c8 --- /dev/null +++ b/Libs/Common_test/hds/_debouncerulogicvector_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom debouncerULogicVector_tester_RTL.vhd diff --git a/Libs/Common_test/hds/_rotarytounsigned_tb._epf b/Libs/Common_test/hds/_rotarytounsigned_tb._epf new file mode 100755 index 0000000..2036a2a --- /dev/null +++ b/Libs/Common_test/hds/_rotarytounsigned_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom rotary@to@unsigned_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_rotarytounsigned_tester._epf b/Libs/Common_test/hds/_rotarytounsigned_tester._epf new file mode 100755 index 0000000..f758d03 --- /dev/null +++ b/Libs/Common_test/hds/_rotarytounsigned_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom rotaryToUnsigned_tester_test.vhd diff --git a/Libs/Common_test/hds/_spikefilter_tb._epf b/Libs/Common_test/hds/_spikefilter_tb._epf new file mode 100644 index 0000000..5050211 --- /dev/null +++ b/Libs/Common_test/hds/_spikefilter_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom spike@filter_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_testutils_tb._epf b/Libs/Common_test/hds/_testutils_tb._epf new file mode 100644 index 0000000..40137e1 --- /dev/null +++ b/Libs/Common_test/hds/_testutils_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom testUtils_tb_test.vhd +DEFAULT_ARCHITECTURE atom test +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_toggler_tb._epf b/Libs/Common_test/hds/_toggler_tb._epf new file mode 100644 index 0000000..94877cb --- /dev/null +++ b/Libs/Common_test/hds/_toggler_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom toggler_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_toggler_tester._epf b/Libs/Common_test/hds/_toggler_tester._epf new file mode 100644 index 0000000..17d8815 --- /dev/null +++ b/Libs/Common_test/hds/_toggler_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom toggler_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Common_test/hds/clock@generator/symbol.sb b/Libs/Common_test/hds/clock@generator/symbol.sb new file mode 100644 index 0000000..6c2577f --- /dev/null +++ b/Libs/Common_test/hds/clock@generator/symbol.sb @@ -0,0 +1,1499 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2074,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 320,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "clock" +t "std_uLogic" +o 1 +suid 2063,0 +) +) +uid 2546,0 +) +*15 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "reset" +t "std_uLogic" +o 2 +suid 2064,0 +) +) +uid 2548,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 333,0 +optionalChildren [ +*16 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *17 (MRCItem +litem &1 +pos 2 +dimension 20 +) +uid 254,0 +optionalChildren [ +*18 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 257,0 +) +*19 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 259,0 +) +*20 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 261,0 +) +*21 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 2547,0 +) +*22 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 2549,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +textAngle 90 +) +uid 255,0 +optionalChildren [ +*23 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 263,0 +) +*24 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 267,0 +) +*25 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 269,0 +) +*26 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 271,0 +) +*27 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 273,0 +) +*28 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 275,0 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"/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/debouncer_tb" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/debouncer_tb" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "debouncer_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value 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"rotaryBitNb" +type "positive" +value "rotaryBitNb" +) +(GiElement +name "outputBitNb" +type "positive" +value "outputBitNb" +) +(GiElement +name "counterBitNb" +type "positive" +value "deglitchCounterBitNb" +) +] +mwi 0 +uid 6518,0 +) +] +libraryRefs [ +"ieee" +] +) +version "31.1" +appVersion "2018.1 (Build 12)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "/home/francois/Favorites/ElN_local/Labs/ElN_support/SinewaveGenerator/Libs/Common_test/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Favorites/ElN_local/Labs/ElN_support/SinewaveGenerator/Libs/Common_test/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Favorites/ElN_local/Labs/ElN_support/SinewaveGenerator/Libs/Common_test/hds/rotary@to@unsigned_tb/struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Favorites/ElN_local/Labs/ElN_support/SinewaveGenerator/Libs/Common_test/hds/rotary@to@unsigned_tb/struct.bd.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Favorites/ElN_local/Labs/ElN_support/SinewaveGenerator/Libs/Common_test/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Favorites/ElN_local/Labs/ElN_support/SinewaveGenerator/Libs/Common_test/hds/rotary@to@unsigned_tb" +) +(vvPair +variable "d_logical" +value "/home/francois/Favorites/ElN_local/Labs/ElN_support/SinewaveGenerator/Libs/Common_test/hds/rotaryToUnsigned_tb" +) +(vvPair +variable "date" +value "11/07/19" +) +(vvPair +variable "day" +value "Thu" +) +(vvPair +variable "day_long" +value "Thursday" +) +(vvPair +variable "dd" +value "07" +) +(vvPair +variable "designName" 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"$SCRATCH_DIR/$DESIGN_NAME/Common_test/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "rotaryToUnsigned_tb" +) +(vvPair +variable "month" +value "Nov" +) +(vvPair +variable "month_long" +value "November" +) +(vvPair +variable "p" +value "/home/francois/Favorites/ElN_local/Labs/ElN_support/SinewaveGenerator/Libs/Common_test/hds/rotary@to@unsigned_tb/struct.bd" +) +(vvPair +variable "p_logical" +value "/home/francois/Favorites/ElN_local/Labs/ElN_support/SinewaveGenerator/Libs/Common_test/hds/rotaryToUnsigned_tb/struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\Board\\ise" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "task_perl" +value "c:\\eda\\hds2007.1a\\resources\\perl\\bin\\perl.exe" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "13:40:36" +) +(vvPair +variable "unit" +value "rotaryToUnsigned_tb" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2018.1 (Build 12)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 52,0 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"/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/spike@filter_tb/struct.bd.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/spike@filter_tb" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/spikeFilter_tb" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "spikeFilter_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/28/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "13:43:51" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Common_test" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../VerifThin_TB/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libs/Common_test/work" +) +(vvPair +variable "mm" +value "08" +) +(vvPair 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a/Libs/Common_test/hds/spike@filter_tb/symbol.sb b/Libs/Common_test/hds/spike@filter_tb/symbol.sb new file mode 100644 index 0000000..551f7ed --- /dev/null +++ b/Libs/Common_test/hds/spike@filter_tb/symbol.sb @@ -0,0 +1,1278 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) 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+duLibraryName "Common" +duName "toggler" +elements [ +(GiElement +name "counterBitNb" +type "natural" +value "counterBitNb" +) +] +mwi 0 +uid 6332,0 +) +] +libraryRefs [ +"ieee" +] +) +version "31.1" +appVersion "2018.1 (Build 12)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/toggler_tb/struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/toggler_tb/struct.bd.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/toggler_tb" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/toggler_tb" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "toggler_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/28/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "13:43:56" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Common_test" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../VerifThin_TB/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libs/Common_test/work" +) +(vvPair +variable "mm" +value "08" +) +(vvPair +variable "module_name" +value "toggler_tb" +) +(vvPair +variable "month" +value "Aug" +) +(vvPair +variable "month_long" +value "August" +) +(vvPair +variable "p" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/toggler_tb/struct.bd" +) +(vvPair +variable "p_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/toggler_tb/struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair 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"50550,7000,51450,10000" +st "toggle" +ju 2 +blo "51250,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 303,0 +va (VaSet +font "courier,8,0" +) +xt "44000,2000,59000,2900" +st "toggle : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "toggle" +t "std_ulogic" +o 4 +suid 16,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,59000,14000" +) +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "courier,8,1" +) +xt "33250,9100,39250,10000" +st "Common_test" +blo "33250,9800" +) +second (Text +uid 12,0 +va (VaSet +font "courier,8,1" +) +xt "33250,10000,40750,10900" +st "toggler_tester" +blo "33250,10700" +) +) +gi *64 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "courier,8,0" +) +xt "13000,6000,23500,6900" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*65 (Grouping +uid 16,0 +optionalChildren [ +*66 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,52400,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*67 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56800,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*68 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,52400,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*69 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,35800,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*70 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,66400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*71 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,59000,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*72 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "38000,44500,47000,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*73 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,35200,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*74 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,35800,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*75 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,53000,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *76 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*77 (Text +uid 49,0 +va (VaSet +font "courier,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*78 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,18600,4000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2600,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,8,0" +) +xt "450,2150,1450,3050" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "courier,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "Common_test" +entityName "toggler_tb" +viewName "struct.bd" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "courier,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "courier,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *79 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "courier,8,0" +) +xt "0,12000,10500,12900" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *80 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "42000,5600,44500,6500" +st "User:" +blo "42000,6300" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "44000,6500,44000,6500" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 311,0 +activeModelName "Symbol:CDM" +) diff --git a/Libs/Common_test/sim/debouncerULogicVector.do b/Libs/Common_test/sim/debouncerULogicVector.do new file mode 100644 index 0000000..dc4bdbd --- /dev/null +++ b/Libs/Common_test/sim/debouncerULogicVector.do @@ -0,0 +1,24 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /debouncerulogicvector_tb/reset +add wave -noupdate /debouncerulogicvector_tb/clock +add wave -noupdate -expand /debouncerulogicvector_tb/input +add wave -noupdate -format Analog-Step -height 30 -max 15.0 -radix unsigned /debouncerulogicvector_tb/i_filt/debouncecounter +add wave -noupdate -expand /debouncerulogicvector_tb/debounced +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {8842679128 ps} 0} +configure wave -namecolwidth 285 +configure wave -valuecolwidth 42 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {2100 ns} diff --git a/Libs/Common_test/sim/rotaryToUnsigned.do b/Libs/Common_test/sim/rotaryToUnsigned.do new file mode 100644 index 0000000..36ec08a --- /dev/null +++ b/Libs/Common_test/sim/rotaryToUnsigned.do @@ -0,0 +1,26 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /rotarytounsigned_tb/reset +add wave -noupdate /rotarytounsigned_tb/clock +add wave -noupdate -format Analog-Step -height 50 -max 14.999999999999998 -radix unsigned -radixshowbase 0 /rotarytounsigned_tb/rotary +add wave -noupdate /rotarytounsigned_tb/I_DUT/glitchDelayCounter +add wave -noupdate -format Analog-Step -height 50 -max 14.999999999999998 -radix unsigned -childformat {{/rotarytounsigned_tb/I_DUT/rotaryStable(3) -radix unsigned} {/rotarytounsigned_tb/I_DUT/rotaryStable(2) -radix unsigned} {/rotarytounsigned_tb/I_DUT/rotaryStable(1) -radix unsigned} {/rotarytounsigned_tb/I_DUT/rotaryStable(0) -radix unsigned}} -radixshowbase 0 -subitemconfig {/rotarytounsigned_tb/I_DUT/rotaryStable(3) {-height 17 -radix unsigned -radixshowbase 0} /rotarytounsigned_tb/I_DUT/rotaryStable(2) {-height 17 -radix unsigned -radixshowbase 0} /rotarytounsigned_tb/I_DUT/rotaryStable(1) {-height 17 -radix unsigned -radixshowbase 0} /rotarytounsigned_tb/I_DUT/rotaryStable(0) {-height 17 -radix unsigned -radixshowbase 0}} /rotarytounsigned_tb/I_DUT/rotaryStable +add wave -noupdate -format Analog-Step -height 200 -max 63.0 -radix unsigned -radixshowbase 0 /rotarytounsigned_tb/number +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 243 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {210 us} diff --git a/Libs/Common_test/sim/spikeFilter.do b/Libs/Common_test/sim/spikeFilter.do new file mode 100644 index 0000000..be55526 --- /dev/null +++ b/Libs/Common_test/sim/spikeFilter.do @@ -0,0 +1,23 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /spikefilter_tb/reset +add wave -noupdate /spikefilter_tb/clock +add wave -noupdate /spikefilter_tb/input +add wave -noupdate /spikefilter_tb/filtered +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3129283489 ps} 0} +configure wave -namecolwidth 285 +configure wave -valuecolwidth 42 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {42 us} diff --git a/Libs/Gates/hdl/and2_sim.vhd b/Libs/Gates/hdl/and2_sim.vhd new file mode 100644 index 0000000..f2c1ddd --- /dev/null +++ b/Libs/Gates/hdl/and2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and2 IS +BEGIN + out1 <= in1 and in2 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and2inv1_sim.vhd b/Libs/Gates/hdl/and2inv1_sim.vhd new file mode 100644 index 0000000..61770f5 --- /dev/null +++ b/Libs/Gates/hdl/and2inv1_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and2inv1 IS +BEGIN + out1 <= in1 and (not in2) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and2inv2_sim.vhd b/Libs/Gates/hdl/and2inv2_sim.vhd new file mode 100644 index 0000000..356240a --- /dev/null +++ b/Libs/Gates/hdl/and2inv2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and2inv2 IS +BEGIN + out1 <= (not in1) and (not in2) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and3_sim.vhd b/Libs/Gates/hdl/and3_sim.vhd new file mode 100644 index 0000000..c1468e4 --- /dev/null +++ b/Libs/Gates/hdl/and3_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and3 IS +BEGIN + out1 <= in1 and in2 and in3 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and3inv1_sim.vhd b/Libs/Gates/hdl/and3inv1_sim.vhd new file mode 100644 index 0000000..7df64cb --- /dev/null +++ b/Libs/Gates/hdl/and3inv1_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and3inv1 IS +BEGIN + out1 <= (not in1) and in2 and in3 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and3inv2_sim.vhd b/Libs/Gates/hdl/and3inv2_sim.vhd new file mode 100644 index 0000000..1c3d98d --- /dev/null +++ b/Libs/Gates/hdl/and3inv2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and3inv2 IS +BEGIN + out1 <= (not in1) and (not in2) and in3 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and3inv3_sim.vhd b/Libs/Gates/hdl/and3inv3_sim.vhd new file mode 100644 index 0000000..1aaf84a --- /dev/null +++ b/Libs/Gates/hdl/and3inv3_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and3inv3 IS +BEGIN + out1 <= (not in1) and (not in2) and (not in3) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and4_sim.vhd b/Libs/Gates/hdl/and4_sim.vhd new file mode 100644 index 0000000..a1ebcb2 --- /dev/null +++ b/Libs/Gates/hdl/and4_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and4 IS +BEGIN + out1 <= in1 and in2 and in3 and in4 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and4inv1_sim.vhd b/Libs/Gates/hdl/and4inv1_sim.vhd new file mode 100644 index 0000000..aee155f --- /dev/null +++ b/Libs/Gates/hdl/and4inv1_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and4inv1 IS +BEGIN + out1 <= (not in1) and in2 and in3 and in4 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and4inv2_sim.vhd b/Libs/Gates/hdl/and4inv2_sim.vhd new file mode 100644 index 0000000..f87e651 --- /dev/null +++ b/Libs/Gates/hdl/and4inv2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and4inv2 IS +BEGIN + out1 <= (not in1) and (not in2) and in3 and in4 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and4inv3_sim.vhd b/Libs/Gates/hdl/and4inv3_sim.vhd new file mode 100644 index 0000000..6547d0f --- /dev/null +++ b/Libs/Gates/hdl/and4inv3_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and4inv3 IS +BEGIN + out1 <= (not in1) and (not in2) and (not in3) and in4 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and4inv4_sim.vhd b/Libs/Gates/hdl/and4inv4_sim.vhd new file mode 100644 index 0000000..55cde7f --- /dev/null +++ b/Libs/Gates/hdl/and4inv4_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and4inv4 IS +BEGIN + out1 <= (not in1) and (not in2) and (not in3) and (not in4) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/and5_sim.vhd b/Libs/Gates/hdl/and5_sim.vhd new file mode 100644 index 0000000..b73d266 --- /dev/null +++ b/Libs/Gates/hdl/and5_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF and5 IS +BEGIN + out1 <= in1 and in2 and in3 and in4 and in5 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/bufferLogicVector_sim.vhd b/Libs/Gates/hdl/bufferLogicVector_sim.vhd new file mode 100644 index 0000000..86feae4 --- /dev/null +++ b/Libs/Gates/hdl/bufferLogicVector_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF bufferLogicVector IS +BEGIN + out1 <= in1 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/bufferSigned_sim.vhd b/Libs/Gates/hdl/bufferSigned_sim.vhd new file mode 100644 index 0000000..64a3a6a --- /dev/null +++ b/Libs/Gates/hdl/bufferSigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF bufferSigned IS +BEGIN + out1 <= in1 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/bufferULogicVector_sim.vhd b/Libs/Gates/hdl/bufferULogicVector_sim.vhd new file mode 100644 index 0000000..c800c2f --- /dev/null +++ b/Libs/Gates/hdl/bufferULogicVector_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF bufferUlogicVector IS +BEGIN + out1 <= in1 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/bufferULogic_sim.vhd b/Libs/Gates/hdl/bufferULogic_sim.vhd new file mode 100644 index 0000000..ecd14af --- /dev/null +++ b/Libs/Gates/hdl/bufferULogic_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF bufferUlogic IS +BEGIN + out1 <= in1 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/bufferUnsigned_sim.vhd b/Libs/Gates/hdl/bufferUnsigned_sim.vhd new file mode 100644 index 0000000..937ada0 --- /dev/null +++ b/Libs/Gates/hdl/bufferUnsigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF bufferUnsigned IS +BEGIN + out1 <= in1 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/demux1to2_sim.vhd b/Libs/Gates/hdl/demux1to2_sim.vhd new file mode 100644 index 0000000..82e98b8 --- /dev/null +++ b/Libs/Gates/hdl/demux1to2_sim.vhd @@ -0,0 +1,19 @@ +ARCHITECTURE sim OF demux1to2 IS +BEGIN + + process(sel, in1) + begin + -- default values + out0 <= '0'; + out1 <= '0'; + + -- selection + case sel is + when '0' => out0 <= in1 after delay; + when '1' => out1 <= in1 after delay; + when others => NULL; + end case; + + end process; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/demux1to4_sim.vhd b/Libs/Gates/hdl/demux1to4_sim.vhd new file mode 100644 index 0000000..2d76d3b --- /dev/null +++ b/Libs/Gates/hdl/demux1to4_sim.vhd @@ -0,0 +1,23 @@ +ARCHITECTURE sim OF demux1to4 IS +BEGIN + + process(sel, in1) + begin + -- default values + out0 <= '0'; + out1 <= '0'; + out2 <= '0'; + out3 <= '0'; + + -- selection + case sel is + when "00" => out0 <= in1 after delay; + when "01" => out1 <= in1 after delay; + when "10" => out2 <= in1 after delay; + when "11" => out3 <= in1 after delay; + when others => NULL; + end case; + + end process; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/gates_pkg.vhd b/Libs/Gates/hdl/gates_pkg.vhd new file mode 100644 index 0000000..46d5370 --- /dev/null +++ b/Libs/Gates/hdl/gates_pkg.vhd @@ -0,0 +1,9 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +PACKAGE gates IS + +-- constant gateDelay: time := 1 ns; + constant gateDelay: time := 0.1 ns; + +END gates; diff --git a/Libs/Gates/hdl/inverter_sim.vhd b/Libs/Gates/hdl/inverter_sim.vhd new file mode 100644 index 0000000..82499cf --- /dev/null +++ b/Libs/Gates/hdl/inverter_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF inverter IS +BEGIN + out1 <= NOT in1 after delay; +END sim; diff --git a/Libs/Gates/hdl/logic0_sim.vhd b/Libs/Gates/hdl/logic0_sim.vhd new file mode 100644 index 0000000..4bf83a8 --- /dev/null +++ b/Libs/Gates/hdl/logic0_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF logic0 IS +BEGIN + logic_0 <= '0'; +END sim; diff --git a/Libs/Gates/hdl/logic1_sim.vhd b/Libs/Gates/hdl/logic1_sim.vhd new file mode 100644 index 0000000..7a5359e --- /dev/null +++ b/Libs/Gates/hdl/logic1_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF logic1 IS +BEGIN + logic_1 <= '1'; +END sim; diff --git a/Libs/Gates/hdl/mux16to1_sim.vhd b/Libs/Gates/hdl/mux16to1_sim.vhd new file mode 100644 index 0000000..3364b29 --- /dev/null +++ b/Libs/Gates/hdl/mux16to1_sim.vhd @@ -0,0 +1,33 @@ +ARCHITECTURE sim OF mux16to1 IS + +BEGIN + + P1: process(sel, + in0, in1, in2, in3, + in4, in5, in6, in7, + in8, in9, in10, in11, + in12, in13, in14, in15 + ) + begin + case to_integer(sel) is + when 0 => muxOut <= in0 after delay; + when 1 => muxOut <= in1 after delay; + when 2 => muxOut <= in2 after delay; + when 3 => muxOut <= in3 after delay; + when 4 => muxOut <= in4 after delay; + when 5 => muxOut <= in5 after delay; + when 6 => muxOut <= in6 after delay; + when 7 => muxOut <= in7 after delay; + when 8 => muxOut <= in8 after delay; + when 9 => muxOut <= in9 after delay; + when 10 => muxOut <= in10 after delay; + when 11 => muxOut <= in11 after delay; + when 12 => muxOut <= in12 after delay; + when 13 => muxOut <= in13 after delay; + when 14 => muxOut <= in14 after delay; + when 15 => muxOut <= in15 after delay; + when others => null; + end case; + end process P1; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/mux2to1Signed_sim.vhd b/Libs/Gates/hdl/mux2to1Signed_sim.vhd new file mode 100644 index 0000000..9f88771 --- /dev/null +++ b/Libs/Gates/hdl/mux2to1Signed_sim.vhd @@ -0,0 +1,22 @@ +ARCHITECTURE sim OF mux2to1Signed IS + + signal selInt: std_ulogic; + +BEGIN + + selInt <= to_X01(sel); + + muxSelect: process(selInt, in0, in1) + begin + if selInt = '0' then + muxOut <= in0 after delay; + elsif selInt = '1' then + muxOut <= in1 after delay; + elsif in0 = in1 then + muxOut <= in0 after delay; + else + muxOut <= (others => 'X') after delay; + end if; + end process muxSelect; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/mux2to1ULogicVector_sim.vhd b/Libs/Gates/hdl/mux2to1ULogicVector_sim.vhd new file mode 100644 index 0000000..7820eb9 --- /dev/null +++ b/Libs/Gates/hdl/mux2to1ULogicVector_sim.vhd @@ -0,0 +1,22 @@ +ARCHITECTURE sim OF mux2to1ULogicVector IS + + signal selInt: std_ulogic; + +BEGIN + + selInt <= to_X01(sel); + + muxSelect: process(selInt, in0, in1) + begin + if selInt = '0' then + muxOut <= in0 after delay; + elsif selInt = '1' then + muxOut <= in1 after delay; + elsif in0 = in1 then + muxOut <= in0 after delay; + else + muxOut <= (others => 'X') after delay; + end if; + end process muxSelect; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/mux2to1Unsigned_sim.vhd b/Libs/Gates/hdl/mux2to1Unsigned_sim.vhd new file mode 100644 index 0000000..6d43ff6 --- /dev/null +++ b/Libs/Gates/hdl/mux2to1Unsigned_sim.vhd @@ -0,0 +1,22 @@ +ARCHITECTURE sim OF mux2to1Unsigned IS + + signal selInt: std_ulogic; + +BEGIN + + selInt <= to_X01(sel); + + muxSelect: process(selInt, in0, in1) + begin + if selInt = '0' then + muxOut <= in0 after delay; + elsif selInt = '1' then + muxOut <= in1 after delay; + elsif in0 = in1 then + muxOut <= in0 after delay; + else + muxOut <= (others => 'X') after delay; + end if; + end process muxSelect; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/mux2to1_sim.vhd b/Libs/Gates/hdl/mux2to1_sim.vhd new file mode 100644 index 0000000..ebc7d46 --- /dev/null +++ b/Libs/Gates/hdl/mux2to1_sim.vhd @@ -0,0 +1,43 @@ +ARCHITECTURE sim OF mux2to1 IS + subtype tSelect is std_uLogic_vector(0 to 2); +BEGIN + + muxSelect: process(sel, in0, in1) + begin + if sel = '1' then + muxOut <= in1 after delay; + elsif sel = '0' then + muxOut <= in0 after delay; + else + muxOut <= 'X' after delay; + end if; + end process muxSelect; + +-- muxSelect: process(sel, in0, in1) +-- begin +-- -- case tSelect'(to_X01(sel & in0 & in1)) is +-- case to_X01(tSelect'(sel & in0 & in1)) is +-- -- select in0 +-- when "000" => muxOut <= '0' after delay; +-- when "001" => muxOut <= '0' after delay; +-- when "00X" => muxOut <= '0' after delay; +-- when "010" => muxOut <= '1' after delay; +-- when "011" => muxOut <= '1' after delay; +-- when "01X" => muxOut <= '1' after delay; +-- -- select in1 +-- when "100" => muxOut <= '0' after delay; +-- when "110" => muxOut <= '0' after delay; +-- when "1X0" => muxOut <= '0' after delay; +-- when "101" => muxOut <= '1' after delay; +-- when "111" => muxOut <= '1' after delay; +-- when "1X1" => muxOut <= '1' after delay; +-- -- select in0 equal to in1 +-- when "X00" => muxOut <= '0' after delay; +-- when "X11" => muxOut <= '1' after delay; +-- -- others +-- when others => muxOut <= 'X' after delay; +-- end case; +-- end process muxSelect; + + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/mux4to1Signed_sim.vhd b/Libs/Gates/hdl/mux4to1Signed_sim.vhd new file mode 100644 index 0000000..7e9e5f4 --- /dev/null +++ b/Libs/Gates/hdl/mux4to1Signed_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF mux4to1Signed IS + +BEGIN + + muxSelect: process(sel, in0, in1, in2, in3) + begin + case to_integer(sel) is + when 0 => muxOut <= in0 after delay; + when 1 => muxOut <= in1 after delay; + when 2 => muxOut <= in2 after delay; + when 3 => muxOut <= in3 after delay; + when others => muxOut <= (others => 'X') after delay; + end case; + end process muxSelect; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/mux4to1ULogicVector_sim.vhd b/Libs/Gates/hdl/mux4to1ULogicVector_sim.vhd new file mode 100644 index 0000000..a3e8aa4 --- /dev/null +++ b/Libs/Gates/hdl/mux4to1ULogicVector_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF mux4to1ULogicVector IS + +BEGIN + + muxSelect: process(sel, in0, in1, in2, in3) + begin + case to_integer(sel) is + when 0 => muxOut <= in0 after delay; + when 1 => muxOut <= in1 after delay; + when 2 => muxOut <= in2 after delay; + when 3 => muxOut <= in3 after delay; + when others => muxOut <= (others => 'X') after delay; + end case; + end process muxSelect; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/mux4to1Unsigned_sim.vhd b/Libs/Gates/hdl/mux4to1Unsigned_sim.vhd new file mode 100644 index 0000000..eb5c7a0 --- /dev/null +++ b/Libs/Gates/hdl/mux4to1Unsigned_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF mux4to1Unsigned IS + +BEGIN + + muxSelect: process(sel, in0, in1, in2, in3) + begin + case to_integer(sel) is + when 0 => muxOut <= in0 after delay; + when 1 => muxOut <= in1 after delay; + when 2 => muxOut <= in2 after delay; + when 3 => muxOut <= in3 after delay; + when others => muxOut <= (others => 'X') after delay; + end case; + end process muxSelect; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/mux4to1_sim.vhd b/Libs/Gates/hdl/mux4to1_sim.vhd new file mode 100644 index 0000000..0b95077 --- /dev/null +++ b/Libs/Gates/hdl/mux4to1_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF mux4to1 IS + +BEGIN + + muxSelect: process(sel, in0, in1, in2, in3) + begin + case to_integer(sel) is + when 0 => muxOut <= in0 after delay; + when 1 => muxOut <= in1 after delay; + when 2 => muxOut <= in2 after delay; + when 3 => muxOut <= in3 after delay; + when others => muxOut <= 'X' after delay; + end case; + end process muxSelect; + +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/nand2_sim.vhd b/Libs/Gates/hdl/nand2_sim.vhd new file mode 100644 index 0000000..91a4938 --- /dev/null +++ b/Libs/Gates/hdl/nand2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF nand2 IS +BEGIN + out1 <= not( in1 and in2 ) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/nor2_m_sim.vhd b/Libs/Gates/hdl/nor2_m_sim.vhd new file mode 100644 index 0000000..ff972f0 --- /dev/null +++ b/Libs/Gates/hdl/nor2_m_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF nor2_m IS +BEGIN + out1 <= (not in1) and (not in2) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/nor2_sim.vhd b/Libs/Gates/hdl/nor2_sim.vhd new file mode 100644 index 0000000..c7dc8dc --- /dev/null +++ b/Libs/Gates/hdl/nor2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF nor2 IS +BEGIN + out1 <= not( in1 or in2 ) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/onesSigned_sim.vhd b/Libs/Gates/hdl/onesSigned_sim.vhd new file mode 100644 index 0000000..09f9420 --- /dev/null +++ b/Libs/Gates/hdl/onesSigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF onesSigned IS +BEGIN + ones <= (others => '1'); +END sim; diff --git a/Libs/Gates/hdl/onesUnsigned_sim.vhd b/Libs/Gates/hdl/onesUnsigned_sim.vhd new file mode 100644 index 0000000..2778f83 --- /dev/null +++ b/Libs/Gates/hdl/onesUnsigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF onesUnsigned IS +BEGIN + ones <= (others => '1'); +END sim; diff --git a/Libs/Gates/hdl/or2_m_sim.vhd b/Libs/Gates/hdl/or2_m_sim.vhd new file mode 100644 index 0000000..a760cfd --- /dev/null +++ b/Libs/Gates/hdl/or2_m_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or2_m IS +BEGIN + out1 <= in1 or in2 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/or2_sim.vhd b/Libs/Gates/hdl/or2_sim.vhd new file mode 100644 index 0000000..6675513 --- /dev/null +++ b/Libs/Gates/hdl/or2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or2 IS +BEGIN + out1 <= in1 or in2 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/or2inv1_sim.vhd b/Libs/Gates/hdl/or2inv1_sim.vhd new file mode 100644 index 0000000..05e1584 --- /dev/null +++ b/Libs/Gates/hdl/or2inv1_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or2inv1 IS +BEGIN + out1 <= (not in1) or in2 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/or2inv2_sim.vhd b/Libs/Gates/hdl/or2inv2_sim.vhd new file mode 100644 index 0000000..bc6aac1 --- /dev/null +++ b/Libs/Gates/hdl/or2inv2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or2inv2 IS +BEGIN + out1 <= (not in1) or (not in2) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/or3_m_sim.vhd b/Libs/Gates/hdl/or3_m_sim.vhd new file mode 100644 index 0000000..36591ca --- /dev/null +++ b/Libs/Gates/hdl/or3_m_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or3_m IS +BEGIN + out1 <= in1 or in2 or in3 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/or3_sim.vhd b/Libs/Gates/hdl/or3_sim.vhd new file mode 100644 index 0000000..bf6745e --- /dev/null +++ b/Libs/Gates/hdl/or3_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or3 IS +BEGIN + out1 <= in1 or in2 or in3 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/or4_m_sim.vhd b/Libs/Gates/hdl/or4_m_sim.vhd new file mode 100644 index 0000000..1d4abab --- /dev/null +++ b/Libs/Gates/hdl/or4_m_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or4_m IS +BEGIN + out1 <= in1 or in2 or in3 or in4 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/or4_sim.vhd b/Libs/Gates/hdl/or4_sim.vhd new file mode 100644 index 0000000..9643021 --- /dev/null +++ b/Libs/Gates/hdl/or4_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or4 IS +BEGIN + out1 <= in1 or in2 or in3 or in4 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/or5_m_sim.vhd b/Libs/Gates/hdl/or5_m_sim.vhd new file mode 100644 index 0000000..c7e2345 --- /dev/null +++ b/Libs/Gates/hdl/or5_m_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or5_m IS +BEGIN + out1 <= in1 or in2 or in3 or in4 or in5 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/or5_sim.vhd b/Libs/Gates/hdl/or5_sim.vhd new file mode 100644 index 0000000..817c260 --- /dev/null +++ b/Libs/Gates/hdl/or5_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF or5 IS +BEGIN + out1 <= in1 or in2 or in3 or in4 or in5 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/transLogUlog_sim.vhd b/Libs/Gates/hdl/transLogUlog_sim.vhd new file mode 100644 index 0000000..85b459d --- /dev/null +++ b/Libs/Gates/hdl/transLogUlog_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF transLogUlog IS +BEGIN + out1 <= std_ulogic_vector(in1) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/transSignedUlog_sim.vhd b/Libs/Gates/hdl/transSignedUlog_sim.vhd new file mode 100644 index 0000000..1d0a8ca --- /dev/null +++ b/Libs/Gates/hdl/transSignedUlog_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF transSignedUlog IS +BEGIN + out1 <= std_ulogic_vector(in1) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/transSignedUnsigned_sim.vhd b/Libs/Gates/hdl/transSignedUnsigned_sim.vhd new file mode 100644 index 0000000..1d49073 --- /dev/null +++ b/Libs/Gates/hdl/transSignedUnsigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF transSignedUnsigned IS +BEGIN + out1 <= unsigned(in1) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/transUlogSigned_sim.vhd b/Libs/Gates/hdl/transUlogSigned_sim.vhd new file mode 100644 index 0000000..3fa20e8 --- /dev/null +++ b/Libs/Gates/hdl/transUlogSigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF transUlogSigned IS +BEGIN + out1 <= signed(in1) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/transUlogUnsigned_sim.vhd b/Libs/Gates/hdl/transUlogUnsigned_sim.vhd new file mode 100644 index 0000000..e65db96 --- /dev/null +++ b/Libs/Gates/hdl/transUlogUnsigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF transUlogUnsigned IS +BEGIN + out1 <= unsigned(in1) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/transUnsignedSigned_sim.vhd b/Libs/Gates/hdl/transUnsignedSigned_sim.vhd new file mode 100644 index 0000000..31b4904 --- /dev/null +++ b/Libs/Gates/hdl/transUnsignedSigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF transUnsignedSigned IS +BEGIN + out1 <= signed(in1) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/transUnsignedUlog_sim.vhd b/Libs/Gates/hdl/transUnsignedUlog_sim.vhd new file mode 100644 index 0000000..5a8817d --- /dev/null +++ b/Libs/Gates/hdl/transUnsignedUlog_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF transUnsignedUlog IS +BEGIN + out1 <= std_ulogic_vector(in1) after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/xnor2_sim.vhd b/Libs/Gates/hdl/xnor2_sim.vhd new file mode 100644 index 0000000..329e69b --- /dev/null +++ b/Libs/Gates/hdl/xnor2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF xnor2 IS +BEGIN + xorOut <= not in1 xor in2 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/xor2_sim.vhd b/Libs/Gates/hdl/xor2_sim.vhd new file mode 100644 index 0000000..0095859 --- /dev/null +++ b/Libs/Gates/hdl/xor2_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF xor2 IS +BEGIN + xorOut <= in1 xor in2 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/xor3_sim.vhd b/Libs/Gates/hdl/xor3_sim.vhd new file mode 100644 index 0000000..34941b4 --- /dev/null +++ b/Libs/Gates/hdl/xor3_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF xor3 IS +BEGIN + xorOut <= in1 xor in2 xor in3 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/xor4_sim.vhd b/Libs/Gates/hdl/xor4_sim.vhd new file mode 100644 index 0000000..cc45303 --- /dev/null +++ b/Libs/Gates/hdl/xor4_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF xor4 IS +BEGIN + xorOut <= in1 xor in2 xor in3 xor in4 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/xor5_sim.vhd b/Libs/Gates/hdl/xor5_sim.vhd new file mode 100644 index 0000000..18f9cc0 --- /dev/null +++ b/Libs/Gates/hdl/xor5_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF xor5 IS +BEGIN + xorOut <= in1 xor in2 xor in3 xor in4 xor in5 after delay; +END ARCHITECTURE sim; diff --git a/Libs/Gates/hdl/zeroSigned_sim.vhd b/Libs/Gates/hdl/zeroSigned_sim.vhd new file mode 100644 index 0000000..4ca1fa5 --- /dev/null +++ b/Libs/Gates/hdl/zeroSigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF zeroSigned IS +BEGIN + zero <= (others => '0'); +END sim; diff --git a/Libs/Gates/hdl/zeroUnsigned_sim.vhd b/Libs/Gates/hdl/zeroUnsigned_sim.vhd new file mode 100644 index 0000000..f645f0b --- /dev/null +++ b/Libs/Gates/hdl/zeroUnsigned_sim.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE sim OF zeroUnsigned IS +BEGIN + zero <= (others => '0'); +END sim; diff --git a/Libs/Gates/hds/.hdlsidedata/_and2_entity.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and2_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and2_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Libs/Gates/hds/.hdlsidedata/_and2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and2inv1_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and2inv1_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and2inv1_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and2inv1_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and2inv1_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and2inv1_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and2inv2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and2inv2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and2inv2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and2inv2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and2inv2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and2inv2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and3_entity.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and3_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and3_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Libs/Gates/hds/.hdlsidedata/_and3_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and3_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and3_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and3_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and3inv1_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and3inv1_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and3inv1_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and3inv1_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and3inv1_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and3inv1_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and3inv2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and3inv2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and3inv2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and3inv2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and3inv2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and3inv2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and3inv3_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and3inv3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and3inv3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and3inv3_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and3inv3_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and3inv3_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and4_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and4_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4inv1_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and4inv1_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4inv1_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4inv1_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and4inv1_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4inv1_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4inv2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and4inv2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4inv2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4inv2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and4inv2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4inv2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4inv3_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and4inv3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4inv3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4inv3_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and4inv3_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4inv3_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4inv4_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and4inv4_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4inv4_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and4inv4_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and4inv4_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and4inv4_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and5_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_and5_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and5_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_and5_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_and5_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_and5_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferLogicVector_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferLogicVector_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferLogicVector_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferSigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferSigned_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferSigned_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferULogicVector_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferULogicVector_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferULogicVector_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferULogic_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferULogic_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferULogic_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferUnsigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferUnsigned_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferUnsigned_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferlogicvector_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferlogicvector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferlogicvector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_buffersigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_buffersigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_buffersigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferulogic_entity.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferulogic_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferulogic_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferulogic_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferulogic_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferulogic_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferulogicvector_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferulogicvector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferulogicvector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_bufferunsigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_bufferunsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_bufferunsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_demux1to2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_demux1to2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_demux1to2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_demux1to2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_demux1to2_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_demux1to2_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_demux1to4_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_demux1to4_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_demux1to4_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_demux1to4_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_demux1to4_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_demux1to4_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_gates_pkg.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_gates_pkg.vhd._fpf new file mode 100644 index 0000000..83d563a --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_gates_pkg.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_87 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Gates/hds/.hdlsidedata/_inverter_entity.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_inverter_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_inverter_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_inverter_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_inverter_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_inverter_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_inverter_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_inverter_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_inverter_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_logic0_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_logic0_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_logic0_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_logic0_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_logic0_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_logic0_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_logic1_entity.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_logic1_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_logic1_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_logic1_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_logic1_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_logic1_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_logic1_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_logic1_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_logic1_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux16to1_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_mux16to1_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux16to1_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux16to1_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_mux16to1_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux16to1_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux2to1Signed_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_mux2to1Signed_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux2to1Signed_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux2to1ULogicVector_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_mux2to1ULogicVector_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux2to1ULogicVector_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux2to1Unsigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_mux2to1Unsigned_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux2to1Unsigned_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux2to1_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_mux2to1_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux2to1_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux2to1_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_mux2to1_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux2to1_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux2to1signed_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_mux2to1signed_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux2to1signed_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux2to1ulogicvector_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_mux2to1ulogicvector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux2to1ulogicvector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux2to1unsigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_mux2to1unsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux2to1unsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux4to1Signed_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_mux4to1Signed_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux4to1Signed_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux4to1ULogicVector_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_mux4to1ULogicVector_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux4to1ULogicVector_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux4to1Unsigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_mux4to1Unsigned_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux4to1Unsigned_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux4to1_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_mux4to1_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux4to1_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux4to1_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_mux4to1_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux4to1_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux4to1signed_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_mux4to1signed_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux4to1signed_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux4to1ulogicvector_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_mux4to1ulogicvector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux4to1ulogicvector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_mux4to1unsigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_mux4to1unsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_mux4to1unsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_nand2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_nand2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_nand2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_nand2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_nand2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_nand2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_nor2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_nor2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_nor2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_nor2_m_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_nor2_m_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_nor2_m_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_nor2_m_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_nor2_m_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_nor2_m_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_nor2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_nor2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_nor2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_onesSigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_onesSigned_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_onesSigned_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_onesUnsigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_onesUnsigned_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_onesUnsigned_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_onessigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_onessigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_onessigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_onesunsigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_onesunsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_onesunsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or2_m_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or2_m_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or2_m_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or2_m_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or2_m_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or2_m_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or2inv1_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or2inv1_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or2inv1_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or2inv1_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or2inv1_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or2inv1_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or2inv2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or2inv2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or2inv2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or2inv2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or2inv2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or2inv2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or3_entity.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or3_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or3_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Libs/Gates/hds/.hdlsidedata/_or3_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or3_m_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or3_m_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or3_m_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or3_m_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or3_m_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or3_m_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or3_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or3_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or3_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or4_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or4_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or4_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or4_m_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or4_m_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or4_m_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or4_m_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or4_m_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or4_m_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or4_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or4_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or4_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or5_entity.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or5_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or5_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Libs/Gates/hds/.hdlsidedata/_or5_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or5_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or5_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or5_m_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_or5_m_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or5_m_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or5_m_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or5_m_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or5_m_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_or5_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_or5_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_or5_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transLogUlog_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_transLogUlog_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transLogUlog_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transSignedUlog_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_transSignedUlog_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transSignedUlog_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transSignedUnsigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_transSignedUnsigned_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transSignedUnsigned_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transUlogSigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_transUlogSigned_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transUlogSigned_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transUlogUnsigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_transUlogUnsigned_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transUlogUnsigned_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transUnsignedSigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_transUnsignedSigned_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transUnsignedSigned_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transUnsignedUlog_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_transUnsignedUlog_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transUnsignedUlog_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_translogulog_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_translogulog_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_translogulog_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transsignedulog_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_transsignedulog_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transsignedulog_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transsignedunsigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_transsignedunsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transsignedunsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transulogsigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_transulogsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transulogsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transulogunsigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_transulogunsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transulogunsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transunsignedsigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_transunsignedsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transunsignedsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_transunsignedulog_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_transunsignedulog_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_transunsignedulog_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xnor2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_xnor2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xnor2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xnor2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_xnor2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xnor2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xor2_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_xor2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xor2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xor2_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_xor2_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xor2_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xor3_entity.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_xor3_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xor3_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Libs/Gates/hds/.hdlsidedata/_xor3_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_xor3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xor3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xor3_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_xor3_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xor3_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xor4_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_xor4_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xor4_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xor4_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_xor4_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xor4_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xor5_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_xor5_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xor5_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_xor5_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_xor5_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_xor5_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_zeroSigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_zeroSigned_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_zeroSigned_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_zeroUnsigned_sim.vhd._fpf b/Libs/Gates/hds/.hdlsidedata/_zeroUnsigned_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_zeroUnsigned_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_zerosigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_zerosigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_zerosigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/.hdlsidedata/_zerounsigned_entity.vhg._fpf b/Libs/Gates/hds/.hdlsidedata/_zerounsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Gates/hds/.hdlsidedata/_zerounsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Gates/hds/_and2._epf b/Libs/Gates/hds/_and2._epf new file mode 100644 index 0000000..39ade64 --- /dev/null +++ b/Libs/Gates/hds/_and2._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom and2_sim.vhd diff --git a/Libs/Gates/hds/_and5._epf b/Libs/Gates/hds/_and5._epf new file mode 100644 index 0000000..423ef21 --- /dev/null +++ b/Libs/Gates/hds/_and5._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom and5_sim.vhd diff --git a/Libs/Gates/hds/_bufferlogicvector._epf b/Libs/Gates/hds/_bufferlogicvector._epf new file mode 100644 index 0000000..9df73d3 --- /dev/null +++ b/Libs/Gates/hds/_bufferlogicvector._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom bufferLogicVector_sim.vhd diff --git a/Libs/Gates/hds/_buffersigned._epf b/Libs/Gates/hds/_buffersigned._epf new file mode 100644 index 0000000..7b12431 --- /dev/null +++ b/Libs/Gates/hds/_buffersigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom bufferSigned_sim.vhd diff --git a/Libs/Gates/hds/_bufferulogic._epf b/Libs/Gates/hds/_bufferulogic._epf new file mode 100644 index 0000000..35a6dd8 --- /dev/null +++ b/Libs/Gates/hds/_bufferulogic._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom bufferULogic_sim.vhd diff --git a/Libs/Gates/hds/_bufferulogicvector._epf b/Libs/Gates/hds/_bufferulogicvector._epf new file mode 100644 index 0000000..dc22383 --- /dev/null +++ b/Libs/Gates/hds/_bufferulogicvector._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom bufferULogicVector_sim.vhd diff --git a/Libs/Gates/hds/_bufferunsigned._epf b/Libs/Gates/hds/_bufferunsigned._epf new file mode 100644 index 0000000..0e5d4f3 --- /dev/null +++ b/Libs/Gates/hds/_bufferunsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom bufferUnsigned_sim.vhd diff --git a/Libs/Gates/hds/_inverter._epf b/Libs/Gates/hds/_inverter._epf new file mode 100644 index 0000000..ed5001c --- /dev/null +++ b/Libs/Gates/hds/_inverter._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom inverter_sim.vhd diff --git a/Libs/Gates/hds/_logic0._epf b/Libs/Gates/hds/_logic0._epf new file mode 100644 index 0000000..b4b8dc5 --- /dev/null +++ b/Libs/Gates/hds/_logic0._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom logic0_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Gates/hds/_logic1._epf b/Libs/Gates/hds/_logic1._epf new file mode 100644 index 0000000..6d2b94f --- /dev/null +++ b/Libs/Gates/hds/_logic1._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom logic1_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Gates/hds/_mux16to1._epf b/Libs/Gates/hds/_mux16to1._epf new file mode 100644 index 0000000..db9191a --- /dev/null +++ b/Libs/Gates/hds/_mux16to1._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom mux16to1_sim.vhd diff --git a/Libs/Gates/hds/_mux2to1._epf b/Libs/Gates/hds/_mux2to1._epf new file mode 100644 index 0000000..33a1958 --- /dev/null +++ b/Libs/Gates/hds/_mux2to1._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom mux2to1_sim.vhd diff --git a/Libs/Gates/hds/_mux2to1signed._epf b/Libs/Gates/hds/_mux2to1signed._epf new file mode 100644 index 0000000..3bc527c --- /dev/null +++ b/Libs/Gates/hds/_mux2to1signed._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom mux2to1Signed_sim.vhd diff --git a/Libs/Gates/hds/_mux2to1ulogicvector._epf b/Libs/Gates/hds/_mux2to1ulogicvector._epf new file mode 100644 index 0000000..576217a --- /dev/null +++ b/Libs/Gates/hds/_mux2to1ulogicvector._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom mux2to1ULogicVector_sim.vhd diff --git a/Libs/Gates/hds/_mux2to1unsigned._epf b/Libs/Gates/hds/_mux2to1unsigned._epf new file mode 100644 index 0000000..69ff576 --- /dev/null +++ b/Libs/Gates/hds/_mux2to1unsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom mux2to1Unsigned_sim.vhd diff --git a/Libs/Gates/hds/_mux4to1._epf b/Libs/Gates/hds/_mux4to1._epf new file mode 100644 index 0000000..a59efcc --- /dev/null +++ b/Libs/Gates/hds/_mux4to1._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom mux4to1_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Gates/hds/_mux4to1signed._epf b/Libs/Gates/hds/_mux4to1signed._epf new file mode 100644 index 0000000..f789c2a --- /dev/null +++ b/Libs/Gates/hds/_mux4to1signed._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom mux4to1Signed_sim.vhd diff --git a/Libs/Gates/hds/_mux4to1ulogicvector._epf b/Libs/Gates/hds/_mux4to1ulogicvector._epf new file mode 100644 index 0000000..c0b56e7 --- /dev/null +++ b/Libs/Gates/hds/_mux4to1ulogicvector._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom mux4to1ULogicVector_sim.vhd diff --git a/Libs/Gates/hds/_mux4to1unsigned._epf b/Libs/Gates/hds/_mux4to1unsigned._epf new file mode 100644 index 0000000..edd319a --- /dev/null +++ b/Libs/Gates/hds/_mux4to1unsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom mux4to1Unsigned_sim.vhd diff --git a/Libs/Gates/hds/_onessigned._epf b/Libs/Gates/hds/_onessigned._epf new file mode 100644 index 0000000..e10b136 --- /dev/null +++ b/Libs/Gates/hds/_onessigned._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom onesSigned_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Gates/hds/_onesunsigned._epf b/Libs/Gates/hds/_onesunsigned._epf new file mode 100644 index 0000000..68d966b --- /dev/null +++ b/Libs/Gates/hds/_onesunsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom onesUnsigned_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Gates/hds/_or3_m._epf b/Libs/Gates/hds/_or3_m._epf new file mode 100644 index 0000000..64585c2 --- /dev/null +++ b/Libs/Gates/hds/_or3_m._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom or3_m_sim.vhd diff --git a/Libs/Gates/hds/_translogulog._epf b/Libs/Gates/hds/_translogulog._epf new file mode 100644 index 0000000..1dc649e --- /dev/null +++ b/Libs/Gates/hds/_translogulog._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom transLogUlog_sim.vhd diff --git a/Libs/Gates/hds/_transsignedulog._epf b/Libs/Gates/hds/_transsignedulog._epf new file mode 100644 index 0000000..88b1d5b --- /dev/null +++ b/Libs/Gates/hds/_transsignedulog._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom transSignedUlog_sim.vhd diff --git a/Libs/Gates/hds/_transsignedunsigned._epf b/Libs/Gates/hds/_transsignedunsigned._epf new file mode 100644 index 0000000..1088def --- /dev/null +++ b/Libs/Gates/hds/_transsignedunsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom transSignedUnsigned_sim.vhd diff --git a/Libs/Gates/hds/_transulogsigned._epf b/Libs/Gates/hds/_transulogsigned._epf new file mode 100644 index 0000000..81da8e2 --- /dev/null +++ b/Libs/Gates/hds/_transulogsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom transUlogSigned_sim.vhd diff --git a/Libs/Gates/hds/_transulogunsigned._epf b/Libs/Gates/hds/_transulogunsigned._epf new file mode 100644 index 0000000..bc39494 --- /dev/null +++ b/Libs/Gates/hds/_transulogunsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom transUlogUnsigned_sim.vhd diff --git a/Libs/Gates/hds/_transunsignedsigned._epf b/Libs/Gates/hds/_transunsignedsigned._epf new file mode 100644 index 0000000..0649f33 --- /dev/null +++ b/Libs/Gates/hds/_transunsignedsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom transUnsignedSigned_sim.vhd diff --git a/Libs/Gates/hds/_transunsignedulog._epf b/Libs/Gates/hds/_transunsignedulog._epf new file mode 100644 index 0000000..e952239 --- /dev/null +++ b/Libs/Gates/hds/_transunsignedulog._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom transUnsignedUlog_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Gates/hds/_xnor2._epf b/Libs/Gates/hds/_xnor2._epf new file mode 100644 index 0000000..69d89cf --- /dev/null +++ b/Libs/Gates/hds/_xnor2._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom xor2_sim1.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Gates/hds/_zerosigned._epf b/Libs/Gates/hds/_zerosigned._epf new file mode 100644 index 0000000..78a44c6 --- /dev/null +++ b/Libs/Gates/hds/_zerosigned._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom zeroSigned_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Gates/hds/_zerounsigned._epf b/Libs/Gates/hds/_zerounsigned._epf new file mode 100644 index 0000000..4ed55f7 --- /dev/null +++ b/Libs/Gates/hds/_zerounsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom zeroUnsigned_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Gates/hds/and2/symbol.sb b/Libs/Gates/hds/and2/symbol.sb new file mode 100644 index 0000000..bfeaf29 --- /dev/null +++ b/Libs/Gates/hds/and2/symbol.sb @@ -0,0 +1,1479 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "gates" +unitName "gates" +) +] +libraryRefs [ +"ieee" +"gates" +] +) +version "26.1" +appVersion "2018.1 (Build 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"graphical_source_time" +value "14:35:13" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE6996" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "gates" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/ElN/Libraries/Gates/work" +) +(vvPair +variable "mm" +value "09" +) +(vvPair +variable "module_name" +value "mux16to1" +) +(vvPair +variable "month" +value "Sep" +) +(vvPair +variable "month_long" +value "September" +) +(vvPair +variable "p" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\mux16to1\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\mux16to1\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_SCRATCH_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "14:35:13" +) +(vvPair +variable "unit" +value "mux16to1" +) +(vvPair +variable "user" +value "silvan.zahno" +) +(vvPair +variable "version" +value "2018.1 (Build 12)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 86,0 +optionalChildren [ +*89 (SymbolBody +uid 11,0 +optionalChildren [ +*90 (CptPort +uid 51,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 52,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "31250,2625,32000,3375" +) +tg (CPTG +uid 123,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 54,0 +va (VaSet +) +xt "33000,2500,34400,3500" +st "in0" +blo "33000,3300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 114,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,9400,14200,10400" +st "in0 : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "in0" +t "std_uLogic" +o 3 +suid 1,0 +) +) +) +*91 (CptPort +uid 57,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 58,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "31250,4625,32000,5375" +) +tg (CPTG +uid 124,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f 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(VaSet +) +xt "0,1000,17500,5800" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; +LIBRARY gates; + USE gates.gates.all;" +tm "PackageList" +) +] +) +windowSize "25,44,1387,948" +viewArea "-1100,-1100,74338,51040" +cachedDiagramExtent "0,0,73000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "Verdana,8,0" +) +xt "450,2150,1450,3150" +st " +Text +" +tm "RequirementText" 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(MLText +va (VaSet +isHidden 1 +) +xt "20000,5000,20000,5000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVis (PortSigDisplay +sT 1 +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Verdana,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Verdana,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *94 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,8800,5400,9800" +st "Declarations" +blo "0,9600" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,9800,2700,10800" +st "Ports:" +blo "0,10600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,16200,2500,17100" +st "User:" +blo "0,16900" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "0,8800,5800,9800" +st "Internal User:" +blo "0,9600" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,17100,2000,17100" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "32000,8800,32000,8800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 327,0 +activeModelName "Symbol" +) diff --git a/Libs/Gates/hds/trans@log@ulog/symbol.sb b/Libs/Gates/hds/trans@log@ulog/symbol.sb new file mode 100644 index 0000000..d1f62c6 --- /dev/null +++ b/Libs/Gates/hds/trans@log@ulog/symbol.sb @@ -0,0 +1,1453 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "gates" +unitName "gates" +) +] +libraryRefs [ +"ieee" +"gates" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2002,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 99,0 +optionalChildren [ +*2 (LogPort +port (LogicalPort +decl (Decl +n "in1" +t "std_logic_vector" +b "(dataNbBits-1 DOWNTO 0)" +o 1 +suid 1,0 +) +) +uid 100,0 +) +*3 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "out1" +t "std_ulogic_vector" +b "(dataNbBits-1 DOWNTO 0)" +o 2 +suid 2,0 +) +) +uid 101,0 +) +*4 (RefLabelRowHdr +) +*5 (TitleRowHdr +) +*6 (FilterRowHdr +) +*7 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*8 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*9 (GroupColHdr +tm "GroupColHdrMgr" +) +*10 (NameColHdr +tm "NameColHdrMgr" +) +*11 (ModeColHdr +tm "ModeColHdrMgr" +) +*12 (TypeColHdr +tm "TypeColHdrMgr" +) +*13 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*14 (InitColHdr +tm "InitColHdrMgr" +) +*15 (EolColHdr +tm "EolColHdrMgr" +) +] +) +pdm (PhysicalDM +uid 102,0 +optionalChildren [ +*16 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *17 (MRCItem +litem &1 +pos 2 +dimension 20 +) +uid 43,0 +optionalChildren [ +*18 (MRCItem +litem &4 +pos 0 +dimension 20 +uid 46,0 +) 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b/Libs/IO/hdl/tristateBufferSigned_sim.vhd new file mode 100644 index 0000000..c56b0d6 --- /dev/null +++ b/Libs/IO/hdl/tristateBufferSigned_sim.vhd @@ -0,0 +1,5 @@ +ARCHITECTURE sim OF tristateBufferSigned IS +BEGIN + out1 <= in1 after delay when OE = '1' else (others => 'Z') after delay; +END ARCHITECTURE sim; + diff --git a/Libs/IO/hdl/tristateBufferULogicVector_sim.vhd b/Libs/IO/hdl/tristateBufferULogicVector_sim.vhd new file mode 100644 index 0000000..20e5627 --- /dev/null +++ b/Libs/IO/hdl/tristateBufferULogicVector_sim.vhd @@ -0,0 +1,5 @@ +ARCHITECTURE sim OF tristateBufferULogicVector IS +BEGIN + out1 <= std_logic_vector(in1) after delay when OE = '1' else (others => 'Z') after delay; +END ARCHITECTURE sim; + diff --git a/Libs/IO/hdl/tristateBufferULogic_sim.vhd b/Libs/IO/hdl/tristateBufferULogic_sim.vhd new file mode 100644 index 0000000..ba007ba --- /dev/null +++ b/Libs/IO/hdl/tristateBufferULogic_sim.vhd @@ -0,0 +1,5 @@ +ARCHITECTURE sim OF tristateBufferULogic IS +BEGIN + out1 <= in1 after delay when OE = '1' else 'Z' after delay; +END ARCHITECTURE sim; + diff --git a/Libs/IO/hdl/tristateBufferUnsigned_sim.vhd b/Libs/IO/hdl/tristateBufferUnsigned_sim.vhd new file mode 100644 index 0000000..19166d3 --- /dev/null +++ b/Libs/IO/hdl/tristateBufferUnsigned_sim.vhd @@ -0,0 +1,5 @@ +ARCHITECTURE sim OF tristateBufferUnsigned IS +BEGIN + out1 <= in1 after delay when OE = '1' else (others => 'Z') after delay; +END ARCHITECTURE sim; + diff --git a/Libs/IO/hds/.hdlsidedata/_tristateBufferSigned_sim.vhd._fpf b/Libs/IO/hds/.hdlsidedata/_tristateBufferSigned_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/IO/hds/.hdlsidedata/_tristateBufferSigned_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/IO/hds/.hdlsidedata/_tristateBufferULogicVector_sim.vhd._fpf b/Libs/IO/hds/.hdlsidedata/_tristateBufferULogicVector_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/IO/hds/.hdlsidedata/_tristateBufferULogicVector_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/IO/hds/.hdlsidedata/_tristateBufferULogic_sim.vhd._fpf b/Libs/IO/hds/.hdlsidedata/_tristateBufferULogic_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/IO/hds/.hdlsidedata/_tristateBufferULogic_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/IO/hds/.hdlsidedata/_tristateBufferUnsigned_sim.vhd._fpf b/Libs/IO/hds/.hdlsidedata/_tristateBufferUnsigned_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/IO/hds/.hdlsidedata/_tristateBufferUnsigned_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/IO/hds/.hdlsidedata/_tristatebuffersigned_entity.vhg._fpf b/Libs/IO/hds/.hdlsidedata/_tristatebuffersigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/IO/hds/.hdlsidedata/_tristatebuffersigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/IO/hds/.hdlsidedata/_tristatebufferulogic_entity.vhg._fpf b/Libs/IO/hds/.hdlsidedata/_tristatebufferulogic_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/IO/hds/.hdlsidedata/_tristatebufferulogic_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/IO/hds/.hdlsidedata/_tristatebufferulogicvector_entity.vhg._fpf b/Libs/IO/hds/.hdlsidedata/_tristatebufferulogicvector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/IO/hds/.hdlsidedata/_tristatebufferulogicvector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/IO/hds/.hdlsidedata/_tristatebufferunsigned_entity.vhg._fpf b/Libs/IO/hds/.hdlsidedata/_tristatebufferunsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/IO/hds/.hdlsidedata/_tristatebufferunsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/IO/hds/_tristatebuffersigned._epf b/Libs/IO/hds/_tristatebuffersigned._epf new file mode 100644 index 0000000..69ce634 --- /dev/null +++ b/Libs/IO/hds/_tristatebuffersigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom tristateBufferSigned_sim.vhd diff --git a/Libs/IO/hds/_tristatebufferulogicvector._epf b/Libs/IO/hds/_tristatebufferulogicvector._epf new file mode 100644 index 0000000..2da5c39 --- /dev/null +++ b/Libs/IO/hds/_tristatebufferulogicvector._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom sim +DEFAULT_FILE atom tristateBufferULogicVector_sim.vhd diff --git a/Libs/IO/hds/tristate@buffer@signed/symbol.sb b/Libs/IO/hds/tristate@buffer@signed/symbol.sb new file mode 100644 index 0000000..8a28a48 --- /dev/null +++ b/Libs/IO/hds/tristate@buffer@signed/symbol.sb @@ -0,0 +1,1509 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 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(LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *81 (SymDeclBlock +uid 31,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,7800,5400,8800" +st "Declarations" +blo "0,8600" +) +portLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,8800,2700,9800" +st "Ports:" +blo "0,9600" +) +externalLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,12500,2500,13400" +st "User:" +blo "0,13200" +) +internalLabel (Text +uid 2,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,15900,5800,16900" +st "Internal User:" +blo "0,16700" +) +externalText (MLText +uid 3,0 +va (VaSet +font "courier,8,0" +) +xt "2000,13400,2000,13400" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 4,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "2000,17600,2000,17600" +tm "SyDeclarativeTextMgr" +) +) +lastUid 215,0 +activeModelName "Symbol" +) diff --git a/Libs/Lcd/hdl/helloWorld_RTL.vhd b/Libs/Lcd/hdl/helloWorld_RTL.vhd new file mode 100644 index 0000000..62f4e05 --- /dev/null +++ b/Libs/Lcd/hdl/helloWorld_RTL.vhd @@ -0,0 +1,159 @@ +library Common; + use Common.CommonLib.all; + +ARCHITECTURE RTL OF helloWorld IS + + constant displaySequenceLength: positive := 97; + type displayDataType is array (1 to displaySequenceLength+1) + of natural; + constant displayData: displayDataType :=( + character'pos(can), -- cancel (clear display) + character'pos(stx), -- start of text (pos 0,0) + character'pos('H'), -- Line 1 + character'pos('E'), + character'pos('S'), + character'pos('-'), + character'pos('S'), + character'pos('O'), + character'pos('/'), + character'pos('/'), + character'pos('V'), + character'pos('a'), + character'pos('l'), + character'pos('a'), + character'pos('i'), + character'pos('s'), + character'pos(' '), + character'pos('W'), + character'pos('a'), + character'pos('l'), + character'pos('l'), + character'pos('i'), + character'pos('s'), + character'pos(' '), + character'pos(cr), + character'pos(lf), + character'pos('-'), -- Line 2 + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos('-'), + character'pos(cr), + character'pos(lf), + character'pos('F'), -- Line 3 + character'pos('P'), + character'pos('G'), + character'pos('A'), + character'pos('-'), + character'pos('E'), + character'pos('B'), + character'pos('S'), + character'pos(' '), + character'pos('L'), + character'pos('C'), + character'pos('D'), + character'pos('-'), + character'pos('E'), + character'pos('x'), + character'pos('t'), + character'pos('e'), + character'pos('n'), + character'pos('s'), + character'pos('i'), + character'pos('o'), + character'pos('n'), + character'pos(cr), + character'pos(lf), + character'pos('L'), -- Line 4 + character'pos('C'), + character'pos('D'), + character'pos(','), + character'pos(' '), + character'pos('4'), + character'pos(' '), + character'pos('B'), + character'pos('u'), + character'pos('t'), + character'pos('t'), + character'pos('o'), + character'pos('n'), + character'pos('s'), + character'pos(','), + character'pos(' '), + character'pos('8'), + character'pos(' '), + character'pos('L'), + character'pos('e'), + character'pos('d'), + character'pos('s'), + character'pos(stx), -- start of text (pos 0,0) + character'pos('-') + ); + + signal sequenceCounter: unsigned(requiredBitNb(displaySequenceLength+1)-1 downto 0); + signal sequenceDone: std_ulogic; + + signal buttonDelayed, buttonRising: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- find button push + delayButton: process(reset, clock) + begin + if reset='1' then + buttonDelayed <= '0'; + elsif rising_edge(clock) then + buttonDelayed <= button; + end if; + end process delayButton; + + buttonRising <= '1' when (button = '1') and (buttonDelayed = '0') + else '0'; + + ------------------------------------------------------------------------------ + -- display sequence counter + countDisplaySequence: process(reset, clock) + begin + if reset='1' then + sequenceCounter <= to_unsigned(1, sequenceCounter'length); + elsif rising_edge(clock) then + if (buttonRising = '1') and (sequenceDone = '1') then + sequenceCounter <= to_unsigned(1, sequenceCounter'length); + elsif busy = '0' then + if sequenceDone = '0' then + sequenceCounter <= sequenceCounter + 1; + end if; + end if; + end if; + end process countDisplaySequence; + + sequenceDone <= '1' when sequenceCounter > displaySequenceLength + else '0'; + + ------------------------------------------------------------------------------ + -- output control + ascii <= std_ulogic_vector(to_unsigned( + displayData(to_integer(sequenceCounter)), ascii'length + )) when (sequenceCounter > 0) + else (others => '-'); + send <= not busy when sequenceDone = '0' + else '0'; + +END ARCHITECTURE RTL; diff --git a/Libs/Lcd/hdl/lcdCharacterEncoder_RTL.vhd b/Libs/Lcd/hdl/lcdCharacterEncoder_RTL.vhd new file mode 100644 index 0000000..64c0c54 --- /dev/null +++ b/Libs/Lcd/hdl/lcdCharacterEncoder_RTL.vhd @@ -0,0 +1,213 @@ +library Common; + use Common.CommonLib.all; + +ARCHITECTURE Encoder OF lcdCharacterEncoder IS + + constant lcdLineBitNb : positive := 6; + constant lcdPageBitNb : positive := 4; + constant lcdColumnBitNb : positive := 8; + + + type fontDisplayStateType is ( + init, idle, readChar, displayColumns + ); + signal fontDisplayState : fontDisplayStateType; + + signal asciiColumnCounter : unsigned(requiredBitNb(fontColumnNb)-1 downto 0); + signal pixelOffset : unsigned(requiredBitNb(fontColumnNb*fontRowNb-1)-1 downto 0); + + signal pageCounter : unsigned(requiredBitNb(lcdPageNb)-1 downto 0); + signal columnCounter : unsigned(requiredBitNb(lcdColumnNb)-1 downto 0); + + signal A0 : std_ulogic; + + signal pixelPage : std_ulogic_vector(fontRowNb-1 downto 0); + signal pixelColumnHigh : std_ulogic_vector(fontRowNb-1 downto 0); + signal pixelColumnLow : std_ulogic_vector(fontRowNb-1 downto 0); + +BEGIN + ------------------------------------------------------------------------------ + -- diplay FSM + fontDisplaySequencer: process(reset, clock) + begin + if reset = '1' then + fontDisplayState <= init; + elsif rising_edge(clock) then + case fontDisplayState is + when init => + if lcdBusy = '0' then + fontDisplayState <= idle; + end if; + when idle => + if asciiSend = '1' then + fontDisplayState <= readChar; + end if; + when readChar => + fontDisplayState <= displayColumns; + when displayColumns => + if (asciiColumnCounter = 0) and (lcdBusy = '0') then + fontDisplayState <= idle; + end if; + end case; + end if; + end process fontDisplaySequencer; + + asciiBusy <= '0' when fontDisplayState = idle + else '1'; + + a0_proc: process(reset ,clock) + begin + if reset = '1' then + A0 <= '0'; + elsif rising_edge(clock) then + if asciiSend = '1' then + if unsigned(asciiData) < 32 then + A0 <= '0'; + else + A0 <= '1'; + end if; + end if; + end if; + end process a0_proc; + + + ------------------------------------------------------------------------------ + -- ascii column counter + asciiCountColums: process(reset, clock) + begin + if reset = '1' then + asciiColumnCounter <= (others => '0'); + elsif rising_edge(clock) then + if asciiColumnCounter = 0 then + if (fontDisplayState = idle) and (asciiSend = '1') then + asciiColumnCounter <= asciiColumnCounter + 1; + end if; + else + if (fontDisplayState = displayColumns) and (lcdBusy = '0') then + if asciiColumnCounter < fontColumnNb then + asciiColumnCounter <= asciiColumnCounter + 1; + else + asciiColumnCounter <= (others => '0'); + end if; + end if; + end if; + end if; + end process asciiCountColums; + ------------------------------------------------------------------------------ + -- page, column counter + counter: process(reset, clock) + begin + if reset = '1' then + pageCounter <= (others => '0'); + columnCounter <= (others => '0'); + clearDisplay <= '0'; + elsif rising_edge(clock) then + clearDisplay <= '0'; + if asciiSend = '1' then + case to_integer(unsigned(asciiData)) is + when 2 => -- Start of text (home) + pageCounter <= (others => '0'); + columnCounter <= (others => '0'); + when 3 => -- End of text (end) + pageCounter <= to_unsigned(lcdPageNb - 1,pageCounter'length); + columnCounter <= to_unsigned(lcdColumnNb - fontColumnNb, columnCounter'length); + when 8 => -- BS (backspace) (column back) + if (columnCounter - fontColumnNb) < 0 then + columnCounter <= (others => '0'); + else + columnCounter <= columnCounter - fontColumnNb; + end if; + when 10 => -- LF (linefeed) (next line) + if pageCounter = (lcdPageNb-1) then + pageCounter <= (others => '0'); + else + pageCounter <= pageCounter + 1; + end if; + when 11 => -- Vertical Tab (prev line) + if pageCounter = 0 then + pageCounter <= to_unsigned(lcdPageNb - 1,pageCounter'length); + else + pageCounter <= pageCounter - 1; + end if; + when 13 => -- CR (carriage return) (coloumn back) + columnCounter <= (others => '0'); + when 24 => -- CAN (cancel) (clear display) + clearDisplay <= '1'; + when others => + if asciiData >= x"20" then -- normal ascii char + columnCounter <= columnCounter + fontColumnNb; + end if; + end case; + end if; + end if; + end process counter; + + lcdSend <= '1' when + (fontDisplayState = displayColumns) and + (lcdBusy = '0') and + (asciiColumnCounter > 0) + else '0'; + ------------------------------------------------------------------------------ + -- Ram Data + pixelOffset <= resize( + resize(fontColumnNb-asciiColumnCounter, pixelOffset'length)*fontRowNb, + pixelOffset'length + ) when asciiColumnCounter > 0 + else (others => '0'); + pixelPage <= + pixelData( + to_integer(pixelOffset) + fontRowNb-1 downto + to_integer(pixelOffset) + lcdPageBitNb + ) & + std_ulogic_vector(resize(pageCounter,lcdPageBitNb)); + pixelColumnHigh <= + pixelData( + to_integer(pixelOffset) + fontRowNb-1 downto + to_integer(pixelOffset) + (lcdColumnBitNb/2) + ) & + std_ulogic_vector(columnCounter( + columnCounter'high downto (columnCounter'length/2) + )); + pixelColumnLow <= + pixelData( + to_integer(pixelOffset) + fontRowNb-1 downto + to_integer(pixelOffset) + (lcdColumnBitNb/2) + ) & + std_ulogic_vector(columnCounter( + (columnCounter'length/2)-1 downto columnCounter'low + )); + + buildLcdData: process( + A0, pixelData, pixelOffset, + pixelPage, pixelColumnHigh, pixelColumnLow + ) + begin + lcdData(lcdData'high) <= A0; + if A0 = '1' then + lcdData(lcdData'high-1 downto 0) <= pixelData( + to_integer(pixelOffset)+fontRowNb-1 downto to_integer(pixelOffset) + ); + elsif pixelOffset >= 40 then + lcdData(lcdData'high-1 downto 0) <= pixelData( + to_integer(pixelOffset)+fontRowNb-1 downto to_integer(pixelOffset) + ); + elsif pixelOffset >= 32 then + lcdData(lcdData'high-1 downto 0) <= pixelPage; + elsif pixelOffset >= 24 then + lcdData(lcdData'high-1 downto 0) <= pixelColumnHigh; + elsif pixelOffset >= 16 then + lcdData(lcdData'high-1 downto 0) <= pixelColumnLow; + else + lcdData(lcdData'high-1 downto 0) <= pixelData( + to_integer(pixelOffset)+fontRowNb-1 downto to_integer(pixelOffset) + ); + end if; + end process buildLcdData; + --lcdData <= A0 & pixelData(to_integer(pixelOffset)+fontRowNb-1 downto to_integer(pixelOffset)) when (A0 = '1') + -- else A0 & pixelData(to_integer(pixelOffset)+fontRowNb-1 downto to_integer(pixelOffset)) when (pixelOffset >= 40) + -- else A0 & pixelPage when (pixelOffset >= 32) + -- else A0 & pixelColumnHigh when (pixelOffset >= 24) + -- else A0 & pixelColumnLow when (pixelOffset >= 16) + -- else A0 & pixelData(to_integer(pixelOffset)+fontRowNb-1 downto to_integer(pixelOffset)); + +END ARCHITECTURE Encoder; diff --git a/Libs/Lcd/hdl/lcdInitializer_RTL.vhd b/Libs/Lcd/hdl/lcdInitializer_RTL.vhd new file mode 100644 index 0000000..8bbc6d1 --- /dev/null +++ b/Libs/Lcd/hdl/lcdInitializer_RTL.vhd @@ -0,0 +1,105 @@ +library Common; + use Common.CommonLib.all; + +ARCHITECTURE RTL OF lcdInitializer IS + + constant initializationSequenceLength: positive := 14; + type initializationDataType is array (1 to initializationSequenceLength+1) + of std_ulogic_vector(lcdData'range); + constant initializationData: initializationDataType :=( + '0' & X"40", -- Display start line 0 + '0' & X"A1", -- ADC reverse + '0' & X"C0", -- Normal COM0~COM31 + '0' & X"A6", -- Display normal + '0' & X"A2", -- Set bias 1/9 (Duty 1/33) + '0' & X"2F", -- Booster, Regulator and Follower on + '0' & X"F8", -- Set internal Booster to 3x / 4x + '0' & X"00", -- + '0' & X"23", -- Contrast set + '0' & X"81", -- + '0' & X"1F", -- + '0' & X"AC", -- No indicator + '0' & X"00", -- + '0' & X"AF", -- Display on + std_ulogic_vector(to_unsigned(0, lcdData'length)) + ); + + constant clearDisplaySequenceLength : positive := 566;--(3+132)*4 + 3; -- (3 commands + 132 columns) * 4 pages + jump back to start + constant clearDisplayDataLength : positive := 6; + type clearDisplayDataType is array (1 to clearDisplayDataLength+1) + of std_ulogic_vector(lcdData'range); + constant clearDisplayData: clearDisplayDataType :=( + -- ind seq + '0' & X"B0", -- 1 Page 0 + '0' & X"B1", -- 2 Page 1 + '0' & X"B2", -- 3 Page 2 + '0' & X"B3", -- 4 Page 3 + '0' & X"10", -- 5 Column MSB 0 + '0' & X"00", -- 6 Column LSB 0 + '1' & X"00" -- 7 Data "empty" + ); + + signal initSequenceCounter: unsigned(requiredBitNb(initializationSequenceLength+1)-1 downto 0); + signal initSequenceDone: std_ulogic; + signal clearSequenceCounter: unsigned(requiredBitNb(clearDisplaySequenceLength+1)-1 downto 0); + signal clearSequenceDone: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- initialization sequence counter + buildInitSequence: process(reset, clock) + begin + if reset='1' then + initSequenceCounter <= to_unsigned(1, initSequenceCounter'length); + elsif rising_edge(clock) then + if lcdBusy = '0' then + if initSequenceDone = '0' then + initSequenceCounter <= initSequenceCounter + 1; + end if; + end if; + end if; + end process buildInitSequence; + + initSequenceDone <= '1' when initSequenceCounter > initializationSequenceLength + else '0'; + + ------------------------------------------------------------------------------ + -- clear sequence counter + buildClearSequence: process(reset, clock) + begin + if reset='1' then + clearSequenceCounter <= to_unsigned(clearDisplaySequenceLength+1, clearSequenceCounter'length); + elsif rising_edge(clock) then + if lcdBusy = '0' then + if clearDisplay = '1' and initSequenceDone = '1' then + clearSequenceCounter <= to_unsigned(1, clearSequenceCounter'length); + elsif clearSequenceDone = '0' then + clearSequenceCounter <= clearSequenceCounter + 1; + end if; + end if; + end if; + end process buildClearSequence; + + clearSequenceDone <= '1' when clearSequenceCounter > clearDisplaySequenceLength + else '0'; + + ------------------------------------------------------------------------------ + -- data multiplexer + lcdData <= columnData when (initSequenceDone = '1' and clearSequenceDone = '1') + else initializationData(to_integer(initSequenceCounter)) when (initSequenceCounter > 0 and initSequenceDone = '0') + else clearDisplayData(1) when (clearSequenceCounter = 1 or clearSequenceCounter = 564) + else clearDisplayData(2) when (clearSequenceCounter = 137) + else clearDisplayData(3) when (clearSequenceCounter = 273) + else clearDisplayData(4) when (clearSequenceCounter = 409) + else clearDisplayData(5) when (clearSequenceCounter = 2 or clearSequenceCounter = 138 or clearSequenceCounter = 274 or clearSequenceCounter = 410 or clearSequenceCounter = 565) + else clearDisplayData(6) when (clearSequenceCounter = 3 or clearSequenceCounter = 139 or clearSequenceCounter = 275 or clearSequenceCounter = 411 or clearSequenceCounter = 566) + else clearDisplayData(7); + + lcdSend <= columnSend when initSequenceDone = '1' and clearSequenceDone = '1' + else not lcdBusy when initSequenceCounter <= initializationSequenceLength + else not lcdBusy when clearSequenceCounter <= clearDisplaySequenceLength + else '0'; + columnBusy <= lcdBusy when initSequenceDone = '1' and clearSequenceDone = '1' + else '1'; + +END ARCHITECTURE RTL; diff --git a/Libs/Lcd/hdl/lcdSerializer_RTL.vhd b/Libs/Lcd/hdl/lcdSerializer_RTL.vhd new file mode 100644 index 0000000..dfee520 --- /dev/null +++ b/Libs/Lcd/hdl/lcdSerializer_RTL.vhd @@ -0,0 +1,143 @@ +library Common; + use Common.CommonLib.all; + +ARCHITECTURE RTL OF lcdSerializer IS + + ------------------------------------------------------------------------------ + -- The clock-pulse rate of the SCL line can be up to 20 MHz @3.3V + -- The clock frequency is divided by generic value "baudRateDivide" + -- The corresponding "sclEn" is further divided by 2 to generate SCL + -- + signal sclCounter: unsigned(requiredBitNb(baudRateDivide-1)-1 downto 0); + signal sclEn: std_ulogic; + signal scl_int: std_ulogic; + + ------------------------------------------------------------------------------ + -- The minimal reset pulse width is 1 us + -- "sclEn" at 40 MHz has to be divided by 40 to generate the 1 us delay + -- + constant resetCount : natural := 40; + signal resetCounter: unsigned(requiredBitNb(2*resetCount-1)-1 downto 0); + signal resetDone: std_ulogic; + + + ------------------------------------------------------------------------------ + -- Serial data bits have to be stable at the rising edge of SCL + -- Data bits will be updated at the falling edge of SCL + -- + -- Data in comprises 9 bits: A0 (as MSB) and 8 row pixels or command bits + -- A0 selects between command data (A0 = 0) and pixel data (A0 = 1) + -- + constant pixelsPerColumn : positive := data'length-1; + signal dataSampled : std_ulogic_vector(data'range); + signal chipSelect : std_ulogic; + signal updateData: std_ulogic; + signal dataCounter: unsigned(requiredBitNb(pixelsPerColumn+1)-1 downto 0); + +BEGIN + ------------------------------------------------------------------------------ + -- clock divider for SCL + divideClock: process(reset, clock) + begin + if reset='1' then + scl_int <= '0'; + sclCounter <= (others => '0'); + elsif rising_edge(clock) then + if sclEn = '1' then + sclCounter <= (others => '0'); + scl_int <= not scl_int; + else + sclCounter <= sclCounter + 1; + end if; + end if; + end process divideClock; + + sclEn <= '1' when sclCounter = baudRateDivide-1 + else '0'; + + ------------------------------------------------------------------------------ + -- LCD reset + process(clock,reset) + variable i : natural; + begin + if reset = '1' then + resetCounter <= (others => '0'); + elsif rising_edge(clock) then + if sclEn = '1' then + if resetDone = '0' then + resetCounter <= resetCounter + 1; + end if; + end if; + end if; + end process; + + resetDone <= '1' when resetCounter >= 2*resetCount-1 + else '0'; + RST_n <= '1' when resetCounter >= resetCount-1 + else '0'; + + ------------------------------------------------------------------------------ + -- sample input data + process (reset, clock) + begin + if reset = '1' then + dataSampled <= (others => '0'); + elsif rising_edge(clock) then + if send = '1' then + dataSampled <= data; + end if; + end if; + end process; + + ------------------------------------------------------------------------------ + -- A0 + A0 <= dataSampled(data'high); + + ------------------------------------------------------------------------------ + -- serialize data + updateData <= sclEn and scl_int; + + process (reset, clock) + begin + if reset = '1' then + dataCounter <= (others => '0'); + elsif rising_edge(clock) then + if resetDone = '1' then + if dataCounter = 0 then + if send = '1' then + dataCounter <= to_unsigned(pixelsPerColumn+1, dataCounter'length); + end if; + else + if updateData = '1' then + dataCounter <= dataCounter - 1; + end if; + end if; + end if; + end if; + end process; + + busy <= '1' when (resetDone = '0') or (dataCounter > 0) + else '0'; + chipSelect <= '1' when (dataCounter > 0) and (dataCounter < pixelsPerColumn+1) + else '0'; + + sampleData: process (reset, clock) + begin + if reset = '1' then + CS_n <= '1'; + SCL <= '1'; + SI <= '1'; + elsif rising_edge(clock) then + if chipSelect = '1' then + CS_n <= '0'; + SCL <= scl_int or not(chipSelect); + SI <= dataSampled(to_integer(dataCounter-1)); + else + CS_n <= '1'; + SCL <= '1'; + SI <= '1'; + end if; + end if; + end process sampleData; + +END ARCHITECTURE RTL; diff --git a/Libs/Lcd/hds/.hdlsidedata/_helloWorld_RTL.vhd._fpf b/Libs/Lcd/hds/.hdlsidedata/_helloWorld_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_helloWorld_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/.hdlsidedata/_helloworld_entity.vhg._fpf b/Libs/Lcd/hds/.hdlsidedata/_helloworld_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_helloworld_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/.hdlsidedata/_lcdCharacterEncoder_RTL.vhd._fpf b/Libs/Lcd/hds/.hdlsidedata/_lcdCharacterEncoder_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_lcdCharacterEncoder_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/.hdlsidedata/_lcdInitializer_RTL.vhd._fpf b/Libs/Lcd/hds/.hdlsidedata/_lcdInitializer_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_lcdInitializer_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/.hdlsidedata/_lcdSerializer_RTL.vhd._fpf b/Libs/Lcd/hds/.hdlsidedata/_lcdSerializer_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_lcdSerializer_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/.hdlsidedata/_lcdcharacterencoder_entity.vhg._fpf b/Libs/Lcd/hds/.hdlsidedata/_lcdcharacterencoder_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_lcdcharacterencoder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/.hdlsidedata/_lcdcontroller_entity.vhg._fpf b/Libs/Lcd/hds/.hdlsidedata/_lcdcontroller_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_lcdcontroller_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/.hdlsidedata/_lcdcontroller_struct.vhg._fpf b/Libs/Lcd/hds/.hdlsidedata/_lcdcontroller_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_lcdcontroller_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/.hdlsidedata/_lcdinitializer_entity.vhg._fpf b/Libs/Lcd/hds/.hdlsidedata/_lcdinitializer_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_lcdinitializer_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/.hdlsidedata/_lcdserializer_entity.vhg._fpf b/Libs/Lcd/hds/.hdlsidedata/_lcdserializer_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd/hds/.hdlsidedata/_lcdserializer_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd/hds/_helloworld._epf b/Libs/Lcd/hds/_helloworld._epf new file mode 100644 index 0000000..28e56b5 --- /dev/null +++ b/Libs/Lcd/hds/_helloworld._epf @@ -0,0 +1,3 @@ +TOP_MARKER atom 0 +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom helloWorld_RTL.vhd diff --git a/Libs/Lcd/hds/_lcdcharacterencoder._epf b/Libs/Lcd/hds/_lcdcharacterencoder._epf new file mode 100644 index 0000000..358609b --- /dev/null +++ b/Libs/Lcd/hds/_lcdcharacterencoder._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom lcdCharacterEncoder_RTL.vhd +DEFAULT_ARCHITECTURE atom Encoder diff --git a/Libs/Lcd/hds/_lcdcontroller._epf b/Libs/Lcd/hds/_lcdcontroller._epf new file mode 100644 index 0000000..e6e0541 --- /dev/null +++ b/Libs/Lcd/hds/_lcdcontroller._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lcd@controller/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Lcd/hds/_lcddemo._epf b/Libs/Lcd/hds/_lcddemo._epf new file mode 100644 index 0000000..9cb5bdd --- /dev/null +++ b/Libs/Lcd/hds/_lcddemo._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lcd@demo/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Lcd/hds/_lcdinitializer._epf b/Libs/Lcd/hds/_lcdinitializer._epf new file mode 100644 index 0000000..ffe6a0b --- /dev/null +++ b/Libs/Lcd/hds/_lcdinitializer._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom lcdInitializer_RTL.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/Libs/Lcd/hds/_lcdserializer._epf b/Libs/Lcd/hds/_lcdserializer._epf new file mode 100644 index 0000000..f147e2a --- /dev/null +++ b/Libs/Lcd/hds/_lcdserializer._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom lcdSerializer_RTL.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/Libs/Lcd/hds/hello@world/symbol.sb b/Libs/Lcd/hds/hello@world/symbol.sb new file mode 100644 index 0000000..af9df0f --- /dev/null +++ b/Libs/Lcd/hds/hello@world/symbol.sb @@ -0,0 +1,1650 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 30,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 21,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 1,0 +) +) +uid 111,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 1 +suid 2,0 +) +) +uid 113,0 +) +*16 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "ascii" +t "std_ulogic_vector" +b "(asciiBitNb-1 downto 0)" +o 3 +suid 11,0 +) +) +uid 798,0 +) +*17 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "send" +t "std_ulogic" +o 4 +suid 21,0 +) +) +uid 1608,0 +) +*18 (LogPort +port (LogicalPort +decl (Decl +n "busy" +t "std_ulogic" +o 5 +suid 29,0 +) +) +uid 2616,0 +) +*19 (LogPort +port (LogicalPort +decl (Decl +n "button" +t "std_ulogic" +o 6 +suid 30,0 +) +) +uid 2719,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 34,0 +optionalChildren [ +*20 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *21 (MRCItem +litem &1 +pos 6 +dimension 20 +) +uid 36,0 +optionalChildren [ +*22 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 37,0 +) +*23 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 38,0 +) +*24 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 39,0 +) +*25 (MRCItem +litem &14 +pos 1 +dimension 20 +uid 112,0 +) +*26 (MRCItem +litem &15 +pos 0 +dimension 20 +uid 114,0 +) +*27 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 797,0 +) +*28 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 1607,0 +) +*29 (MRCItem +litem &18 +pos 4 +dimension 20 +uid 2615,0 +) +*30 (MRCItem +litem &19 +pos 5 +dimension 20 +uid 2720,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 40,0 +optionalChildren [ +*31 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 41,0 +) +*32 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 42,0 +) +*33 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 43,0 +) +*34 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 44,0 +) +*35 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 45,0 +) +*36 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 46,0 +) +*37 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 47,0 +) +*38 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 48,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 35,0 +vaOverrides [ +] +) +] +) +uid 20,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *39 (LEmptyRow +) +uid 50,0 +optionalChildren [ +*40 (RefLabelRowHdr +) +*41 (TitleRowHdr +) +*42 (FilterRowHdr +) +*43 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*44 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*45 (GroupColHdr +tm "GroupColHdrMgr" +) +*46 (NameColHdr +tm "GenericNameColHdrMgr" +) +*47 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*48 (InitColHdr +tm "GenericValueColHdrMgr" +) +*49 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*50 (EolColHdr +tm "GenericEolColHdrMgr" +) +*51 (LogGeneric +generic (GiElement +name "asciiBitNb" +type "positive" +value "7" +) +uid 805,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 62,0 +optionalChildren [ +*52 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *53 (MRCItem +litem &39 +pos 1 +dimension 20 +) +uid 64,0 +optionalChildren [ +*54 (MRCItem +litem &40 +pos 0 +dimension 20 +uid 65,0 +) +*55 (MRCItem +litem &41 +pos 1 +dimension 23 +uid 66,0 +) +*56 (MRCItem +litem &42 +pos 2 +hidden 1 +dimension 20 +uid 67,0 +) +*57 (MRCItem +litem &51 +pos 0 +dimension 20 +uid 804,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 68,0 +optionalChildren [ +*58 (MRCItem +litem &43 +pos 0 +dimension 20 +uid 69,0 +) +*59 (MRCItem +litem &45 +pos 1 +dimension 50 +uid 70,0 +) +*60 (MRCItem +litem &46 +pos 2 +dimension 100 +uid 71,0 +) +*61 (MRCItem +litem &47 +pos 3 +dimension 100 +uid 72,0 +) +*62 (MRCItem +litem &48 +pos 4 +dimension 50 +uid 73,0 +) +*63 (MRCItem +litem &49 +pos 5 +dimension 50 +uid 74,0 +) +*64 (MRCItem +litem &50 +pos 6 +dimension 80 +uid 75,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 63,0 +vaOverrides [ +] +) +] +) +uid 49,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "d:\\Workspaces\\svn\\eda\\VHDL\\ELN_board\\..\\Libs\\Lcd\\hdl" +) +(vvPair +variable "HDSDir" +value "d:\\Workspaces\\svn\\eda\\VHDL\\ELN_board\\..\\Libs\\Lcd\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "d:\\Workspaces\\svn\\eda\\VHDL\\ELN_board\\..\\Libs\\Lcd\\hds\\hello@world\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "d:\\Workspaces\\svn\\eda\\VHDL\\ELN_board\\..\\Libs\\Lcd\\hds\\hello@world\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "d:\\Workspaces\\svn\\eda\\VHDL\\ELN_board\\..\\Libs\\Lcd\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "concat" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "d:\\Workspaces\\svn\\eda\\VHDL\\ELN_board\\..\\Libs\\Lcd\\hds\\hello@world" +) +(vvPair +variable "d_logical" +value "d:\\Workspaces\\svn\\eda\\VHDL\\ELN_board\\..\\Libs\\Lcd\\hds\\helloWorld" +) +(vvPair +variable "date" +value "22.08.2013" +) +(vvPair +variable "day" +value "Do" +) +(vvPair +variable "day_long" +value "Donnerstag" +) +(vvPair +variable "dd" +value "22" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "helloWorld" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE3877" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Lcd" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../libs/SPI/concat" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../libs/SPI/designcheck" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/$DESIGN_NAME/Lcd/work" +) +(vvPair +variable "mm" +value "08" +) +(vvPair +variable "module_name" +value "helloWorld" +) +(vvPair +variable "month" +value "Aug" +) +(vvPair +variable "month_long" +value "August" +) +(vvPair +variable "p" +value "d:\\Workspaces\\svn\\eda\\VHDL\\ELN_board\\..\\Libs\\Lcd\\hds\\hello@world\\symbol.sb" +) +(vvPair +variable "p_logical" +value "d:\\Workspaces\\svn\\eda\\VHDL\\ELN_board\\..\\Libs\\Lcd\\hds\\helloWorld\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "16:01:40" +) +(vvPair +variable "unit" +value "helloWorld" +) +(vvPair +variable "user" +value "uadmin" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2013" +) +(vvPair +variable "yy" +value "13" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 19,0 +optionalChildren [ +*65 (SymbolBody +uid 8,0 +optionalChildren [ +*66 (CptPort +uid 76,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 77,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "7250,23625,8000,24375" +) +tg (CPTG +uid 78,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 79,0 +va (VaSet +font "Verdana,9,0" +) +xt "9000,23400,12400,24600" +st "clock" +blo "9000,24400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 80,0 +va (VaSet +font "Courier New,8,0" +) +xt "-28000,8600,-12000,9400" +st "clock : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 1,0 +) +) +) +*67 (CptPort +uid 81,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 82,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "7250,25625,8000,26375" +) +tg (CPTG +uid 83,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 84,0 +va (VaSet +font "Verdana,9,0" +) +xt "9000,25400,12300,26600" +st "reset" +blo "9000,26400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 85,0 +va (VaSet +font "Courier New,8,0" +) +xt "-28000,7800,-12000,8600" +st "reset : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 1 +suid 2,0 +) +) +) +*68 (CptPort +uid 799,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2744,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24000,19625,24750,20375" +) +tg (CPTG +uid 801,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 802,0 +va (VaSet +font "Verdana,9,0" +) +xt "19900,19400,23000,20600" +st "ascii" +ju 2 +blo "23000,20400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 803,0 +va (VaSet +font "Courier New,8,0" +) +xt "-28000,9400,3500,10200" +st "ascii : OUT std_ulogic_vector (asciiBitNb-1 downto 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ascii" +t "std_ulogic_vector" +b "(asciiBitNb-1 downto 0)" +o 3 +suid 11,0 +) +) +) +*69 (CptPort +uid 1611,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2745,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24000,21625,24750,22375" +) +tg (CPTG +uid 1613,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1614,0 +va (VaSet +font "Verdana,9,0" +) +xt "19900,21400,23000,22600" +st "send" +ju 2 +blo "23000,22400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1615,0 +va (VaSet +font "Courier New,8,0" +) +xt "-28000,10200,-12000,11000" +st "send : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "send" +t "std_ulogic" +o 4 +suid 21,0 +) +) +) +*70 (CptPort +uid 2617,0 +ps "OnEdgeStrategy" +shape (Triangle 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"-28000,11800,-13000,12600" +st "button : IN std_ulogic " +) +thePort (LogicalPort +decl (Decl +n "button" +t "std_ulogic" +o 6 +suid 30,0 +) +) +) +] +shape (Rectangle +uid 148,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "8000,16000,24000,28000" +) +oxt "15000,6000,33000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Verdana,9,1" +) +xt "8600,27800,10900,29000" +st "Lcd" +blo "8600,28800" +) +second (Text +uid 12,0 +va (VaSet +font "Verdana,9,1" +) +xt "8600,29000,15200,30200" +st "helloWorld" +blo "8600,30000" +) +) +gi *72 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "8000,31800,21000,34200" +st "Generic Declarations + +asciiBitNb positive 7 +" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "asciiBitNb" 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+pts [ +"40000,23000" +"40500,23000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6738,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6739,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "43000,22300,46500,23600" +st "RST_n" +blo "43000,23300" +tm "WireNameMgr" +) +) +) +*18 (Net +uid 6748,0 +decl (Decl +n "SI" +t "std_ulogic" +o 2 +suid 121,0 +) +declText (MLText +uid 6749,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,57300,-63700,58300" +st "SI : std_ulogic +" +) +) +*19 (Net +uid 6750,0 +decl (Decl +n "SCL" +t "std_ulogic" +o 3 +suid 122,0 +) +declText (MLText +uid 6751,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,58300,-63300,59300" +st "SCL : std_ulogic +" +) +) +*20 (Net +uid 6752,0 +decl (Decl +n "A0" +t "std_ulogic" +o 4 +suid 123,0 +) +declText (MLText +uid 6753,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,59300,-63500,60300" +st "A0 : std_ulogic +" +) +) +*21 (Net +uid 7909,0 +decl (Decl +n "clock" +t "std_ulogic" +o 7 +suid 139,0 +) +declText (MLText +uid 7910,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,62300,-63400,63300" +st "clock : std_ulogic +" +) +) +*22 (PortIoIn +uid 8031,0 +shape (CompositeShape +uid 8032,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 8033,0 +sl 0 +ro 270 +xt "-58000,16625,-56500,17375" +) +(Line +uid 8034,0 +sl 0 +ro 270 +xt "-56500,17000,-56000,17000" +pts [ +"-56500,17000" +"-56000,17000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 8035,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8036,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-62500,16300,-59000,17600" +st "ascii" +ju 2 +blo "-59000,17300" +tm "WireNameMgr" +) +) +) +*23 (Net +uid 8170,0 +decl (Decl +n "ascii" +t "std_ulogic_vector" +b "(asciiBitNb-1 downto 0)" +o 8 +suid 158,0 +) +declText (MLText +uid 8171,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,63300,-50600,64300" +st "ascii : std_ulogic_vector(asciiBitNb-1 downto 0) +" +) +) +*24 (PortIoOut +uid 9321,0 +shape (CompositeShape +uid 9322,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 9323,0 +sl 0 +ro 90 +xt "-58000,20625,-56500,21375" +) +(Line +uid 9324,0 +sl 0 +ro 90 +xt "-56500,21000,-56000,21000" +pts [ +"-56000,21000" +"-56500,21000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 9325,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9326,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-61800,20300,-59000,21600" +st "busy" +ju 2 +blo "-59000,21300" +tm "WireNameMgr" +) +) +) +*25 (PortIoIn +uid 9455,0 +shape (CompositeShape +uid 9456,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 9457,0 +sl 0 +ro 270 +xt "-58000,18625,-56500,19375" +) +(Line +uid 9458,0 +sl 0 +ro 270 +xt "-56500,19000,-56000,19000" +pts [ +"-56500,19000" +"-56000,19000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 9459,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9460,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-61800,18300,-59000,19600" +st "send" +ju 2 +blo "-59000,19300" +tm "WireNameMgr" +) +) +) +*26 (Net +uid 9467,0 +decl (Decl +n "send" +t "std_ulogic" +o 9 +suid 176,0 +) +declText (MLText +uid 9468,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,64300,-63200,65300" +st "send : std_ulogic +" +) +) +*27 (Net +uid 9948,0 +decl (Decl +n "CS1_n" +t "std_ulogic" +o 5 +suid 182,0 +) +declText (MLText +uid 9949,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,60300,-62800,61300" +st "CS1_n : std_ulogic +" +) +) +*28 (Net +uid 9950,0 +decl (Decl +n "RST_n" +t "std_ulogic" +o 6 +suid 183,0 +) +declText (MLText +uid 9951,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,61300,-62800,62300" +st "RST_n : std_ulogic +" +) +) +*29 (PortIoIn +uid 10651,0 +shape (CompositeShape +uid 10652,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 10653,0 +sl 0 +ro 270 +xt "-58000,24625,-56500,25375" +) +(Line +uid 10654,0 +sl 0 +ro 270 +xt "-56500,25000,-56000,25000" +pts [ +"-56500,25000" +"-56000,25000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 10655,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10656,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-62500,24300,-59000,25600" +st "clock" +ju 2 +blo "-59000,25300" +tm "WireNameMgr" +) +) +) +*30 (PortIoIn +uid 10657,0 +shape (CompositeShape +uid 10658,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 10659,0 +sl 0 +ro 270 +xt "-58000,26625,-56500,27375" +) +(Line +uid 10660,0 +sl 0 +ro 270 +xt "-56500,27000,-56000,27000" +pts [ +"-56500,27000" +"-56000,27000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 10661,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10662,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-62500,26300,-59000,27600" +st "reset" +ju 2 +blo "-59000,27300" +tm "WireNameMgr" +) +) +) +*31 (Net +uid 11116,0 +decl (Decl +n "lcdData" +t "std_ulogic_vector" +b "(9-1 DOWNTO 0)" +o 11 +suid 187,0 +) +declText (MLText +uid 11117,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,75100,-49300,76100" +st "SIGNAL lcdData : std_ulogic_vector(9-1 DOWNTO 0) +" +) +) +*32 (Net +uid 11118,0 +decl (Decl +n "lcdSend" +t "std_ulogic" +o 12 +suid 188,0 +) +declText (MLText +uid 11119,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,76100,-59700,77100" +st "SIGNAL lcdSend : std_ulogic +" +) +) +*33 (Net +uid 11124,0 +decl (Decl +n "lcdBusy" +t "std_ulogic" +o 13 +suid 189,0 +) +declText (MLText +uid 11125,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,77100,-59800,78100" +st "SIGNAL lcdBusy : std_ulogic +" +) +) +*34 (Net +uid 11273,0 +decl (Decl +n "lcdData1" +t "std_ulogic_vector" +b "(lcdDataBitNb-1 downto 0)" +o 14 +suid 190,0 +) +declText (MLText +uid 11274,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,78100,-45200,79100" +st "SIGNAL lcdData1 : std_ulogic_vector(lcdDataBitNb-1 downto 0) +" +) +) +*35 (Net +uid 11279,0 +decl (Decl +n "lcdSend1" +t "std_ulogic" +o 15 +suid 191,0 +) +declText (MLText +uid 11280,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,79100,-59500,80100" +st "SIGNAL lcdSend1 : std_ulogic +" +) +) +*36 (Net +uid 11285,0 +decl (Decl +n "lcdBusy1" +t "std_ulogic" +o 16 +suid 192,0 +) +declText (MLText +uid 11286,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,80100,-59600,81100" +st "SIGNAL lcdBusy1 : std_ulogic +" +) +) +*37 (Net +uid 11291,0 +decl (Decl +n "busy" +t "std_ulogic" +o 10 +suid 193,0 +) +declText (MLText +uid 11292,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,65300,-63200,66300" +st "busy : std_ulogic +" +) +) +*38 (Net +uid 11446,0 +lang 11 +decl (Decl +n "dataInA" +t "std_ulogic_vector" +b "(characterPixelNb-1 DOWNTO 0)" +o 17 +suid 194,0 +) +declText (MLText +uid 11447,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,81100,-43000,82100" +st "SIGNAL dataInA : std_ulogic_vector(characterPixelNb-1 DOWNTO 0) +" +) +) +*39 (Net +uid 11454,0 +lang 11 +decl (Decl +n "addressB" +t "std_ulogic_vector" +b "(asciiBitNb-1 DOWNTO 0)" +o 18 +suid 195,0 +) +declText (MLText +uid 11455,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,82100,-45700,83100" +st "SIGNAL addressB : std_ulogic_vector(asciiBitNb-1 DOWNTO 0) +" +) +) +*40 (Net +uid 11462,0 +lang 11 +decl (Decl +n "dataInB" +t "std_ulogic_vector" +b "(characterPixelNb-1 DOWNTO 0)" +o 19 +suid 196,0 +) +declText (MLText +uid 11463,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,83100,-43000,84100" +st "SIGNAL dataInB : std_ulogic_vector(characterPixelNb-1 DOWNTO 0) +" +) +) +*41 (Net +uid 11470,0 +lang 11 +decl (Decl +n "writeEnB" +t "std_ulogic" +o 20 +suid 197,0 +) +declText (MLText +uid 11471,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,84100,-59600,85100" +st "SIGNAL writeEnB : std_ulogic +" +) +) +*42 (Net +uid 11478,0 +lang 11 +decl (Decl +n "enB" +t "std_ulogic" +o 21 +suid 198,0 +) +declText (MLText +uid 11479,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,85100,-60100,86100" +st "SIGNAL enB : std_ulogic +" +) +) +*43 (Net +uid 11486,0 +lang 11 +decl (Decl +n "clockB" +t "std_ulogic" +o 22 +suid 199,0 +) +declText (MLText +uid 11487,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,86100,-60000,87100" +st "SIGNAL clockB : std_ulogic +" +) +) +*44 (Net +uid 11494,0 +lang 11 +decl (Decl +n "enA" +t "std_ulogic" +o 23 +suid 200,0 +) +declText (MLText +uid 11495,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,87100,-60100,88100" +st "SIGNAL enA : std_ulogic +" +) +) +*45 (Net +uid 11502,0 +lang 11 +decl (Decl +n "writeEnA" +t "std_ulogic" +o 24 +suid 201,0 +) +declText (MLText +uid 11503,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,88100,-59600,89100" +st "SIGNAL writeEnA : std_ulogic +" +) +) +*46 (Net +uid 11665,0 +lang 11 +decl (Decl +n "pixelData" +t "std_ulogic_vector" +b "(characterPixelNb-1 DOWNTO 0)" +posAdd 0 +o 25 +suid 203,0 +) +declText (MLText +uid 11666,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,89100,-42900,90100" +st "SIGNAL pixelData : std_ulogic_vector(characterPixelNb-1 DOWNTO 0) +" +) +) +*47 (HdlText +uid 11667,0 +optionalChildren [ +*48 (EmbeddedText +uid 11714,0 +commentText (CommentText +uid 11715,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 11716,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "16000,38000,32000,54000" +) +oxt "0,0,18000,5000" +text (MLText +uid 11717,0 +va (VaSet +font "Courier,9,0" +) +xt "16200,38200,30600,53800" +st " +addressB <= (others => '0'); +dataInA <= (others => '0'); +dataInB <= (others => '0'); +enA <= '1'; +enB <= '0'; +writeEnA <= '0'; +writeEnB <= '0'; +clockB <= '0'; + + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 16000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 11668,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "16000,37000,32000,55000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 11669,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*49 (Text +uid 11670,0 +va (VaSet +font "Verdana,9,1" +) +xt "16400,55000,17900,55900" +st "eb1" +blo "16400,55700" +tm "HdlTextNameMgr" +) +*50 (Text +uid 11671,0 +va (VaSet +font "Verdana,9,1" +) +xt "16400,56200,16900,57100" +st "1" +blo "16400,56900" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 11850,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "16250,53250,17750,54750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*51 (SaComponent +uid 12026,0 +optionalChildren [ +*52 (CptPort +uid 11978,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11979,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-16750,52625,-16000,53375" +) +tg (CPTG +uid 11980,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11981,0 +va (VaSet +) +xt "-15000,52500,-11400,53500" +st "clockA" +blo "-15000,53300" +) +) +thePort (LogicalPort +lang 10 +decl (Decl +n "clockA" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*53 (CptPort +uid 11982,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11983,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-16750,50625,-16000,51375" +) +tg (CPTG +uid 11984,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11985,0 +va (VaSet +) +xt "-15000,50500,-13200,51500" +st "enA" +blo "-15000,51300" +) +) +thePort (LogicalPort +lang 10 +decl (Decl +n "enA" +t "std_ulogic" +o 2 +suid 3,0 +) +) +) +*54 (CptPort +uid 11986,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11987,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-16750,46625,-16000,47375" +) +tg (CPTG +uid 11988,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11989,0 +va (VaSet +) +xt "-15000,46500,-10200,47500" +st "writeEnA" +blo "-15000,47300" +) +) +thePort (LogicalPort +lang 10 +decl (Decl +n "writeEnA" +t "std_ulogic" +o 3 +suid 4,0 +) +) +) +*55 (CptPort +uid 11990,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11991,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-16750,40625,-16000,41375" +) +tg (CPTG +uid 11992,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11993,0 +va (VaSet +) +xt "-15000,40500,-10200,41500" +st "addressA" +blo "-15000,41300" +) +) +thePort (LogicalPort +lang 10 +decl (Decl +n "addressA" +t "std_ulogic_vector" +b "(addressBitNb-1 DOWNTO 0)" +o 4 +suid 5,0 +) +) +) +*56 (CptPort +uid 11994,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11995,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-16750,44625,-16000,45375" +) +tg (CPTG +uid 11996,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11997,0 +va (VaSet +) +xt "-15000,44500,-10800,45500" +st "dataInA" +blo "-15000,45300" +) +) +thePort (LogicalPort +lang 10 +decl (Decl +n "dataInA" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 5 +suid 6,0 +) +) +) +*57 (CptPort +uid 11998,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11999,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-16750,42625,-16000,43375" +) +tg (CPTG +uid 12000,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12001,0 +va (VaSet +) +xt "-15000,42500,-10200,43500" +st "dataOutA" +blo "-15000,43300" +) +) +thePort (LogicalPort +lang 10 +m 1 +decl (Decl +n "dataOutA" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +posAdd 0 +o 6 +suid 7,0 +) +) +) +*58 (CptPort +uid 12002,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12003,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,52625,750,53375" +) +tg (CPTG +uid 12004,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12005,0 +va (VaSet +) +xt "-4600,52500,-1000,53500" +st "clockB" +ju 2 +blo "-1000,53300" +) +) +thePort (LogicalPort +lang 10 +decl (Decl +n "clockB" +t "std_ulogic" +o 7 +suid 8,0 +) +) +) +*59 (CptPort +uid 12006,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12007,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,50625,750,51375" +) +tg (CPTG +uid 12008,0 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0 +sf 1 +si 0 +tg (WTG +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,0,3400,1400" +st "sig0" +blo "0,1200" +tm "WireNameMgr" +) +) +) +defaultBus (Wire +shape (OrthoPolyLine +va (VaSet +vasetType 3 +lineWidth 2 +) +pts [ +"0,0" +"0,0" +] +) +ss 0 +es 0 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,0,4700,1400" +st "dbus0" +blo "0,1200" +tm "WireNameMgr" +) +) +) +defaultBundle (Bundle +shape (OrthoPolyLine +va (VaSet +vasetType 3 +lineColor "32768,0,0" +lineWidth 2 +) +pts [ +"0,0" +"0,0" +] +) +ss 0 +es 0 +sat 32 +eat 32 +textGroup (BiTextGroup +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +) +xt "0,-200,4700,1000" +st "bundle0" +blo "0,800" +tm "BundleNameMgr" +) +second (MLText +va (VaSet +) +xt "0,1000,1500,2200" +st "()" +tm "BundleContentsMgr" +) +) +bundleNet &0 +) +defaultPortMapFrame (PortMapFrame +ps "PortMapFrameStrategy" +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "0,0,10000,12000" +) +portMapText (BiTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +first (MLText +va (VaSet +) +xt "0,0,5000,1200" +st "Auto list" +) +second (MLText +va (VaSet +) +xt "0,1200,9600,2400" +st "User defined list" +tm "PortMapTextMgr" +) +) +) +defaultGenFrame (Frame +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "26368,26368,26368" +lineStyle 2 +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (MLText +va (VaSet +) +xt "-2950,-1200,15550,0" +st "g0: FOR i IN 0 TO n GENERATE" +tm "FrameTitleTextMgr" +) +) +seqNum (FrameSequenceNumber +ps "TopLeftStrategy" +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "50,50,1050,1450" +) +num (Text +va (VaSet +) +xt "-150,150,1250,1350" +st "1" +blo "-150,1150" +tm "FrameSeqNumMgr" +) +) +decls (MlTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*173 (Text +va (VaSet +font "Verdana,9,1" +) +xt "14100,20000,24900,21200" +st "Frame Declarations" +blo "14100,21000" +) +*174 (MLText +va (VaSet +) +xt "14100,21200,14100,21200" +tm "BdFrameDeclTextMgr" +) +] +) +) +defaultBlockFrame (Frame +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "26368,26368,26368" +lineStyle 1 +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (MLText +va (VaSet +) +xt "-1800,-1200,9200,0" +st "b0: BLOCK (guard)" +tm "FrameTitleTextMgr" +) +) +seqNum (FrameSequenceNumber +ps "TopLeftStrategy" +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "50,50,1050,1450" +) +num (Text +va (VaSet +) +xt "-150,150,1250,1350" +st "1" +blo "-150,1150" +tm "FrameSeqNumMgr" +) +) +decls (MlTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*175 (Text +va (VaSet +font "Verdana,9,1" +) +xt "14100,20000,24900,21200" +st "Frame Declarations" +blo "14100,21000" +) +*176 (MLText +va (VaSet +) +xt "14100,21200,14100,21200" +tm "BdFrameDeclTextMgr" +) +] +) +style 3 +) +defaultSaCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1950" +st "Port" +blo "0,1750" +) +) +thePort (LogicalPort +decl (Decl +n "Port" +t "" +o 0 +) +) +) +defaultSaCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1950" +st "Port" +blo "0,1750" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Port" +t "" +o 0 +) +) +) +defaultDeclText (MLText +va (VaSet +font "Verdana,8,0" +) +) +archDeclarativeBlock (BdArchDeclBlock +uid 1,0 +stg "BdArchDeclBlockLS" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,8,1" +) +xt "-76000,54500,-69500,55400" +st "Declarations" +blo "-76000,55200" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,8,1" +) +xt "-76000,55400,-73000,56300" +st "Ports:" +blo "-76000,56100" +) +preUserLabel (Text +uid 4,0 +va (VaSet +font "Verdana,8,1" +) +xt "-76000,66300,-71500,67200" +st "Pre User:" +blo "-76000,67000" +) +preUserText (MLText +uid 5,0 +va (VaSet +font "Verdana,8,0" +) +xt "-74000,67200,-44900,74200" +st "constant fontColumnNb: positive := 6; +constant fontRowNb: positive := 8; +constant characterPixelNb: positive := fontColumnNb*fontRowNb; + +constant lcdDataBitNb: positive := 8+1; +constant lcdPageNb: positive := 4; +constant lcdColumnNb: positive := 132;" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +font "Verdana,8,1" +) +xt "-76000,74200,-67500,75100" +st "Diagram Signals:" +blo "-76000,74900" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "-76000,54500,-70500,55400" +st "Post User:" +blo "-76000,55200" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "-76000,54500,-76000,54500" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 205,0 +usingSuid 1 +emptyRow *177 (LEmptyRow +) +uid 1151,0 +optionalChildren [ +*178 (RefLabelRowHdr +) +*179 (TitleRowHdr +) +*180 (FilterRowHdr +) +*181 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*182 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*183 (GroupColHdr +tm "GroupColHdrMgr" +) +*184 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*185 (ModeColHdr +tm "BlockDiagramModeColHdrMgr" +) +*186 (TypeColHdr +tm "BlockDiagramTypeColHdrMgr" +) +*187 (BoundsColHdr +tm "BlockDiagramBoundsColHdrMgr" +) +*188 (InitColHdr +tm "BlockDiagramInitColHdrMgr" +) +*189 (EolColHdr +tm "BlockDiagramEolColHdrMgr" +) +*190 (LeafLogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 1 +suid 115,0 +) +) +uid 6784,0 +) +*191 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "SI" +t "std_ulogic" +o 2 +suid 121,0 +) +) +uid 6786,0 +) +*192 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "SCL" +t "std_ulogic" +o 3 +suid 122,0 +) +) +uid 6788,0 +) +*193 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "A0" +t "std_ulogic" +o 4 +suid 123,0 +) +) +uid 6790,0 +) +*194 (LeafLogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 7 +suid 139,0 +) +) +uid 7915,0 +) +*195 (LeafLogPort +port (LogicalPort +decl (Decl +n "ascii" +t "std_ulogic_vector" +b "(asciiBitNb-1 downto 0)" +o 8 +suid 158,0 +) +) +uid 8176,0 +) +*196 (LeafLogPort +port (LogicalPort +decl (Decl +n "send" +t "std_ulogic" +o 9 +suid 176,0 +) +) +uid 9479,0 +) +*197 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "CS1_n" +t "std_ulogic" +o 5 +suid 182,0 +) +) +uid 9952,0 +) +*198 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "RST_n" +t "std_ulogic" +o 6 +suid 183,0 +) +) +uid 9954,0 +) +*199 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "lcdData" +t "std_ulogic_vector" +b "(9-1 DOWNTO 0)" +o 11 +suid 187,0 +) +) +uid 11293,0 +) +*200 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "lcdSend" +t "std_ulogic" +o 12 +suid 188,0 +) +) +uid 11295,0 +) +*201 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "lcdBusy" +t "std_ulogic" +o 13 +suid 189,0 +) +) +uid 11297,0 +) +*202 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "lcdData1" +t "std_ulogic_vector" +b "(lcdDataBitNb-1 downto 0)" +o 14 +suid 190,0 +) +) +uid 11299,0 +) +*203 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "lcdSend1" +t "std_ulogic" +o 15 +suid 191,0 +) +) +uid 11301,0 +) +*204 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "lcdBusy1" +t "std_ulogic" +o 16 +suid 192,0 +) +) +uid 11303,0 +) +*205 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "busy" +t "std_ulogic" +o 10 +suid 193,0 +) +) +uid 11305,0 +) +*206 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "dataInA" +t "std_ulogic_vector" +b "(characterPixelNb-1 DOWNTO 0)" +o 17 +suid 194,0 +) +) +uid 11696,0 +) +*207 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "addressB" +t "std_ulogic_vector" +b "(asciiBitNb-1 DOWNTO 0)" +o 18 +suid 195,0 +) +) +uid 11698,0 +) +*208 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "dataInB" +t "std_ulogic_vector" +b "(characterPixelNb-1 DOWNTO 0)" +o 19 +suid 196,0 +) +) +uid 11700,0 +) +*209 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "writeEnB" +t "std_ulogic" +o 20 +suid 197,0 +) +) +uid 11702,0 +) +*210 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "enB" +t "std_ulogic" +o 21 +suid 198,0 +) +) +uid 11704,0 +) +*211 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "clockB" +t "std_ulogic" +o 22 +suid 199,0 +) +) +uid 11706,0 +) +*212 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "enA" +t "std_ulogic" +o 23 +suid 200,0 +) +) +uid 11708,0 +) +*213 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "writeEnA" +t "std_ulogic" +o 24 +suid 201,0 +) +) +uid 11710,0 +) +*214 (LeafLogPort +port (LogicalPort +lang 10 +m 4 +decl (Decl +n "pixelData" +t "std_ulogic_vector" +b "(characterPixelNb-1 DOWNTO 0)" +posAdd 0 +o 25 +suid 203,0 +) +) +uid 11712,0 +) +*215 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "clearDisplay" +t "std_ulogic" +o 26 +suid 204,0 +) +) +uid 12585,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 1164,0 +optionalChildren [ +*216 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *217 (MRCItem +litem &177 +pos 26 +dimension 20 +) +uid 1166,0 +optionalChildren [ +*218 (MRCItem +litem &178 +pos 0 +dimension 20 +uid 1167,0 +) +*219 (MRCItem +litem &179 +pos 1 +dimension 23 +uid 1168,0 +) +*220 (MRCItem +litem &180 +pos 2 +hidden 1 +dimension 20 +uid 1169,0 +) +*221 (MRCItem +litem &190 +pos 0 +dimension 20 +uid 6785,0 +) +*222 (MRCItem +litem &191 +pos 1 +dimension 20 +uid 6787,0 +) +*223 (MRCItem +litem &192 +pos 2 +dimension 20 +uid 6789,0 +) +*224 (MRCItem +litem &193 +pos 3 +dimension 20 +uid 6791,0 +) +*225 (MRCItem +litem &194 +pos 4 +dimension 20 +uid 7916,0 +) +*226 (MRCItem +litem &195 +pos 5 +dimension 20 +uid 8177,0 +) +*227 (MRCItem +litem &196 +pos 6 +dimension 20 +uid 9480,0 +) +*228 (MRCItem +litem &197 +pos 7 +dimension 20 +uid 9953,0 +) +*229 (MRCItem +litem &198 +pos 8 +dimension 20 +uid 9955,0 +) +*230 (MRCItem +litem &199 +pos 10 +dimension 20 +uid 11294,0 +) +*231 (MRCItem +litem &200 +pos 11 +dimension 20 +uid 11296,0 +) +*232 (MRCItem +litem &201 +pos 12 +dimension 20 +uid 11298,0 +) +*233 (MRCItem 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+textAngle 90 +) +uid 1170,0 +optionalChildren [ +*247 (MRCItem +litem &181 +pos 0 +dimension 20 +uid 1171,0 +) +*248 (MRCItem +litem &183 +pos 1 +dimension 50 +uid 1172,0 +) +*249 (MRCItem +litem &184 +pos 2 +dimension 100 +uid 1173,0 +) +*250 (MRCItem +litem &185 +pos 3 +dimension 50 +uid 1174,0 +) +*251 (MRCItem +litem &186 +pos 4 +dimension 100 +uid 1175,0 +) +*252 (MRCItem +litem &187 +pos 5 +dimension 100 +uid 1176,0 +) +*253 (MRCItem +litem &188 +pos 6 +dimension 50 +uid 1177,0 +) +*254 (MRCItem +litem &189 +pos 7 +dimension 80 +uid 1178,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 1165,0 +vaOverrides [ +] +) +] +) +uid 1150,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *255 (LEmptyRow +) +uid 1180,0 +optionalChildren [ +*256 (RefLabelRowHdr +) +*257 (TitleRowHdr +) +*258 (FilterRowHdr +) +*259 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*260 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*261 (GroupColHdr +tm "GroupColHdrMgr" +) +*262 (NameColHdr +tm "GenericNameColHdrMgr" +) +*263 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*264 (InitColHdr +tm "GenericValueColHdrMgr" +) +*265 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*266 (EolColHdr +tm "GenericEolColHdrMgr" +) +*267 (LogGeneric +generic (GiElement +name "asciiBitNb" +type "positive" +value "7" +) +uid 8178,0 +) +*268 (LogGeneric +generic (GiElement +name "baudRateDivide" +type "integer" +value "2" +) +uid 10994,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 1192,0 +optionalChildren [ +*269 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *270 (MRCItem +litem &255 +pos 2 +dimension 20 +) +uid 1194,0 +optionalChildren [ +*271 (MRCItem +litem &256 +pos 0 +dimension 20 +uid 1195,0 +) +*272 (MRCItem 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+vasetType 1 +fg "65280,65280,46080" +) +xt "10000,23000,14000,24000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 34,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "10200,23500,10200,23500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +uid 35,0 +shape (Rectangle +uid 36,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "10000,24000,14000,25000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 37,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "10200,24500,10200,24500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*11 (CommentText +uid 38,0 +shape (Rectangle +uid 39,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,23000,31000,24000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 40,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "14200,23500,14200,23500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 10,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "10000,20000,51000,25000" +) +oxt "14000,66000,55000,71000" +) +*12 (Net +uid 6676,0 +decl (Decl +n "reset" +t "std_ulogic" +o 1 +suid 115,0 +) +declText (MLText +uid 6677,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-65600,-85300,-64600" +st "reset : std_ulogic" +) +) +*13 (PortIoOut +uid 6678,0 +shape (CompositeShape +uid 6679,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6680,0 +sl 0 +ro 270 +xt "14500,-16375,16000,-15625" +) +(Line +uid 6681,0 +sl 0 +ro 270 +xt "14000,-16000,14500,-16000" +pts [ +"14000,-16000" +"14500,-16000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6682,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6683,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "17000,-16700,18400,-15400" +st "SI" +blo "17000,-15700" +tm "WireNameMgr" +) +) +) +*14 (PortIoOut +uid 6684,0 +shape (CompositeShape +uid 6685,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6686,0 +sl 0 +ro 270 +xt "14500,-14375,16000,-13625" +) +(Line +uid 6687,0 +sl 0 +ro 270 +xt "14000,-14000,14500,-14000" +pts [ +"14000,-14000" +"14500,-14000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6688,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6689,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "17000,-14700,19100,-13400" +st "SCL" +blo "17000,-13700" +tm "WireNameMgr" +) +) +) +*15 (PortIoOut +uid 6690,0 +shape (CompositeShape +uid 6691,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6692,0 +sl 0 +ro 270 +xt "14500,-12375,16000,-11625" +) +(Line +uid 6693,0 +sl 0 +ro 270 +xt "14000,-12000,14500,-12000" +pts [ +"14000,-12000" +"14500,-12000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6694,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6695,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "17000,-12700,18400,-11400" +st "A0" +blo "17000,-11700" +tm "WireNameMgr" +) +) +) +*16 (PortIoOut +uid 6696,0 +shape (CompositeShape +uid 6697,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6698,0 +sl 0 +ro 270 +xt "14500,-8375,16000,-7625" +) +(Line +uid 6699,0 +sl 0 +ro 270 +xt "14000,-8000,14500,-8000" +pts [ +"14000,-8000" +"14500,-8000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6700,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6701,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "17000,-8700,20500,-7400" +st "CS1_n" +blo "17000,-7700" +tm "WireNameMgr" +) +) +) +*17 (PortIoOut +uid 6734,0 +shape (CompositeShape +uid 6735,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 6736,0 +sl 0 +ro 270 +xt "14500,-10375,16000,-9625" +) +(Line +uid 6737,0 +sl 0 +ro 270 +xt "14000,-10000,14500,-10000" +pts [ +"14000,-10000" +"14500,-10000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 6738,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6739,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "17000,-10700,20500,-9400" +st "RST_n" +blo "17000,-9700" +tm "WireNameMgr" +) +) +) +*18 (Net +uid 6748,0 +decl (Decl +n "SI" +t "std_ulogic" +o 2 +suid 121,0 +) +declText (MLText +uid 6749,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-64700,-85600,-63700" +st "SI : std_ulogic" +) +) +*19 (Net +uid 6750,0 +decl (Decl +n "SCL" +t "std_ulogic" +o 3 +suid 122,0 +) +declText (MLText +uid 6751,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-63800,-85200,-62800" +st "SCL : std_ulogic" +) +) +*20 (Net +uid 6752,0 +decl (Decl +n "A0" +t "std_ulogic" +o 4 +suid 123,0 +) +declText (MLText +uid 6753,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-62900,-85400,-61900" +st "A0 : std_ulogic" +) +) +*21 (Net +uid 7909,0 +decl (Decl +n "clock" +t "std_ulogic" +o 7 +suid 139,0 +) +declText (MLText +uid 7910,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-60200,-85300,-59200" +st "clock : std_ulogic" +) +) +*22 (Net +uid 9948,0 +decl (Decl +n "CS1_n" +t "std_ulogic" +o 5 +suid 182,0 +) +declText (MLText +uid 9949,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-62000,-84700,-61000" +st "CS1_n : std_ulogic" +) +) +*23 (Net +uid 9950,0 +decl (Decl +n "RST_n" +t "std_ulogic" +o 6 +suid 183,0 +) +declText (MLText +uid 9951,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-61100,-84700,-60100" +st "RST_n : std_ulogic" +) +) +*24 (PortIoIn +uid 10651,0 +shape (CompositeShape +uid 10652,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 10653,0 +sl 0 +ro 270 +xt "-75000,-12375,-73500,-11625" +) +(Line +uid 10654,0 +sl 0 +ro 270 +xt "-73500,-12000,-73000,-12000" +pts [ +"-73500,-12000" +"-73000,-12000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 10655,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10656,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-79500,-12700,-76000,-11400" +st "clock" +ju 2 +blo "-76000,-11700" +tm "WireNameMgr" +) +) +) +*25 (PortIoIn +uid 10657,0 +shape (CompositeShape +uid 10658,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 10659,0 +sl 0 +ro 270 +xt "-75000,-10375,-73500,-9625" +) +(Line +uid 10660,0 +sl 0 +ro 270 +xt "-73500,-10000,-73000,-10000" +pts [ +"-73500,-10000" +"-73000,-10000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 10661,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10662,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-79500,-10700,-76000,-9400" +st "reset" +ju 2 +blo "-76000,-9700" +tm "WireNameMgr" +) +) +) +*26 (HdlText +uid 11667,0 +optionalChildren [ +*27 (EmbeddedText +uid 11714,0 +commentText (CommentText +uid 11715,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 11716,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "-10000,5000,6000,21000" +) +oxt "0,0,18000,5000" +text (MLText +uid 11717,0 +va (VaSet +font "Courier,9,0" +) +xt "-9800,5200,6200,13000" +st " +leds(buttons'range) <= buttons; + +leds(buttons'high+1 to leds'high) <= (others => '0'); + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 16000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 11668,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "-10000,4000,6000,22000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 11669,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*28 (Text +uid 11670,0 +va (VaSet +font "Verdana,9,1" +) +xt "-9600,22000,-8100,22900" +st "eb1" +blo "-9600,22700" +tm "HdlTextNameMgr" +) +*29 (Text +uid 11671,0 +va (VaSet +font "Verdana,9,1" +) +xt "-9600,23200,-9100,24100" +st "1" +blo "-9600,23900" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 11850,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-9750,20250,-8250,21750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*30 (PortIoIn +uid 12304,0 +shape (CompositeShape +uid 12305,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 12306,0 +sl 0 +ro 270 +xt "-20000,7625,-18500,8375" +) +(Line +uid 12307,0 +sl 0 +ro 270 +xt "-18500,8000,-18000,8000" +pts [ +"-18500,8000" +"-18000,8000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 12308,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 12309,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-25900,7500,-21000,8800" +st "buttons" +ju 2 +blo "-21000,8500" +tm "WireNameMgr" +) +) +) +*31 (Net +uid 12316,0 +decl (Decl +n "buttons" +t "std_ulogic_vector" +b "(1 to buttonNb)" +o 8 +suid 204,0 +) +declText (MLText +uid 12317,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-59300,-75000,-58300" +st "buttons : std_ulogic_vector(1 to buttonNb)" +) +) +*32 (PortIoOut +uid 12318,0 +shape (CompositeShape +uid 12319,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 12320,0 +sl 0 +ro 270 +xt "14500,7625,16000,8375" +) +(Line +uid 12321,0 +sl 0 +ro 270 +xt "14000,8000,14500,8000" +pts [ +"14000,8000" +"14500,8000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 12322,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 12323,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "17000,7500,19800,8800" +st "leds" +blo "17000,8500" +tm "WireNameMgr" +) +) +) +*33 (Net +uid 12330,0 +decl (Decl +n "leds" +t "std_ulogic_vector" +b "(1 to ledNb)" +o 9 +suid 205,0 +) +declText (MLText +uid 12331,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-58400,-76900,-57400" +st "leds : std_ulogic_vector(1 to ledNb)" +) +) +*34 (HdlText +uid 12702,0 +optionalChildren [ +*35 (EmbeddedText +uid 12708,0 +commentText (CommentText +uid 12709,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 12710,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "-32000,-19000,-16000,-9000" +) +oxt "0,0,18000,5000" +text (MLText +uid 12711,0 +va (VaSet +font "Courier,9,0" +) +xt "-31800,-18800,-16600,-9700" +st " +mux: process(uartSend, helloData, helloSend) +begin + if uartSend = '1' then + ascii <= uartData(ascii'range); + send <= '1'; + else + ascii <= helloData; + send <= helloSend; + end if; +end process mux; + +helloBusy <= busy; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 12703,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "-32000,-20000,-16000,-8000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 12704,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*36 (Text +uid 12705,0 +va (VaSet +font "Verdana,9,1" +) +xt "-31700,-8200,-30200,-7300" +st "eb2" +blo "-31700,-7500" +tm "HdlTextNameMgr" +) +*37 (Text +uid 12706,0 +va (VaSet +font "Verdana,9,1" +) +xt "-31700,-7000,-31200,-6100" +st "2" +blo "-31700,-6300" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 12707,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-31750,-9750,-30250,-8250" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*38 (Net +uid 12758,0 +decl (Decl +n "ascii" +t "std_ulogic_vector" +b "(asciiBitNb-1 downto 0)" +o 13 +suid 214,0 +) +declText (MLText +uid 12759,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-50300,-69300,-49300" +st "SIGNAL ascii : std_ulogic_vector(asciiBitNb-1 downto 0)" +) +) +*39 (Net +uid 12760,0 +decl (Decl +n "send" +t "std_ulogic" +o 15 +suid 215,0 +) +declText (MLText +uid 12761,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-48500,-81900,-47500" +st "SIGNAL send : std_ulogic" +) +) +*40 (Net +uid 12762,0 +decl (Decl +n "busy" +t "std_ulogic" +o 17 +suid 216,0 +) +declText (MLText +uid 12763,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-46700,-81900,-45700" +st "SIGNAL busy : std_ulogic" +) +) +*41 (PortIoIn +uid 12796,0 +shape (CompositeShape +uid 12797,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 12798,0 +sl 0 +ro 270 +xt "-75000,-36375,-73500,-35625" +) +(Line +uid 12799,0 +sl 0 +ro 270 +xt "-73500,-36000,-73000,-36000" +pts [ +"-73500,-36000" +"-73000,-36000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 12800,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 12801,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-78100,-36700,-76000,-35400" +st "RxD" +ju 2 +blo "-76000,-35700" +tm "WireNameMgr" +) +) +) +*42 (Net +uid 12802,0 +decl (Decl +n "RxD" +t "std_ulogic" +o 10 +suid 217,0 +) +declText (MLText +uid 12803,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-57500,-85000,-56500" +st "RxD : std_ulogic" +) +) +*43 (PortIoOut +uid 13024,0 +shape (CompositeShape +uid 13025,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 13026,0 +sl 0 +ro 270 +xt "14500,-33375,16000,-32625" +) +(Line +uid 13027,0 +sl 0 +ro 270 +xt "14000,-33000,14500,-33000" +pts [ +"14000,-33000" +"14500,-33000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 13028,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 13029,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "17000,-33700,20500,-32400" +st "debug" +blo "17000,-32700" +tm "WireNameMgr" +) +) +) +*44 (Net +uid 13038,0 +decl (Decl +n "debug" +t "std_ulogic_vector" +b "(15 DOWNTO 0)" +o 11 +suid 219,0 +) +declText (MLText +uid 13039,0 +va (VaSet +font "Verdana,8,0" +) +xt "-95000,-56600,-74700,-55600" +st "debug : std_ulogic_vector(15 DOWNTO 0)" +) +) +*45 (HdlText +uid 13102,0 +optionalChildren [ +*46 (EmbeddedText +uid 13132,0 +commentText (CommentText +uid 13133,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 13134,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "2000,-31000,23000,-26000" +) +oxt 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"" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "22200,15000,27600,16200" +st "" +blo "22200,16000" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "22200,16200,26100,17400" +st "" +blo "22200,17200" +) +) +gi *108 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sTC 0 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *109 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,9,1" +) +xt "-30000,5400,-22600,6600" +st "Declarations" +blo "-30000,6400" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,9,1" +) +xt "-30000,6600,-26300,7800" +st "Ports:" +blo "-30000,7600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "-30000,16600,-26800,17800" +st "User:" +blo "-30000,17600" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "-30000,5400,-21800,6600" +st "Internal User:" +blo "-30000,6400" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "-28000,17800,-28000,17800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "-30000,5400,-30000,5400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 2948,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/Libs/Lcd/hds/lcd@initializer/symbol.sb b/Libs/Lcd/hds/lcd@initializer/symbol.sb new file mode 100644 index 0000000..dd05038 --- /dev/null +++ b/Libs/Lcd/hds/lcd@initializer/symbol.sb @@ -0,0 +1,1886 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 16,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 21,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "columnSend" +t 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+variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "15:35:23" +) +(vvPair +variable "unit" +value "lcdSerializer" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2013" +) +(vvPair +variable "yy" +value "13" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 19,0 +optionalChildren [ +*75 (SymbolBody +uid 8,0 +optionalChildren [ +*76 (CptPort +uid 76,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 77,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,5625,54750,6375" +) +tg (CPTG +uid 78,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 79,0 +va (VaSet +font "Verdana,9,0" +) +xt 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"54000,9625,54750,10375" +) +tg (CPTG +uid 93,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 94,0 +va (VaSet +font "Verdana,9,0" +) +xt "49600,9400,53000,10600" +st "CS_n" +ju 2 +blo "53000,10400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 95,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,-1000,17500,-200" +st "CS_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CS_n" +t "std_ulogic" +o 6 +suid 4,0 +) +) +) +*79 (CptPort +uid 106,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 107,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,11625,38000,12375" +) +tg (CPTG +uid 108,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 109,0 +va (VaSet +font "Verdana,9,0" +) +xt "39000,11400,42300,12600" +st "reset" +blo "39000,12400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 110,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,-4200,17500,-3400" +st "reset : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 2 +suid 7,0 +) +) +) +*80 (CptPort +uid 111,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 112,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,7625,54750,8375" +) +tg (CPTG +uid 113,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 114,0 +va (VaSet +font "Verdana,9,0" +) +xt "49000,7400,53000,8600" +st "RST_n" +ju 2 +blo "53000,8400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 115,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,-200,17500,600" +st "RST_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RST_n" +t "std_ulogic" +o 7 +suid 8,0 +) +) +) +*81 (CptPort +uid 116,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 117,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,3625,54750,4375" +) +tg (CPTG +uid 118,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 119,0 +va (VaSet +font "Verdana,9,0" +) +xt "50200,3400,53000,4600" +st "SCL" +ju 2 +blo "53000,4400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 120,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,-2600,17500,-1800" +st "SCL : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "SCL" +t "std_ulogic" +o 4 +suid 9,0 +) +) +) +*82 (CptPort +uid 121,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 122,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,1625,54750,2375" +) +tg (CPTG +uid 123,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 124,0 +va (VaSet +font "Verdana,9,0" +) +xt "51100,1400,53000,2600" +st "SI" +ju 2 +blo "53000,2400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 125,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,-3400,17500,-2600" +st "SI : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "SI" +t "std_ulogic" +o 3 +suid 10,0 +) +) +) +*83 (CptPort +uid 383,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 384,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,1625,38000,2375" +) +tg (CPTG +uid 385,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 386,0 +va (VaSet +font "Verdana,9,0" +) +xt "39000,1400,41900,2600" +st "data" +blo "39000,2400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 387,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,600,32500,1400" +st "data : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +decl (Decl +n "data" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 8 +suid 11,0 +) +) +) +*84 (CptPort +uid 473,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 474,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,3625,38000,4375" +) +tg (CPTG +uid 475,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 476,0 +va (VaSet +font "Verdana,9,0" +) +xt "39000,3400,42100,4600" +st "send" +blo "39000,4400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 477,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,1400,17500,2200" +st "send : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "send" +t "std_ulogic" +o 9 +suid 17,0 +) +) +) +*85 (CptPort +uid 503,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 504,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,5625,38000,6375" +) +tg (CPTG +uid 505,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 506,0 +va (VaSet +font "Verdana,9,0" +) +xt "39000,5400,42100,6600" +st "busy" +blo "39000,6400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 507,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,2200,16500,3000" +st "busy : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "busy" +t "std_ulogic" +o 10 +suid 19,0 +) +) +) +] +shape (Rectangle +uid 169,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "38000,-2000,54000,14000" +) +oxt "15000,6000,33000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Verdana,9,1" +) +xt "37950,14000,40250,15200" +st "Lcd" +blo "37950,15000" +) +second (Text +uid 12,0 +va (VaSet +font "Verdana,9,1" +) +xt "37950,15200,45150,16400" +st "lcdSerializer" +blo "37950,16200" +) +) +gi *86 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "38000,18800,53000,22000" +st "Generic Declarations + +dataBitNb positive 9 +baudRateDivide integer 2 +" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "9" +) +(GiElement +name "baudRateDivide" +type "integer" +value "2" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sIVOD 1 +) +) +*87 (Grouping +uid 708,0 +optionalChildren [ +*88 (CommentText +uid 710,0 +shape (Rectangle +uid 711,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,33000,53000,34000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 712,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,33000,46200,34000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*89 (CommentText +uid 713,0 +shape (Rectangle +uid 714,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,29000,57000,30000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 715,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,29000,56200,30000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*90 (CommentText +uid 716,0 +shape (Rectangle +uid 717,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,31000,53000,32000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 718,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,31000,46200,32000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*91 (CommentText +uid 719,0 +shape (Rectangle +uid 720,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,31000,36000,32000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 721,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,31000,34300,32000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*92 (CommentText +uid 722,0 +shape (Rectangle +uid 723,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,30000,73000,34000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 724,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,30200,62400,31200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*93 (CommentText +uid 725,0 +shape (Rectangle +uid 726,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,29000,73000,30000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 727,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,29000,58800,30000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*94 (CommentText +uid 728,0 +shape (Rectangle +uid 729,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,29000,53000,31000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 730,0 +va (VaSet +fg "32768,0,0" +) +xt "39150,29500,45850,30500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*95 (CommentText +uid 731,0 +shape (Rectangle +uid 732,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,32000,36000,33000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 733,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,32000,34300,33000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*96 (CommentText +uid 734,0 +shape (Rectangle +uid 735,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,33000,36000,34000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 736,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,33000,34900,34000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*97 (CommentText +uid 737,0 +shape (Rectangle +uid 738,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,32000,53000,33000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 739,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,32000,45600,33000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 709,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,29000,73000,34000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *98 (PackageList +uid 16,0 +stg "VerticalLayoutStrategy" +textVec [ +*99 (Text +uid 17,0 +va (VaSet +font "Verdana,9,1" +) +xt "0,-14800,7600,-13600" +st "Package List" +blo "0,-13800" +) +*100 (MLText +uid 18,0 +va (VaSet +font "Verdana,9,0" +) +xt "0,-13600,17500,-10000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL;" +tm "PackageList" +) +] +) +windowSize "134,37,1420,895" +viewArea "-1100,-15900,75724,35652" +cachedDiagramExtent "0,-14800,73000,34000" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +xMargin 49 +yMargin 49 +paperWidth 761 +paperHeight 1077 +windowsPaperWidth 761 +windowsPaperHeight 1077 +paperType "A4" +windowsPaperName "A4" +windowsPaperType 9 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,-15000" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +font "Verdana,9,0" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "22200,15000,27600,16200" +st "" +blo "22200,16000" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "22200,16200,26100,17400" +st "" +blo "22200,17200" +) +) +gi *101 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sTC 0 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,9,0" +) +xt "0,750,2500,1950" +st "In0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,9,0" +) +xt "0,750,4300,1950" +st "Buffer0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *102 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,9,1" +) +xt "0,-7400,7400,-6200" +st "Declarations" +blo "0,-6400" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,9,1" +) +xt "0,-6200,3700,-5000" +st "Ports:" +blo "0,-5200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "0,3000,3200,4200" +st "User:" +blo "0,4000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "0,-7400,8200,-6200" +st "Internal User:" +blo "0,-6400" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,4200,2000,4200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,-7400,0,-7400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 969,0 +activeModelName "Symbol" +) diff --git a/Libs/Lcd_test/LCD_explanation.txt b/Libs/Lcd_test/LCD_explanation.txt new file mode 100644 index 0000000..7214b89 --- /dev/null +++ b/Libs/Lcd_test/LCD_explanation.txt @@ -0,0 +1,188 @@ +-- filename: LCD_usage.vhd +-- kind: txt file +-------------------------------------------------------------------------------- +-- History: +-- v1.0 : zas 22.08.2013 -- Initial Version +-------------------------------------------------------------------------------- +-- Description: +-- Explanation about the usage and the functionalities of the LCD Driver. +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Overview +-- +The Lcd and Lcd_test library is intended to use with the HEB_LCD_V2_0, see +http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_lcd. + +The HEB_LCD_V2_0 features a EADOGM132-5 LCD. Its a 4 Line and 132 column black- +light display. The font created for it uses 6 columns per character which allows +to have 4 lines with 22 characters each. + +The connection is I2C based and some initial configuration needs to be done. The +bloc lcdController has everything needed to use the LCD. See the vague toplevel +overview below. + + +--------------------------------------------------------------------------+ + | +---------------------+ +----------------+ +---------------+ | + | | lcdCharacterEncoder |---->| lcdInitialiser |------>| lcdSerialiser | | + | +---------------------+ +----------------+ +---------------+ | + | ^ | + | | +-------------+ | + | +--------| bramMemory | | + | lcdController +-------------+ | + +--------------------------------------------------------------------------+ + +-------------------------------------------------------------------------------- +-- Bloc description +-- +lcdController -- Main bloc containing all needed subblocs + lcdCharacterEncoder -- This bloc receives the ASCII data to display and + and converts it to display data or display commands + bramMemory -- Contains the command for command chars (<0x20) and + the display (pixel) data for a the symbol chars + (>=0x20). + All the data of this ram are stored inthe font.txt file + lcdInitialiser -- This bloc lets send predefined commands for 2 + features. One is for initialising the display in the + beginning, and the other is for clear all data from + the display + lcdSerialiser -- This bloc takes the parallised data and sends them + over the I2C bus. + +-------------------------------------------------------------------------------- +-- Supported Characters +-- +In VHDL the characters can be written with the following command: + character'pos("VHDL") +where VHDL is inidicated in the table below. + + Hex VHDL Value Description Function +----------------------------------------------------------- +0x00 "nul" Null Not supported +0x01 "soh" Start of Header Not supported +0x02 "stx" Start of Text (0,0) Goto pos line 0 character 0 +0x03 "etx" End of Text (3,21) Goto pos line 3 character 21 +0x04 "eot" End of Transmission Not supported +0x05 "enq" Enquiry Not supported +0x06 "ack" Acknowledgment Not supported +0x07 "bel" Bell Not supported +0x08 "bs" Backspace (y,x-1) Jump one char back +0x09 "ht" Horizontal Tab Not supported +0x0A "lf" Line Feed (y+1,x)Goto next line +0x0B "vt" Vertical Tab (y-1,x) Goto previous line +0x0C "ff" Form Feed Not supported +0x0D "cr" Carriage Return (y,0) Goto beginning of line +0x0E "so" Shift Out Not supported +0x0F "si" Shift In Not supported +0x10 "dle" Data Link Escape Not supported +0x11 "dc1" XON Device Control 1 Not supported +0x12 "dc2" Device Control 2 Not supported +0x13 "dc3" XOFFDevice Control 3 Not supported +0x14 "dc4" Device Control 4 Not supported +0x15 "nak" Negativ Acknowledgemnt Not supported +0x16 "syn" Synchronous Idle Not supported +0x17 "etb" End of Trans. Block Not supported +0x18 "can" Cancel Clear entire display +0x19 "em" End of Medium Not supported +0x1A "sub" Substitute Not supported +0x1B "esc" Escape Not supported +0x1C "fsp" File Separator Not supported +0x1D "gsp" Group Separator Not supported +0x1E "rsp" Reqst to SendRec. Sep. Not supported +0x1F "usp" Unit Separator Not supported +0x20 " " Space Print char +0x21 "!" exclamation mark Print char +0x22 """ double quote Print char +0x23 "#" number sign Print char +0x24 "$" dollar sign Print char +0x25 "%" percent Print char +0x26 "&" ampersand Print char +0x27 "'" single quote Print char +0x28 "(" left/open parenthesis Print char +0x29 ")" right/closing parenth. Print char +0x2A "*" asterisk Print char +0x2B "+" plus Print char +0x2C "," comma Print char +0x2D "-" minus or dash Print char +0x2E "." dot Print char +0x2F "/" forward slash Print char +0x30 "0" Print char +0x31 "1" Print char +0x32 "2" Print char +0x33 "3" Print char +0x34 "4" Print char +0x35 "5" Print char +0x36 "6" Print char +0x37 "7" Print char +0x38 "8" Print char +0x39 "9" Print char +0x3A ":" colon Print char +0x3B ";" semi-colon Print char +0x3C "<" less than Print char +0x3D "=" equal sign Print char +0x3E ">" greater than Print char +0x3F "?" question mark Print char +0x40 "@" AT symbol Print char +0x41 "A" Print char +0x42 "B" Print char +0x43 "C" Print char +0x44 "D" Print char +0x45 "E" Print char +0x46 "F" Print char +0x47 "G" Print char +0x48 "H" Print char +0x49 "I" Print char +0x4A "J" Print char +0x4B "K" Print char +0x4C "L" Print char +0x4D "M" Print char +0x4E "N" Print char +0x4F "O" Print char +0x50 "P" Print char +0x51 "Q" Print char +0x52 "R" Print char +0x53 "S" Print char +0x54 "T" Print char +0x55 "U" Print char +0x56 "V" Print char +0x57 "W" Print char +0x58 "X" Print char +0x59 "Y" Print char +0x5A "Z" Print char +0x5B "[" left/opening bracket Print char +0x5C "\" back slash Print char +0x5D "]" right/closing bracket Print char +0x5E "^" caret/circumflex Print char +0x5F "_" underscore Print char +0x60 "`" Print char +0x61 "a" Print char +0x62 "b" Print char +0x63 "c" Print char +0x64 "d" Print char +0x65 "e" Print char +0x66 "f" Print char +0x67 "g" Print char +0x68 "h" Print char +0x69 "i" Print char +0x6A "j" Print char +0x6B "k" Print char +0x6C "l" Print char +0x6D "m" Print char +0x6E "n" Print char +0x6F "o" Print char +0x70 "p" Print char +0x71 "q" Print char +0x72 "r" Print char +0x73 "s" Print char +0x74 "t" Print char +0x75 "u" Print char +0x76 "v" Print char +0x77 "w" Print char +0x78 "x" Print char +0x79 "y" Print char +0x7A "z" Print char +0x7B "{" left/opening brace Print char +0x7C "|" vertical bar Print char +0x7D "}" right/closing brace Print char +0x7E "~" tilde Print char +0x7F "del" arrow to the left Print char \ No newline at end of file diff --git a/Libs/Lcd_test/dogm132-5e.pdf b/Libs/Lcd_test/dogm132-5e.pdf new file mode 100644 index 0000000..37c6a3a Binary files /dev/null and b/Libs/Lcd_test/dogm132-5e.pdf differ diff --git a/Libs/Lcd_test/hdl/lcdController_tester_test.vhd b/Libs/Lcd_test/hdl/lcdController_tester_test.vhd new file mode 100644 index 0000000..ac8462d --- /dev/null +++ b/Libs/Lcd_test/hdl/lcdController_tester_test.vhd @@ -0,0 +1,47 @@ +ARCHITECTURE test OF lcdController_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_ulogic := '1'; + + constant testInterval: time := 5 us; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- send sequence + process + begin + ascii <= (others => '0'); + send <= '0'; + wait until falling_edge(busy); + wait for testInterval; + -- send single character + wait until rising_edge(clock_int); + ascii <= std_ulogic_vector(to_unsigned(character'pos('a'), ascii'length)); + send <= '1', '0' after clockPeriod; + wait until rising_edge(busy); + wait until falling_edge(busy); + wait for testInterval; + -- send character stream + for index in character'pos('b') to character'pos('d') loop + ascii <= std_ulogic_vector(to_unsigned(index, ascii'length)); + send <= '1', '0' after clockPeriod; + wait until rising_edge(busy); + wait until falling_edge(busy); + wait for 1 ns; + end loop; + wait for testInterval; + -- end of simulation + assert false + report "End of simulation" + severity failure; + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Lcd_test/hdl/lcdDemo_tester_test.vhd b/Libs/Lcd_test/hdl/lcdDemo_tester_test.vhd new file mode 100644 index 0000000..a43aa24 --- /dev/null +++ b/Libs/Lcd_test/hdl/lcdDemo_tester_test.vhd @@ -0,0 +1,111 @@ +ARCHITECTURE test OF lcdDemo_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_ulogic := '1'; + + constant testInterval:time := 0.1 ms; + constant initSequenceLength:time := 20 us; + constant helloSequenceLength:time := 1 ms; + + constant rs232Frequency: real := real(baudRate); + constant rs232Period: time := (1.0/rs232Frequency) * 1 sec; + constant rs232WriteInterval: time := 10*rs232Period; + + signal rs232OutString : string(1 to 32); + signal rs232SendOutString: std_uLogic; + signal rs232SendOutDone: std_uLogic; + signal rs232OutByte: character; + signal rs232SendOutByte: std_uLogic; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- test sequence + process + begin + rs232SendOutString <= '0'; + buttons <= (others => '0'); + wait for initSequenceLength + helloSequenceLength; + -- send bytes from serial port + rs232OutString <= "a "; + rs232SendOutString <= '1', '0' after 1 ns; + wait until rs232SendOutDone = '1'; + wait for rs232WriteInterval; + + rs232OutString <= "hello world "; + rs232SendOutString <= '1', '0' after 1 ns; + wait until rs232SendOutDone = '1'; + wait for rs232WriteInterval; + wait for testInterval; + -- send hello message + wait until rising_edge(clock_int); + for index in buttons'range loop + buttons(index) <= '1'; + wait until rising_edge(clock_int); + buttons(index) <= '0'; + wait until rising_edge(clock_int); + end loop; + wait for helloSequenceLength; + wait for testInterval; + -- end of simulation + assert false + report "End of simulation" + severity failure; + wait; + end process; + +--============================================================================ + -- RS232 send + rsSendSerialString: process + constant rs232BytePeriod : time := 15*rs232Period; + variable commandRight: natural; + begin + rs232SendOutByte <= '0'; + rs232SendOutDone <= '0'; + + wait until rising_edge(rs232SendOutString); + + commandRight := rs232OutString'right; + while rs232OutString(commandRight) = ' ' loop + commandRight := commandRight-1; + end loop; + + for index in rs232OutString'left to commandRight loop + rs232OutByte <= rs232OutString(index); + rs232SendOutByte <= '1', '0' after 1 ns; + wait for rs232BytePeriod; + end loop; + + rs232OutByte <= cr; + rs232SendOutByte <= '1', '0' after 1 ns; + wait for rs232BytePeriod; + + rs232SendOutDone <= '1'; + wait for 1 ns; + end process rsSendSerialString; + -- send byte + rsSendSerialByte: process + variable txData: unsigned(7 downto 0); + begin + RxD <= '1'; + + wait until rising_edge(rs232SendOutByte); + txData := to_unsigned(character'pos(rs232OutByte), txData'length); + + RxD <= '0'; + wait for rs232Period; + + for index in txData'reverse_range loop + RxD <= txData(index); + wait for rs232Period; + end loop; + + end process rsSendSerialByte; + +END ARCHITECTURE test; diff --git a/Libs/Lcd_test/hdl/lcdSerializer_tester_test.vhd b/Libs/Lcd_test/hdl/lcdSerializer_tester_test.vhd new file mode 100644 index 0000000..dd8798b --- /dev/null +++ b/Libs/Lcd_test/hdl/lcdSerializer_tester_test.vhd @@ -0,0 +1,69 @@ +ARCHITECTURE test OF lcdSerializer_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_ulogic := '1'; + + constant initializationSequenceLength: positive := 14; + type initializtionDataType is array (1 to initializationSequenceLength) + of std_ulogic_vector(data'range); + constant initializtionData: initializtionDataType :=( + '0' & X"40", -- Display start line 0 + '0' & X"A1", -- + '0' & X"C0", -- + '0' & X"A6", -- + '0' & X"A2", -- + '0' & X"2F", -- + '0' & X"F8", -- + '0' & X"00", -- + '0' & X"23", -- + '0' & X"81", -- + '0' & X"1F", -- + '0' & X"AC", -- + '0' & X"00", -- + '0' & X"AF" -- + ); + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- send sequence + process + begin + data <= (others => '0'); + send <= '0'; + wait until falling_edge(busy); + -- send initialization codes + wait until rising_edge(clock_int); + for index in initializtionData'range loop + data <= initializtionData(index); + send <= '1', '0' after clockPeriod; + wait until rising_edge(busy); + wait until falling_edge(busy); + wait for 1 ns; + end loop; + wait for 100*clockPeriod; + -- send pixel codes + wait until rising_edge(clock_int); + for index in 1 to 8 loop + data <= std_ulogic_vector(to_unsigned(index, data'length)); + data(data'high) <= '1'; + send <= '1', '0' after clockPeriod; + wait until rising_edge(busy); + wait until falling_edge(busy); + wait for 1 ns; + end loop; + wait for 100*clockPeriod; + -- end of simulation + assert false + report "End of simulation" + severity failure; + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Lcd_test/hds/.hdlsidedata/_lcdController_tester_test.vhd._fpf b/Libs/Lcd_test/hds/.hdlsidedata/_lcdController_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Lcd_test/hds/.hdlsidedata/_lcdController_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd_test/hds/.hdlsidedata/_lcdDemo_tester_test.vhd._fpf b/Libs/Lcd_test/hds/.hdlsidedata/_lcdDemo_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Lcd_test/hds/.hdlsidedata/_lcdDemo_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd_test/hds/.hdlsidedata/_lcdSerializer_tester_test.vhd._fpf b/Libs/Lcd_test/hds/.hdlsidedata/_lcdSerializer_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Lcd_test/hds/.hdlsidedata/_lcdSerializer_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Lcd_test/hds/.hdlsidedata/lcdController_tester_test.vhd.info/msimSimulationReplay.sh b/Libs/Lcd_test/hds/.hdlsidedata/lcdController_tester_test.vhd.info/msimSimulationReplay.sh new file mode 100644 index 0000000..6ecd536 --- /dev/null +++ b/Libs/Lcd_test/hds/.hdlsidedata/lcdController_tester_test.vhd.info/msimSimulationReplay.sh @@ -0,0 +1,3 @@ +# Script to replay the last simulation run +cd $SCRATCH_DIR/$DESIGN_NAME/Lcd_test/work +"C:\eda\Modelsim/win32/vsim" -f hds_args.tmp diff --git a/Libs/Lcd_test/hds/_lcdcontroller_tb._epf b/Libs/Lcd_test/hds/_lcdcontroller_tb._epf new file mode 100644 index 0000000..41daecf --- /dev/null +++ b/Libs/Lcd_test/hds/_lcdcontroller_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lcd@controller_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Lcd_test/hds/_lcdcontroller_tester._epf b/Libs/Lcd_test/hds/_lcdcontroller_tester._epf new file mode 100644 index 0000000..a8e5eac --- /dev/null +++ b/Libs/Lcd_test/hds/_lcdcontroller_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom lcdController_tester_test.vhd diff --git a/Libs/Lcd_test/hds/_lcddemo_tb._epf b/Libs/Lcd_test/hds/_lcddemo_tb._epf new file mode 100644 index 0000000..41ff47d --- /dev/null +++ b/Libs/Lcd_test/hds/_lcddemo_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lcd@demo_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Lcd_test/hds/_lcddemo_tester._epf b/Libs/Lcd_test/hds/_lcddemo_tester._epf new file mode 100644 index 0000000..fa20b5d --- /dev/null +++ b/Libs/Lcd_test/hds/_lcddemo_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom lcdDemo_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Lcd_test/hds/_lcdserializer_tb._epf b/Libs/Lcd_test/hds/_lcdserializer_tb._epf new file mode 100644 index 0000000..71b93dd --- /dev/null +++ b/Libs/Lcd_test/hds/_lcdserializer_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lcd@serializer_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 0 diff --git a/Libs/Lcd_test/hds/_lcdserializer_tester._epf b/Libs/Lcd_test/hds/_lcdserializer_tester._epf new file mode 100644 index 0000000..f90badb --- /dev/null +++ b/Libs/Lcd_test/hds/_lcdserializer_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom lcdSerializer_tester_test.vhd diff --git a/Libs/Lcd_test/hds/lcd@controller_tb/struct.bd b/Libs/Lcd_test/hds/lcd@controller_tb/struct.bd new file mode 100644 index 0000000..0cfb350 --- /dev/null +++ b/Libs/Lcd_test/hds/lcd@controller_tb/struct.bd @@ -0,0 +1,3437 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "Lcd_test" +duName "lcdController_tester" +elements [ +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +(GiElement +name "asciiBitNb" +type "positive" +value "asciiBitNb" +) +] +mwi 0 +uid 175,0 +) +(Instance +name "I_dut" +duLibraryName "Lcd" +duName "lcdController" +elements [ +(GiElement +name "baudRateDivide" +type "integer" +value "baudRateDivide" +) +(GiElement +name "asciiBitNb" +type "positive" +value "asciiBitNb" +) +] +mwi 0 +uid 3514,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tb" +) +(vvPair +variable "d_logical" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdController_tb" +) +(vvPair +variable "date" +value "11.11.2019" +) +(vvPair +variable "day" +value "Mon" +) +(vvPair +variable "day_long" +value "Monday" +) +(vvPair +variable "dd" +value "11" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "lcdController_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "silvan.zahno" +) +(vvPair +variable "graphical_source_date" +value "11.11.2019" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE6996" +) +(vvPair +variable "graphical_source_time" +value "07:37:47" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE6996" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Lcd_test" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../libs/SPI_test/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/ElN/Libraries/Lcd_test/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "lcdController_tb" +) +(vvPair +variable "month" +value "Nov" +) +(vvPair +variable "month_long" +value "November" +) +(vvPair +variable "p" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdController_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_ActelPath" +value "D:\\Projects\\Trypano\\ControlBoard\\IglooTester\\Board\\actel\\boardTester" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\BoardTester\\Board\\ise" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME/modeltech/bin" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "07:37:47" +) +(vvPair +variable "unit" +value "lcdController_tb" +) +(vvPair +variable "user" +value "silvan.zahno" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 20,0 +optionalChildren [ +*1 (Grouping +uid 77,0 +optionalChildren [ +*2 (CommentText +uid 79,0 +shape (Rectangle +uid 80,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "78000,58000,97000,60000" +) +oxt "45000,22000,64000,24000" +text (MLText +uid 81,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "78200,58400,93600,59600" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 18600 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +uid 82,0 +shape (Rectangle +uid 83,0 +sl 0 +va (VaSet +vasetType 1 +fg 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+xt "25250,46250,26750,47750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +) +*16 (Net +uid 2316,0 +decl (Decl +n "reset" +t "std_ulogic" +o 9 +suid 37,0 +) +declText (MLText +uid 2317,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,22600,13700,23600" +st "SIGNAL reset : std_ulogic" +) +) +*17 (Net +uid 2324,0 +decl (Decl +n "clock" +t "std_ulogic" +o 8 +suid 38,0 +) +declText (MLText +uid 2325,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,21600,13700,22600" +st "SIGNAL clock : std_ulogic" +) +) +*18 (Net +uid 3041,0 +decl (Decl +n "CS1_n" +t "std_ulogic" +o 2 +suid 47,0 +) +declText (MLText +uid 3042,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,15600,14300,16600" +st "SIGNAL CS1_n : std_ulogic" +) +) +*19 (Net +uid 3049,0 +decl (Decl +n "RST_n" +t "std_ulogic" +o 3 +suid 48,0 +) +declText (MLText +uid 3050,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,16600,14300,17600" +st "SIGNAL RST_n : std_ulogic" +) +) +*20 (Net +uid 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"2000,19600,26500,20600" +st "SIGNAL ascii : std_ulogic_vector(asciiBitNb-1 downto 0)" +) +) +*25 (Net +uid 3414,0 +decl (Decl +n "busy" +t "std_ulogic" +o 7 +suid 55,0 +) +declText (MLText +uid 3415,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,20600,13900,21600" +st "SIGNAL busy : std_ulogic" +) +) +*26 (SaComponent +uid 3514,0 +optionalChildren [ +*27 (CptPort +uid 3474,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3475,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "44250,27625,45000,28375" +) +tg (CPTG +uid 3476,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3477,0 +va (VaSet +) +xt "46000,27400,48500,28300" +st "clock" +blo "46000,28100" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 7 +suid 1,0 +) +) +) +*28 (CptPort +uid 3478,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3479,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "44250,29625,45000,30375" +) +tg (CPTG +uid 3480,0 +ps "CptPortTextPlaceStrategy" +stg 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"49152,49152,49152" +) +xt "45250,30250,46750,31750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" +ftype 1 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*40 (Wire +uid 2318,0 +shape (OrthoPolyLine +uid 2319,0 +va (VaSet +vasetType 3 +) +xt "43000,30000,44250,40000" +pts [ +"44250,30000" +"43000,30000" +"43000,40000" +] +) +start &28 +end &12 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2322,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2323,0 +va (VaSet +font "Verdana,12,0" +) +xt "41250,28600,45350,30000" +st "reset" +blo "41250,29800" +tm "WireNameMgr" +) +) +on &16 +) +*41 (Wire +uid 2326,0 +shape (OrthoPolyLine +uid 2327,0 +va (VaSet +vasetType 3 +) +xt "41000,28000,44250,40000" +pts [ +"44250,28000" +"41000,28000" +"41000,40000" +] +) +start &27 +end &12 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2330,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f 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3,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,900,45000,1800" +st "Ports:" +blo "42000,1600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,9800,44500,10700" +st "User:" +blo "42000,10500" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "42000,0,49500,900" +st "Internal User:" +blo "42000,700" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Verdana,8,0" +) +xt "44000,10700,44000,10700" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 841,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/Lcd_test/hds/lcd@demo_tb/struct.bd b/Libs/Lcd_test/hds/lcd@demo_tb/struct.bd new file mode 100644 index 0000000..92e3c4d --- /dev/null +++ b/Libs/Lcd_test/hds/lcd@demo_tb/struct.bd @@ -0,0 +1,3526 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "Lcd_test" +duName "lcdDemo_tester" +elements [ +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +(GiElement +name "buttonNb" +type "positive" +value "buttonNb" +) +(GiElement +name "ledNb" +type "positive" +value "ledNb" +) +(GiElement +name "baudrate" +type "positive" +value "rs232Baudrate" +) +] +mwi 0 +uid 175,0 +) +(Instance +name "I_dut" +duLibraryName "lcd" +duName "lcdDemo" +elements [ +(GiElement +name "baudRateDivide" +type "positive" +value "baudRateDivide" +) +(GiElement +name "buttonNb" +type "positive" +value "buttonNb" +) +(GiElement +name "ledNb" +type "positive" +value "ledNb" +) +(GiElement +name "rs232BaudRate" +type "positive" +value "rs232Baudrate" +) +] +mwi 0 +uid 4057,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@demo_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@demo_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" 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&0 +) +defaultPortMapFrame (PortMapFrame +ps "PortMapFrameStrategy" +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "0,0,10000,12000" +) +portMapText (BiTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +first (MLText +va (VaSet +) +) +second (MLText +va (VaSet +) +tm "PortMapTextMgr" +) +) +) +defaultGenFrame (Frame +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "26368,26368,26368" +lineStyle 2 +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (MLText +va (VaSet +) +xt "-2950,-1200,15550,0" +st "g0: FOR i IN 0 TO n GENERATE" +tm "FrameTitleTextMgr" +) +) +seqNum (FrameSequenceNumber +ps "TopLeftStrategy" +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "50,50,1250,1450" +) +num (Text +va (VaSet +) +xt "-50,150,1350,1350" +st "1" +blo "-50,1150" +tm "FrameSeqNumMgr" +) +) +decls (MlTextGroup +ps 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"0,6200,5500,7100" +st "Post User:" +blo "0,6900" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,6200,0,6200" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +suid 58,0 +usingSuid 1 +emptyRow *82 (LEmptyRow +) +uid 22,0 +optionalChildren [ +*83 (RefLabelRowHdr +) +*84 (TitleRowHdr +) +*85 (FilterRowHdr +) +*86 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*87 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*88 (GroupColHdr +tm "GroupColHdrMgr" +) +*89 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*90 (ModeColHdr +tm "BlockDiagramModeColHdrMgr" +) +*91 (TypeColHdr +tm "BlockDiagramTypeColHdrMgr" +) +*92 (BoundsColHdr +tm "BlockDiagramBoundsColHdrMgr" +) +*93 (InitColHdr +tm "BlockDiagramInitColHdrMgr" +) +*94 (EolColHdr +tm "BlockDiagramEolColHdrMgr" +) +*95 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "reset" +t "std_ulogic" +o 10 +suid 37,0 +) +) +uid 2392,0 +) +*96 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n 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+fixedCol 4 +fixedRow 2 +name "Ports" +uid 36,0 +vaOverrides [ +] +) +] +) +uid 21,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *128 (LEmptyRow +) +uid 51,0 +optionalChildren [ +*129 (RefLabelRowHdr +) +*130 (TitleRowHdr +) +*131 (FilterRowHdr +) +*132 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*133 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*134 (GroupColHdr +tm "GroupColHdrMgr" +) +*135 (NameColHdr +tm "GenericNameColHdrMgr" +) +*136 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*137 (InitColHdr +tm "GenericValueColHdrMgr" +) +*138 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*139 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 63,0 +optionalChildren [ +*140 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *141 (MRCItem +litem &128 +pos 0 +dimension 20 +) +uid 65,0 +optionalChildren [ +*142 (MRCItem +litem &129 +pos 0 +dimension 20 +uid 66,0 +) +*143 (MRCItem +litem &130 +pos 1 +dimension 23 +uid 67,0 +) +*144 (MRCItem +litem &131 +pos 2 +hidden 1 +dimension 20 +uid 68,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 69,0 +optionalChildren [ +*145 (MRCItem +litem &132 +pos 0 +dimension 20 +uid 70,0 +) +*146 (MRCItem +litem &134 +pos 1 +dimension 50 +uid 71,0 +) +*147 (MRCItem +litem &135 +pos 2 +dimension 100 +uid 72,0 +) +*148 (MRCItem +litem &136 +pos 3 +dimension 100 +uid 73,0 +) +*149 (MRCItem +litem &137 +pos 4 +dimension 50 +uid 74,0 +) +*150 (MRCItem +litem &138 +pos 5 +dimension 50 +uid 75,0 +) +*151 (MRCItem +litem &139 +pos 6 +dimension 80 +uid 76,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 64,0 +vaOverrides [ +] +) +] +) +uid 50,0 +type 1 +) +activeModelName "BlockDiag" +) diff --git a/Libs/Lcd_test/hds/lcd@demo_tb/struct.bd.info/msimSimulationReplay.sh b/Libs/Lcd_test/hds/lcd@demo_tb/struct.bd.info/msimSimulationReplay.sh new file mode 100644 index 0000000..efec789 --- /dev/null +++ b/Libs/Lcd_test/hds/lcd@demo_tb/struct.bd.info/msimSimulationReplay.sh @@ -0,0 +1,3 @@ +# Script to replay the last simulation run +cd $SCRATCH_DIR/$DESIGN_NAME/Lcd_test/work +"C:\eda\modeltech_6.6e/win32/vsim" -f hds_args.tmp diff --git a/Libs/Lcd_test/hds/lcd@demo_tb/symbol.sb b/Libs/Lcd_test/hds/lcd@demo_tb/symbol.sb new file mode 100644 index 0000000..2f16795 --- /dev/null +++ b/Libs/Lcd_test/hds/lcd@demo_tb/symbol.sb @@ -0,0 +1,1297 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 5,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 21,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 34,0 +optionalChildren [ +*14 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *15 (MRCItem +litem &1 +pos 0 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integer((clockFrequency/2.0)/spiFrequency + 1.0); + +constant dataBitNb: positive := 8+1;" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +font "Arial,8,1" +) +xt "0,13000,7100,14000" +st "Diagram Signals:" +blo "0,13800" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,6000,4700,7000" +st "Post User:" +blo "0,6800" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,6000,0,6000" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +suid 53,0 +usingSuid 1 +emptyRow *81 (LEmptyRow +) +uid 22,0 +optionalChildren [ +*82 (RefLabelRowHdr +) +*83 (TitleRowHdr +) +*84 (FilterRowHdr +) +*85 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*86 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*87 (GroupColHdr +tm "GroupColHdrMgr" +) +*88 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*89 (ModeColHdr +tm "BlockDiagramModeColHdrMgr" +) +*90 (TypeColHdr +tm "BlockDiagramTypeColHdrMgr" +) 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"44000,8000,74500,8800" +st "data : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "data" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 8 +suid 50,0 +) +) +) +*81 (CptPort +uid 581,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 582,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32625,5250,33375,6000" +) +tg (CPTG +uid 583,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 584,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "32300,7000,33700,11100" +st "reset" +ju 2 +blo "33500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 585,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8800,59500,9600" +st "reset : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "reset" +t "std_ulogic" +o 9 +suid 51,0 +) +) +) +*82 (CptPort +uid 586,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 587,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "56625,5250,57375,6000" +) +tg (CPTG +uid 588,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 589,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "56300,7000,57700,11700" +st "RST_n" +ju 2 +blo "57500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 590,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4000,59500,4800" +st "RST_n : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "RST_n" +t "std_ulogic" +o 3 +suid 52,0 +) +) +) +*83 (CptPort +uid 591,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 592,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60625,5250,61375,6000" +) +tg (CPTG +uid 593,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 594,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "60300,7000,61700,10200" +st "SCL" +ju 2 +blo "61500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 595,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4800,59500,5600" +st "SCL : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "SCL" +t "std_ulogic" +o 4 +suid 53,0 +) +) +) +*84 (CptPort +uid 596,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 597,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24625,5250,25375,6000" +) +tg (CPTG +uid 598,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 599,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "24300,7000,25700,10900" +st "send" +ju 2 +blo "25500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 600,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9600,58500,10400" +st "send : OUT std_ulogic +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "send" +t "std_ulogic" +o 10 +suid 54,0 +) +) +) +*85 (CptPort +uid 601,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 602,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62625,5250,63375,6000" +) +tg (CPTG +uid 603,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 604,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "62300,7000,63700,9100" +st "SI" +ju 2 +blo "63500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 605,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5600,59500,6400" +st "SI : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "SI" +t "std_ulogic" +o 5 +suid 55,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,71000,14000" +) +oxt "15000,6000,67000,14000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Verdana,9,1" +) +xt "37250,8800,42250,10000" +st "Lcd_test" +blo "37250,9800" +) +second (Text +uid 12,0 +va (VaSet +font "Verdana,9,1" +) +xt "37250,10000,48750,11200" +st "lcdSerializer_tester" +blo "37250,11000" +) +) +gi *86 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "20000,6000,38000,9200" +st "Generic Declarations + +clockFrequency real 100.0E6 +dataBitNb positive 9 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "clockFrequency" +type "real" +value "100.0E6" +) +(GiElement +name "dataBitNb" +type "positive" +value "9" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *87 (PackageList +uid 16,0 +stg "VerticalLayoutStrategy" +textVec [ +*88 (Text +uid 17,0 +va (VaSet +font "Verdana,9,1" +) +xt "0,0,7600,1200" +st "Package List" +blo "0,1000" +) +*89 (MLText +uid 18,0 +va (VaSet +) +xt "0,1200,17500,4800" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all;" +tm "PackageList" +) +] +) +windowSize "186,60,1203,750" +viewArea "-500,-500,71320,48820" +cachedDiagramExtent "0,0,74500,14000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "Lcd_test" +entityName "lcdSerializer_tb" +viewName "struct.bd" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,31000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "20300,14800,25700,16000" +st "" +blo "20300,15800" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "20300,16000,24200,17200" +st "" +blo "20300,17000" +) +) +gi *90 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sIVOD 1 +) +portVis (PortSigDisplay +sTC 0 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2500,1950" +st "In0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_ulogic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,4300,1950" +st "Buffer0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_ulogic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *91 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,0,49400,1200" +st "Declarations" +blo "42000,1000" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,1200,45700,2400" +st "Ports:" +blo "42000,2200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,10400,45200,11600" +st "User:" +blo "42000,11400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "42000,0,50200,1200" +st "Internal User:" +blo "42000,1000" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,44000,11600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 625,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/Lcd_test/sim/lcdController.do b/Libs/Lcd_test/sim/lcdController.do new file mode 100644 index 0000000..3d2fcaf --- /dev/null +++ b/Libs/Lcd_test/sim/lcdController.do @@ -0,0 +1,45 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group {Reset and clock} /lcdcontroller_tb/reset +add wave -noupdate -group {Reset and clock} /lcdcontroller_tb/clock +add wave -noupdate -expand -group {Character to send} -radix ascii -radixshowbase 0 /lcdcontroller_tb/ascii +add wave -noupdate -expand -group {Character to send} -radix hexadecimal -radixshowbase 0 /lcdcontroller_tb/ascii +add wave -noupdate -expand -group {Character to send} -radixshowbase 0 /lcdcontroller_tb/send +add wave -noupdate -expand -group {Character to send} -radixshowbase 0 /lcdcontroller_tb/busy +add wave -noupdate -group {Font encoder} -radixshowbase 0 /lcdcontroller_tb/I_dut/I_font/fontDisplayState +add wave -noupdate -group {Font encoder} -format Analog-Step -height 20 -max 6.0 -radix unsigned -radixshowbase 0 /lcdcontroller_tb/I_dut/I_font/columnCounter +add wave -noupdate -group {Font encoder} -height 20 -radix unsigned -radixshowbase 0 /lcdcontroller_tb/I_dut/I_font/columnCounter +add wave -noupdate -group {Font encoder} -radix unsigned -radixshowbase 0 /lcdcontroller_tb/I_dut/I_font/pixelOffset +add wave -noupdate -group {Font encoder} -radix hexadecimal -childformat {{/lcdcontroller_tb/I_dut/pixelData(47) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(46) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(45) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(44) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(43) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(42) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(41) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(40) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(39) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(38) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(37) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(36) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(35) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(34) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(33) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(32) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(31) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(30) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(29) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(28) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(27) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(26) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(25) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(24) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(23) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(22) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(21) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(20) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(19) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(18) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(17) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(16) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(15) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(14) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(13) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(12) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(11) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(10) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(9) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(8) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(7) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(6) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(5) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(4) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(3) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(2) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(1) -radix hexadecimal} {/lcdcontroller_tb/I_dut/pixelData(0) -radix hexadecimal}} -radixshowbase 0 -subitemconfig {/lcdcontroller_tb/I_dut/pixelData(47) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(46) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(45) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(44) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(43) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(42) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(41) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(40) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(39) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(38) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(37) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(36) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(35) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(34) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(33) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(32) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(31) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(30) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(29) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(28) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(27) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(26) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(25) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(24) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(23) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(22) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(21) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(20) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(19) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(18) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(17) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(16) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(15) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(14) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(13) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(12) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(11) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(10) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(9) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(8) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(7) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(6) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(5) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(4) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(3) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(2) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(1) {-height 16 -radix hexadecimal -radixshowbase 0} /lcdcontroller_tb/I_dut/pixelData(0) {-height 16 -radix hexadecimal -radixshowbase 0}} /lcdcontroller_tb/I_dut/pixelData +add wave -noupdate -group {Font encoder} -radix hexadecimal -radixshowbase 0 /lcdcontroller_tb/I_dut/lcdData1 +add wave -noupdate -group Initialization -radix unsigned -radixshowbase 0 /lcdcontroller_tb/I_dut/I_ser/resetCounter +add wave -noupdate -group Initialization -radix unsigned -radixshowbase 0 /lcdcontroller_tb/I_dut/I_init/initSequenceCounter +add wave -noupdate -group Initialization /lcdcontroller_tb/I_dut/I_init/initSequenceDone +add wave -noupdate -group Initialization /lcdcontroller_tb/I_dut/lcdBusy +add wave -noupdate -group Serializer -radix hexadecimal -radixshowbase 0 /lcdcontroller_tb/I_dut/lcdData +add wave -noupdate -group Serializer /lcdcontroller_tb/I_dut/lcdSend +add wave -noupdate -group Serializer /lcdcontroller_tb/I_dut/lcdBusy +add wave -noupdate -expand -group {LCD interface} /lcdcontroller_tb/RST_n +add wave -noupdate -expand -group {LCD interface} /lcdcontroller_tb/A0 +add wave -noupdate -expand -group {LCD interface} /lcdcontroller_tb/CS1_n +add wave -noupdate -expand -group {LCD interface} /lcdcontroller_tb/SCL +add wave -noupdate -expand -group {LCD interface} /lcdcontroller_tb/SI +add wave -noupdate -radix unsigned -radixshowbase 0 /lcdcontroller_tb/I_dut/I_init/clearSequenceCounter +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 375 +configure wave -valuecolwidth 58 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {48300 ns} diff --git a/Libs/Lcd_test/sim/lcdDemo.do b/Libs/Lcd_test/sim/lcdDemo.do new file mode 100644 index 0000000..dfdfbbb --- /dev/null +++ b/Libs/Lcd_test/sim/lcdDemo.do @@ -0,0 +1,71 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /lcddemo_tb/reset +add wave -noupdate /lcddemo_tb/clock +add wave -noupdate -divider Controls +add wave -noupdate -radix hexadecimal /lcddemo_tb/leds +add wave -noupdate -radix hexadecimal /lcddemo_tb/buttons +add wave -noupdate -divider UART +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/dataout +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/datavalid +add wave -noupdate -divider Test +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/send_int +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/busy_int +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/ascii_int +add wave -noupdate -divider {ASCII data} +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/ascii +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/send +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/busy +add wave -noupdate -divider Encoder +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/asciisend +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/asciibusy +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/asciidata +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_font/asciibitnb +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_font/lcdcolumnnb +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_font/lcddatabitnb +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_font/lcdpagenb +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_font/fontrownb +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_font/fontcolumnnb +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/fontdisplaystate +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/asciicolumncounter +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_font/columncounter +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_font/pagecounter +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_font/pixeloffset +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/pixeldata +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/a0 +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/cleardisplay +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/lcdsend +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/lcdbusy +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/i_font/lcddata +add wave -noupdate -divider Initialization +add wave -noupdate /lcddemo_tb/i_dut/i_lcd/i_init/cleardisplay +add wave -noupdate /lcddemo_tb/i_dut/i_lcd/i_init/initsequencedone +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_init/initsequencecounter +add wave -noupdate /lcddemo_tb/i_dut/i_lcd/i_init/clearsequencedone +add wave -noupdate -radix unsigned /lcddemo_tb/i_dut/i_lcd/i_init/clearsequencecounter +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/lcdsend +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/lcdbusy +add wave -noupdate -radix hexadecimal /lcddemo_tb/i_dut/i_lcd/lcddata +add wave -noupdate -divider LCD +add wave -noupdate /lcddemo_tb/rst_n +add wave -noupdate /lcddemo_tb/a0 +add wave -noupdate /lcddemo_tb/cs1_n +add wave -noupdate /lcddemo_tb/scl +add wave -noupdate /lcddemo_tb/si +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 350 +configure wave -valuecolwidth 58 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {31265344 ps} diff --git a/Libs/Lcd_test/sim/lcdFont.txt b/Libs/Lcd_test/sim/lcdFont.txt new file mode 100644 index 0000000..2ab4422 --- /dev/null +++ b/Libs/Lcd_test/sim/lcdFont.txt @@ -0,0 +1,128 @@ +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +000000000000000000000000000000000000000000000000 +000000000000000001001111000000000000000000000000 +000000000000011100000000000001110000000000000000 +000101000111111100010100011111110001010000000000 +001001000010101001111111001010100001001000000000 +001000110001001100001000011001000110001000000000 +001101100100100101010101001000100101000000000000 +000000000000010100000011000000000000000000000000 +000000000001110000100010010000010000000000000000 +000000000100000100100010000111000000000000000000 +000101000000100000111110000010000001010000000000 +000010000000100000111110000010000000100000000000 +000000000101000000110000000000000000000000000000 +000010000000100000001000000010000000100000000000 +000000000110000001100000000000000000000000000000 +001000000001000000001000000001000000001000000000 +001111100101000101001001010001010011111000000000 +000000000100001001111111010000000000000000000000 +010000100110000101010001010010010100011000000000 +001000010100000101000101010010110011000100000000 +000110000001010000010010011111110001000000000000 +001001110100010101000101010001010011100100000000 +001111000100101001001001010010010011000000000000 +000000010111000100001001000001010000001100000000 +001101100100100101001001010010010011011000000000 +000001100100100101001001001010010001111000000000 +000000000011011000110110000000000000000000000000 +000000000101011000110110000000000000000000000000 +000010000001010000100010010000010000000000000000 +000101000001010000010100000101000001010000000000 +000000000100000100100010000101000000100000000000 +000000100000000101010001000010010000011000000000 +001100100100100101111001010000010011111000000000 +011111100001000100010001000100010111111000000000 +011111110100100101001001010010010011011000000000 +001111100100000101000001010000010010001000000000 +011111110100000101000001001000100001110000000000 +011111110100100101001001010010010100000100000000 +011111110000100100001001000010010000000100000000 +001111100100000101001001010010010111101000000000 +011111110000100000001000000010000111111100000000 +000000000100000101111111010000010000000000000000 +001000000100000001000001001111110000000100000000 +011111110000100000010100001000100100000100000000 +011111110100000001000000010000000100000000000000 +011111110000001000001100000000100111111100000000 +011111110000010000001000000100000111111100000000 +001111100100000101000001010000010011111000000000 +011111110000100100001001000010010000011000000000 +001111100100000101010001001000010101111000000000 +011111110000100100011001001010010100011000000000 +010001100100100101001001010010010011000100000000 +000000010000000101111111000000010000000100000000 +001111110100000001000000010000000011111100000000 +000111110010000001000000001000000001111100000000 +001111110100000000111000010000000011111100000000 +011000110001010000001000000101000110001100000000 +000001110000100001110000000010000000011100000000 +011000010101000101001001010001010100001100000000 +000000000111111101000001010000010000000000000000 +000101010001011001111100000101100001010100000000 +000000000100000101000001011111110000000000000000 +000001000000001000000001000000100000010000000000 +010000000100000001000000010000000100000000000000 +000000000000000100000010000001000000000000000000 +001000000101010001010100010101000111100000000000 +011111110100100001000100010001000011100000000000 +001110000100010001000100010001000010000000000000 +001110000100010001000100010010000111111100000000 +001110000101010001010100010101000001100000000000 +000010000111111000001001000000010000001000000000 +000011000101001001010010010100100011111000000000 +011111110000100000000100000001000111100000000000 +000000000100010001111101010000000000000000000000 +001000000100000001000100001111010000000000000000 +011111110001000000101000010001000000000000000000 +000000000100000101111111010000000000000000000000 +011111000000010000011000000001000111100000000000 +011111000000100000000100000001000111100000000000 +001110000100010001000100010001000011100000000000 +011111000001010000010100000101000000100000000000 +000010000001010000010100000110000111110000000000 +011111000000100000000100000001000000100000000000 +010010000101010001010100010101000010000000000000 +000001000011111101000100010000000010000000000000 +001111000100000001000000001000000111110000000000 +000111000010000001000000001000000001110000000000 +001111000100000000110000010000000011110000000000 +010001000010100000010000001010000100010000000000 +000011000101000001010000010100000011110000000000 +010001000110010001010100010011000100010000000000 +000000000000100000110110010000010000000000000000 +000000000000000001111111000000000000000000000000 +000000000100000100110110000010000000000000000000 +000010000000100000101010000111000000100000000000 +000010000001110000101010000010000000100000000000 diff --git a/Libs/Lcd_test/sim/lcdSerializer.do b/Libs/Lcd_test/sim/lcdSerializer.do new file mode 100644 index 0000000..91a8d4f --- /dev/null +++ b/Libs/Lcd_test/sim/lcdSerializer.do @@ -0,0 +1,43 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group {Reset and clock} /lcddemo_tb/reset +add wave -noupdate -expand -group {Reset and clock} /lcddemo_tb/clock +add wave -noupdate -group {Buttons and LEDs} -radix hexadecimal -childformat {{/lcddemo_tb/buttons(1) -radix hexadecimal} {/lcddemo_tb/buttons(2) -radix hexadecimal} {/lcddemo_tb/buttons(3) -radix hexadecimal} {/lcddemo_tb/buttons(4) -radix hexadecimal}} -expand -subitemconfig {/lcddemo_tb/buttons(1) {-height 16 -radix hexadecimal} /lcddemo_tb/buttons(2) {-height 16 -radix hexadecimal} /lcddemo_tb/buttons(3) {-height 16 -radix hexadecimal} /lcddemo_tb/buttons(4) {-height 16 -radix hexadecimal}} /lcddemo_tb/buttons +add wave -noupdate -group {Buttons and LEDs} -radix hexadecimal -childformat {{/lcddemo_tb/leds(1) -radix hexadecimal} {/lcddemo_tb/leds(2) -radix hexadecimal} {/lcddemo_tb/leds(3) -radix hexadecimal} {/lcddemo_tb/leds(4) -radix hexadecimal} {/lcddemo_tb/leds(5) -radix hexadecimal} {/lcddemo_tb/leds(6) -radix hexadecimal} {/lcddemo_tb/leds(7) -radix hexadecimal} {/lcddemo_tb/leds(8) -radix hexadecimal}} -expand -subitemconfig {/lcddemo_tb/leds(1) {-height 16 -radix hexadecimal} /lcddemo_tb/leds(2) {-height 16 -radix hexadecimal} /lcddemo_tb/leds(3) {-height 16 -radix hexadecimal} /lcddemo_tb/leds(4) {-height 16 -radix hexadecimal} /lcddemo_tb/leds(5) {-height 16 -radix hexadecimal} /lcddemo_tb/leds(6) {-height 16 -radix hexadecimal} /lcddemo_tb/leds(7) {-height 16 -radix hexadecimal} /lcddemo_tb/leds(8) {-height 16 -radix hexadecimal}} /lcddemo_tb/leds +add wave -noupdate -expand -group {Hello message} /lcddemo_tb/I_dut/I_hello/buttonRising +add wave -noupdate -expand -group {Hello message} -radix unsigned -radixshowbase 0 /lcddemo_tb/I_dut/I_hello/sequenceCounter +add wave -noupdate -expand -group {Hello message} /lcddemo_tb/I_dut/I_hello/sequenceDone +add wave -noupdate -expand -group {Hello message} /lcddemo_tb/I_dut/helloSend +add wave -noupdate -expand -group {Hello message} -radix hexadecimal -radixshowbase 0 /lcddemo_tb/I_dut/helloData +add wave -noupdate -expand -group {Hello message} -radix ascii -radixshowbase 0 /lcddemo_tb/I_dut/helloData +add wave -noupdate -expand -group {Hello message} /lcddemo_tb/I_dut/helloBusy +add wave -noupdate -expand -group UART /lcddemo_tb/I_tester/rs232OutByte +add wave -noupdate -expand -group UART /lcddemo_tb/I_tester/rs232SendOutByte +add wave -noupdate -expand -group UART /lcddemo_tb/I_dut/RxD +add wave -noupdate -group {LCD controller interface} -radix hexadecimal -radixshowbase 0 /lcddemo_tb/I_dut/ascii +add wave -noupdate -group {LCD controller interface} -radix ascii -radixshowbase 0 /lcddemo_tb/I_dut/ascii +add wave -noupdate -group {LCD controller interface} -radix hexadecimal /lcddemo_tb/I_dut/send +add wave -noupdate -group {LCD controller interface} -radix hexadecimal /lcddemo_tb/I_dut/busy +add wave -noupdate -expand -group {LCD interface} /lcddemo_tb/RST_n +add wave -noupdate -expand -group {LCD interface} /lcddemo_tb/A0 +add wave -noupdate -expand -group {LCD interface} /lcddemo_tb/CS1_n +add wave -noupdate -expand -group {LCD interface} /lcddemo_tb/SCL +add wave -noupdate -expand -group {LCD interface} /lcddemo_tb/SI +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 350 +configure wave -valuecolwidth 58 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {2527664378 ps} diff --git a/Libs/Lcd_test/st7565r.pdf b/Libs/Lcd_test/st7565r.pdf new file mode 100644 index 0000000..de467bb Binary files /dev/null and b/Libs/Lcd_test/st7565r.pdf differ diff --git a/Libs/Memory/hdl/bramDualportWritefirst_bhv.vhd b/Libs/Memory/hdl/bramDualportWritefirst_bhv.vhd new file mode 100644 index 0000000..09bf83a --- /dev/null +++ b/Libs/Memory/hdl/bramDualportWritefirst_bhv.vhd @@ -0,0 +1,54 @@ +USE std.textio.all; + +ARCHITECTURE bhv OF bramDualportWritefirst IS + -- Define ramContent type + type ramContentType is array(0 to (2**addressBitNb)-1) of bit_vector(dataBitNb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(initFile); + +BEGIN + -- Port A + process(clockA) + begin + if clockA'event and clockA='1' then + if enA = '1' then + if writeEnA = '1' then + dataOutA <= dataInA; + ramContent(to_integer(unsigned(addressA))) := to_bitvector(dataInA,'0'); + else + dataOutA <= to_stdulogicvector(ramContent(to_integer(unsigned(addressA)))); + end if; + end if; + end if; + end process; + + -- Port B + process(clockB) + begin + if clockB'event and clockB='1' then + if enB = '1' then +-- if writeEnB = '1' then +-- ramContent(to_integer(unsigned(addressB))) := to_bitvector(dataInB,'0'); +-- dataOutB <= dataInB; +-- else + dataOutB <= to_stdulogicvector(ramContent(to_integer(unsigned(addressB)))); +-- end if; + end if; + end if; + end process; + +END ARCHITECTURE bhv; diff --git a/Libs/Memory/hdl/bram_bhv.vhd b/Libs/Memory/hdl/bram_bhv.vhd new file mode 100644 index 0000000..f0f92f5 --- /dev/null +++ b/Libs/Memory/hdl/bram_bhv.vhd @@ -0,0 +1,39 @@ +USE std.textio.all; + +ARCHITECTURE bhv OF bram IS + -- Define ramContent type + type ramContentType is array(0 to (2**addressBitNb)-1) of bit_vector(dataBitNb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(initFile); + +BEGIN + -- Port A + process(clock) + begin + if clock'event and clock='1' then + if en = '1' then + if writeEn = '1' then + dataOut <= dataIn; + ramContent(to_integer(unsigned(addressIn))) := to_bitvector(dataIn,'0'); + else + dataOut <= to_stdulogicvector(ramContent(to_integer(unsigned(addressIn)))); + end if; + end if; + end if; + end process; + +END ARCHITECTURE bhv; diff --git a/Libs/Memory/hdl/bram_dualport_writefirst.vhd b/Libs/Memory/hdl/bram_dualport_writefirst.vhd new file mode 100644 index 0000000..8fd72bf --- /dev/null +++ b/Libs/Memory/hdl/bram_dualport_writefirst.vhd @@ -0,0 +1,55 @@ +USE std.textio.all; + +ARCHITECTURE bhv OF bramContentDualportWritefirst IS + -- Define ramContent type + type ramContentType is array(0 to (2**addr_bit_nb)-1) of bit_vector(data_bit_nb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(init_file); + +BEGIN + -- Port A + process(clockA) + begin + if clockA'event and clockA='1' then + if enA = '1' then + if writeEnA = '1' then + dataOutA <= dataInA; + ramContent(to_integer(unsigned(addressA))) := to_bitvector(dataInA,'0'); + else + dataOutA <= to_stdulogicvector(ramContent(to_integer(unsigned(addressA)))); + end if; + end if; + end if; + end process; + + -- Port B + process(clockB) + begin + if clockB'event and clockB='1' then + if enB = '1' then + if writeEnB = '1' then + ramContent(to_integer(unsigned(addressB))) := to_bitvector(dataInB,'0'); + dataOutB <= dataInB; + else + dataOutB <= to_stdulogicvector(ramContent(to_integer(unsigned(addressB)))); + end if; + end if; + end if; + end process; + +END ARCHITECTURE bhv; + diff --git a/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd b/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd new file mode 100644 index 0000000..9773ce4 --- /dev/null +++ b/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd @@ -0,0 +1,73 @@ +-- ------------------------------------------------------------------------------ +-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch) +-- ------------------------------------------------------------------------------ +-- FIFO bridge with bus width adaption +-- A shift register that connects two FIFOs with different bus width. +-- Many IP blocks nowadays have FIFO or FIFO-like interfaces and often they +-- have to be connected. This block can the be used for this task, even if +-- the bus size of the two FIFO interfaces is different. +-- The Rx side bus width has to be a multiple of the Tx side bus width. +-- +-- Created on 2013-10-18 +-- +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-- +-- 2014-10-06: *modify introduction text +-- +add some comment +-- *change readRx to a pulse +-- *fix bug on shift of shiftreg_s +-- 2013-10-18: +intital release +-- ------------------------------------------------------------------------------ +-- + +library Common; + use Common.CommonLib.all; + +ARCHITECTURE behavioral OF fifoBridgeRxToTxBusWidthAdaptionRxBigger IS + + signal cnt_s: unsigned(requiredBitNb(dataBitNbRx)-1 downto 0); + signal shiftreg_s: std_ulogic_vector(dataBitNbRx-1 downto 0); + signal emptyRx_s: std_ulogic; -- internal empty signal + signal writeTx_s: std_ulogic; -- internal write signal + + constant ratio_rxtx_c: positive range 1 to dataBitNbRx/dataBitNbTx:= dataBitNbRx/dataBitNbTx; + +BEGIN + + rx0: process(clock, reset) + begin + if reset = '1' then + shiftreg_s <= (others => '0'); + emptyRx_s <= '1'; + cnt_s <= (others => '0'); + writeTx_s <= '0'; + dataTx <= (others => '0'); + readRx <= '0'; + elsif rising_edge(clock) then + writeTx_s <= '0'; + readRx <= '0'; + -- fetch data + if emptyRx_s = '1' and emptyRx = '0' then + emptyRx_s <= '0'; + shiftreg_s <= dataRx; + readRx <= '1'; + end if; + -- shift data and put out + -- after each write, wait one cylce to check if full gets high + if emptyRx_s = '0' and fullTx = '0' and writeTx_s = '0' then + shiftreg_s <= shiftreg_s(dataBitNbRx-dataBitNbTx-1 downto 0) & std_ulogic_vector(to_unsigned(0,dataBitNbTx)); + dataTx <= shiftreg_s(dataBitNbRx-1 downto dataBitNbRx-dataBitNbTx); + writeTx_s <= '1'; + cnt_s <= cnt_s +1; + if cnt_s >= ratio_rxtx_c-1 then + cnt_s <= (others => '0'); + emptyRx_s <= '1'; + end if; + end if; + end if; + end process; + + writeTx <= writeTx_s; + +END ARCHITECTURE behavioral; + diff --git a/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd b/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd new file mode 100644 index 0000000..c6217f8 --- /dev/null +++ b/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd @@ -0,0 +1,75 @@ +-- ------------------------------------------------------------------------------ +-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch) +-- ------------------------------------------------------------------------------ +-- FIFO bridge with bus width adaption +-- A shift register that connects two FIFOs with different bus width. +-- Many IP blocks nowadays have FIFO or FIFO-like interface. But the bus width +-- varies often. This block can the be used to adapt the bus width to your own +-- needs. +-- The Tx side bus width has to be a multiple of the Rx side bus width. +-- +-- Created on 2013-10-21 +-- +-- Version: 1.0 +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-- ------------------------------------------------------------------------------ +-- + +library common; + use common.commonlib.all; + +ARCHITECTURE behavioral OF fifoBridgeRxToTxBusWidthAdaptionTxbigger IS + + constant ratio_txrx_c: positive range 1 to dataBitNbTx/dataBitNbRx:= dataBitNbTx/dataBitNbRx; + + signal cnt_s: unsigned(requiredBitNb(ratio_txrx_c-1)-1 downto 0); + signal shiftreg_s: std_ulogic_vector(dataBitNbTx-1 downto 0); + signal fullTx_s: std_ulogic; + signal emptyRx_s: std_ulogic; + +BEGIN + + rx0: process(clock, reset) + begin + if reset = '1' then + shiftreg_s <= (others => '0'); + readRx <= '1'; + emptyRx_s <= '1'; + cnt_s <= (others => '0'); + elsif rising_edge(clock) then + readRx <= NOT fullTx_s; + emptyRx_s <= '1'; + if emptyRx = '0' and fullTx_s = '0' then +-- shiftreg_s(((to_integer(cnt_s)+1)*dataBitNbRx)-1 downto to_integer(cnt_s)*dataBitNbRx) <= dataRx; + shiftreg_s <= shiftreg_s(dataBitNbTx-dataBitNbRx-1 downto 0) & dataRx; + readRx <= '1'; + cnt_s <= cnt_s +1; + if cnt_s >= ratio_txrx_c-1 then + cnt_s <= (others => '0'); + emptyRx_s <= '0'; + end if; + end if; + end if; + end process; + + tx0: process(clock, reset) + begin + if reset = '1' then + fullTx_s <= '1'; + writeTx <= '0'; + dataTx <= (others => '0'); + elsif rising_edge(clock) then + fullTx_s <= fullTx; + writeTx <= '0'; + -- no need to wait to check for full (in contrast to RxBigger) + -- because it will forcibly take several clocks to fill the shiftreg + if emptyRx_s = '0' and fullTx = '0' then + dataTx <= shiftreg_s; + writeTx <= '1'; + end if; + end if; + end process; + +END ARCHITECTURE behavioral; + + diff --git a/Libs/Memory/hdl/fifo_bram_rtl.vhd b/Libs/Memory/hdl/fifo_bram_rtl.vhd new file mode 100644 index 0000000..83336ca --- /dev/null +++ b/Libs/Memory/hdl/fifo_bram_rtl.vhd @@ -0,0 +1,165 @@ +library Common; + use Common.CommonLib.all; + +architecture RTL of FIFO_bram is + + subtype register_type is std_ulogic_vector(dataIn'high downto 0); + type memory_type is array (0 to depth-1) of register_type; + + signal writeCounter: unsigned(requiredBitNb(depth-1)-1 downto 0); + signal readCounter: unsigned(writeCounter'range); + signal memoryArray: memory_type; + + type fifoStateType is ( + sEmpty, sFull, + sRead, sWrite, sWriteFirst, + sReadWrite, sWait + ); + signal fifoState: fifoStateType; + signal emptyCondition, fullCondition, empty_int: std_ulogic; + +begin + ------------------------------------------------------------------------------ + -- read and write counters + updateWriteCounter: process(reset, clock) + begin + if reset = '1' then + writeCounter <= (others => '0'); + elsif rising_edge(clock) then + if (write = '1') and (fullCondition = '0') then + writeCounter <= writeCounter + 1; + end if; + end if; + end process updateWriteCounter; + + updateReadCounter: process(reset, clock) + begin + if reset = '1' then + readCounter <= (others => '0'); + elsif rising_edge(clock) then + if (read = '1') and (empty_int = '0') then + readCounter <= readCounter + 1; + end if; + end if; + end process updateReadCounter; + + ------------------------------------------------------------------------------ + -- memory access + writeMem: process(clock) + begin + if rising_edge(clock) then + if (write = '1') and (fullCondition = '0') then + memoryArray(to_integer(writeCounter)) <= dataIn; + end if; + end if; + end process writeMem; + + readMem: process(reset, clock) + begin + if reset = '1' then + dataOut <= (others => '0'); + elsif rising_edge(clock) then + if (read = '0') or (empty_int = '1') then + dataOut <= memoryArray(to_integer(readCounter)); + else + dataOut <= memoryArray(to_integer(readCounter+1)); + end if; + end if; + end process readMem; + + ------------------------------------------------------------------------------ + -- controls + emptyCondition <= '1' when + ( (fifoState = sRead) and (writeCounter = readCounter) ) or + (fifoState = sEmpty) + else '0'; + + fullCondition <= '1' when + ( (fifoState = sWrite) and (writeCounter = readCounter) ) or + (fifoState = sFull) + else '0'; + + + fifoControl: process(reset, clock) + begin + if reset = '1' then + fifoState <= sEmpty; + elsif rising_edge(clock) then + case fifoState is + when sEmpty => + if write = '1' then + fifoState <= sWriteFirst; + end if; + when sFull => + if (read = '1') then + fifoState <= sRead; + end if; + when sRead => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif write = '1' then + fifoState <= sWrite; + elsif emptyCondition = '1' then + fifoState <= sEmpty; + elsif read = '1' then + fifoState <= sRead; + else + fifoState <= sWait; + end if; + when sWriteFirst => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif write = '1' then + fifoState <= sWrite; + elsif read = '1' then + fifoState <= sRead; + else + fifoState <= sWait; + end if; + when sWrite => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif read = '1' then + fifoState <= sRead; + elsif fullCondition = '1' then + fifoState <= sFull; + elsif write = '1' then + fifoState <= sWrite; + else + fifoState <= sWait; + end if; + when sReadWrite => + if (read = '0') and (write = '0') then + fifoState <= sWait; + elsif (read = '1') and (write = '0') then + fifoState <= sRead; + elsif (write = '1') and (read = '0') then + fifoState <= sWrite; + end if; + when sWait => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif read = '1' then + fifoState <= sRead; + elsif write = '1' then + fifoState <= sWrite; + end if; + when others => null; + end case; + end if; + end process fifoControl; + + + full <= '1' when + (fifoState = sFull) or + (fullCondition = '1') + else '0'; + + empty_int <= '1' when + (fifoState = sEmpty) or + (fifoState = sWriteFirst) or + ( (emptyCondition = '1') and (fifoState = sRead) ) + else '0'; + empty <= empty_int; + +end RTL; diff --git a/Libs/Memory/hdl/fifo_minimal.vhd b/Libs/Memory/hdl/fifo_minimal.vhd new file mode 100644 index 0000000..915866c --- /dev/null +++ b/Libs/Memory/hdl/fifo_minimal.vhd @@ -0,0 +1,63 @@ +library Common; + use Common.CommonLib.all; + +architecture minimal of FIFO_bram is + + subtype register_type is std_ulogic_vector(dataIn'high downto 0); + type memory_type is array (0 to depth-1) of register_type; + + signal writeCounter: unsigned(requiredBitNb(depth)-1 downto 0); + signal readCounter: unsigned(writeCounter'range); + signal memoryArray : memory_type; + +begin + + updateWriteCounter: process(reset, clock) + begin + if reset = '1' then + writeCounter <= (others => '0'); + elsif rising_edge(clock) then + if write = '1' then + writeCounter <= writeCounter + 1; + end if; + end if; + end process updateWriteCounter; + + updateReadCounter: process(reset, clock) + begin + if reset = '1' then + readCounter <= (others => '0'); + elsif rising_edge(clock) then + if read = '1' then + readCounter <= readCounter + 1; + end if; + end if; + end process updateReadCounter; + + writeMem: process(clock) + begin + if rising_edge(clock) then + if write = '1' then + memoryArray(to_integer(writeCounter)) <= dataIn; + end if; + end if; + end process writeMem; + + dataOut <= memoryArray(to_integer(readCounter)); + + checkStatus: process(readCounter, writeCounter) + begin + if readCounter = writeCounter then + empty <= '1'; + else + empty <= '0'; + end if; + if writeCounter+1 = readCounter then + full <= '1'; + else + full <= '0'; + end if; + end process checkStatus; + +end minimal; + diff --git a/Libs/Memory/hdl/fifo_oneRegister_rtl.vhd b/Libs/Memory/hdl/fifo_oneRegister_rtl.vhd new file mode 100644 index 0000000..244749d --- /dev/null +++ b/Libs/Memory/hdl/fifo_oneRegister_rtl.vhd @@ -0,0 +1,37 @@ +architecture oneRegister of FIFO_oneRegister is + + signal dataRegister: std_ulogic_vector(dataIn'range); + +begin + + writeReg: process(reset, clock) + begin + if reset = '1' then + dataRegister <= (others => '0'); + elsif rising_edge(clock) then + if write = '1' then + dataRegister <= dataIn; + end if; + end if; + end process writeReg; + + dataOut <= dataRegister; + + manageFlags: process(reset, clock) + begin + if reset = '1' then + empty <= '1'; + full <= '0'; + elsif rising_edge(clock) then + if write = '1' then + empty <= '0'; + full <= '1'; + elsif read = '1' then + empty <= '1'; + full <= '0'; + end if; + end if; + end process manageFlags; + +end oneRegister; + diff --git a/Libs/Memory/hdl/fifo_pim.vhd b/Libs/Memory/hdl/fifo_pim.vhd new file mode 100644 index 0000000..81006e3 --- /dev/null +++ b/Libs/Memory/hdl/fifo_pim.vhd @@ -0,0 +1,118 @@ +library Common; + use Common.CommonLib.all; + +architecture pim of FIFO_bram is + + type mem_t is array (depth-1 downto 0) of std_ulogic_vector(dataIn'range); + subtype mem_range_r is natural range requiredBitNb(depth)-1 downto 0; + subtype ptr_range_r is natural range requiredBitNb(depth)+1-1 downto 0; + + signal mem : mem_t := (others => (others => '0')); + + signal full_int : std_logic; + signal empty_int : std_logic; + signal write_error : std_logic; + signal read_error : std_logic; + signal read_ptr : unsigned(ptr_range_r); + signal read_ptr_next : unsigned(ptr_range_r); + signal write_ptr : unsigned(ptr_range_r); + signal write_ptr_next : unsigned(ptr_range_r); + + signal used_int : unsigned(ptr_range_r); + +begin + ----------------------------------------------------------------------------- + -- Free / used + ----------------------------------------------------------------------------- + + fifo_count_proc: process(reset, clock) + begin + if reset = '1' then + used_int <= (others => '0'); + elsif rising_edge(clock) then + if write = '1' and full_int = '0' then + used_int <= used_int + 1; + end if; + if read = '1' and empty_int = '0' then + used_int <= used_int - 1; + end if; + + -- Simultaneous read/write -> no change + -- ignore full_int, since it is valid + if write = '1' and read = '1' and empty_int = '0' then + used_int <= used_int; + end if; + end if; + end process; + + + ----------------------------------------------------------------------------- + -- FIFO status + ----------------------------------------------------------------------------- + + full_int <= '1' when (write_ptr(write_ptr'left) /= read_ptr(read_ptr'left)) + and ((write_ptr(mem_range_r) = read_ptr(mem_range_r))) + else '0'; + empty_int <= '1' when (write_ptr = read_ptr) else '0'; + + full <= full_int; + empty <= empty_int; + + write_ptr_next <= write_ptr + 1; + read_ptr_next <= read_ptr + 1; + + + ----------------------------------------------------------------------------- + -- FIFO pointers + ----------------------------------------------------------------------------- + + fifo_ptr_proc: process(reset, clock) + begin + if reset = '1' then + write_ptr <= (others => '0'); + read_ptr <= (others => '0'); + write_error <= '0'; + read_error <= '0'; + elsif rising_edge(clock) then + write_error <= '0'; + read_error <= '0'; + if write = '1' then + if full_int = '0' or read = '1' then + write_ptr <= write_ptr_next; + else + write_error <= '1'; + end if; + end if; + if read = '1' then + if empty_int = '0' then + read_ptr <= read_ptr_next; + else + read_error <= '1'; + end if; + end if; + end if; + end process; + + + ----------------------------------------------------------------------------- + -- FIFO RAM + ----------------------------------------------------------------------------- + + fifo_out_proc : process(clock) + begin + if rising_edge(clock) then + dataOut <= mem(to_integer(read_ptr(mem_range_r))); + end if; + end process; + + fifo_in_proc : process(clock) + begin + if rising_edge(clock) then + if write = '1' and full_int = '0' then + mem(to_integer(write_ptr(mem_range_r))) <= dataIn; + end if; + end if; + end process; + +end pim; + diff --git a/Libs/Memory/hdl/fifo_rtl_minimal.vhd b/Libs/Memory/hdl/fifo_rtl_minimal.vhd new file mode 100644 index 0000000..6fcccc8 --- /dev/null +++ b/Libs/Memory/hdl/fifo_rtl_minimal.vhd @@ -0,0 +1,97 @@ +-- +-- VHDL Architecture Memory.fifo_minimal +-- +-- Created: +-- by - uadmin.UNKNOWN (WE3877) +-- at - 13:54:33 11.07.2012 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10) +-- +library Common; + use Common.CommonLib.all; + +architecture RTL_minimal of FIFO is + + subtype register_type is std_ulogic_vector(dataIn'high downto 0); + type memory_type is array (0 to depth-1) of register_type; + + signal writeCounter: unsigned(requiredBitNb(depth)-1 downto 0); + signal readCounter: unsigned(writeCounter'range); + signal memoryArray : memory_type; + +begin + + updateWriteCounter: process(reset, clock) + begin + if reset = '1' then + writeCounter <= (others => '0'); + elsif rising_edge(clock) then + if write = '1' then + writeCounter <= writeCounter + 1; + end if; + end if; + end process updateWriteCounter; + + updateReadCounter: process(reset, clock) + begin + if reset = '1' then + readCounter <= (others => '0'); + elsif rising_edge(clock) then + if read = '1' then + readCounter <= readCounter + 1; + end if; + end if; + end process updateReadCounter; + + writeMem: process(clock) + begin + if rising_edge(clock) then + if write = '1' then + memoryArray(to_integer(writeCounter)) <= dataIn; + end if; + end if; + end process writeMem; + + dataOut <= memoryArray(to_integer(readCounter)); + +-- checkStatus: process(reset, clock) +-- begin +-- if reset = '1' then +-- empty <= '1'; +-- full <= '0'; +-- elsif rising_edge(clock) then +-- if readCounter+1 = writeCounter then +-- if read = '1' then +-- empty <= '1'; +-- end if; +-- elsif writeCounter = readCounter then +-- if write = '1' then +-- empty <= '0'; +-- end if; +-- if read = '1' then +-- full <= '0'; +-- end if; +-- elsif writeCounter+1 = readCounter then +-- if write = '1' then +-- full <= '1'; +-- end if; +-- end if; +-- end if; +-- end process checkStatus; + + checkStatus: process(readCounter, writeCounter) + begin + if readCounter = writeCounter then + empty <= '1'; + else + empty <= '0'; + end if; + if writeCounter+1 = readCounter then + full <= '1'; + else + full <= '0'; + end if; + end process checkStatus; + +END ARCHITECTURE RTL_minimal; + diff --git a/Libs/Memory/hdl/fifobridgerxtotx_rtl.vhd b/Libs/Memory/hdl/fifobridgerxtotx_rtl.vhd new file mode 100644 index 0000000..5c20654 --- /dev/null +++ b/Libs/Memory/hdl/fifobridgerxtotx_rtl.vhd @@ -0,0 +1,84 @@ +-- ------------------------------------------------------------------------------ +-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch) +-- ------------------------------------------------------------------------------ +-- FIFO bridge with bus width adaptation +-- A register that connects two FIFOs. +-- Many IP blocks nowadays have FIFO or FIFO-like interfaces and often they +-- have to be connected. This block can the be used for this task. +-- +-- Created on 2012 +-- +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-- +-- 2016-04-01: fix bug in FWFT read when full +-- 2016-03-22: +add FirstWordFallThrough (FWFT) generic +-- 2012: +intital release +-- ------------------------------------------------------------------------------ +-- + +ARCHITECTURE RTL OF fifoBridgeRxToTx IS + + signal read1: std_ulogic; + signal read2: std_ulogic; + signal read: std_ulogic; + signal storedData: std_ulogic_vector(data1'range); + signal write: std_ulogic; + +BEGIN + + readControl: process(reset, clock) + begin + if reset = '1' then + read1 <= '0'; + read2 <= '0'; + elsif rising_edge(clock) then + if (empty1 = '0') and (full2 = '0') then + read1 <= '1'; + else + read1 <= '0'; + end if; + read2 <= read1; + end if; + end process readControl; + + read <= not empty1 and not full2 when firstWordFallThrough + else not empty1 and read1; + rd1 <= read; + + readData: process(reset, clock) + begin + if reset = '1' then + storedData <= (others => '0'); + elsif rising_edge(clock) then + if firstWordFallThrough then + storedData <= data1; + else + if read = '1' then + storedData <= data1; + end if; + end if; + end if; + end process readData; + + data2 <= storedData; + + writeControl: process(reset, clock) + begin + if reset = '1' then + write <= '0'; + elsif rising_edge(clock) then + if firstWordFallThrough then + write <= not empty1 and not full2; + else + if read = '1' then + write <= '1'; + else + write <= '0'; + end if; + end if; + end if; + end process writeControl; + + wr2 <= write; + +end RTL; diff --git a/Libs/Memory/hdl/flashController_RTL.vhd b/Libs/Memory/hdl/flashController_RTL.vhd new file mode 100644 index 0000000..f8f65c4 --- /dev/null +++ b/Libs/Memory/hdl/flashController_RTL.vhd @@ -0,0 +1,140 @@ +ARCHITECTURE RTL OF flashController IS + + signal addressReg: unsigned(flashAddr'range); + signal dataOutReg: std_ulogic_vector(flashDataOut'range); + signal dataInReg: std_ulogic_vector(flashDataIn'range); + type sequenceStateType is ( + idle, + waitForBus1, waitForBus0, + startAccess, waitAcccessEnd + ); + signal sequenceState: sequenceStateType; + signal read: std_ulogic; + signal startCounter: std_ulogic; + signal sequenceCounter: unsigned(3 downto 0); + signal endOfCount: std_ulogic; + signal readDataValid: std_ulogic; + signal flashCE: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- memory reset + memRst_n <= not '0'; + + ------------------------------------------------------------------------------ + -- address + storeAddress: process(reset, clock) + begin + if reset = '1' then + addressReg <= (others => '0'); + elsif rising_edge(clock) then + if (flashRd = '1') or (flashWr = '1') then + addressReg <= shift_left(flashAddr, 1); + end if; + end if; + end process storeAddress; + + memAddress <= std_ulogic_vector(addressReg); + + ------------------------------------------------------------------------------ + -- data out + storeDataOut: process(reset, clock) + begin + if reset = '1' then + dataOutReg <= (others => '0'); + elsif rising_edge(clock) then + if flashWr = '1' then + dataOutReg <= flashDataOut; + end if; + end if; + end process storeDataOut; + + memDataOut <= flashDataOut; + + ------------------------------------------------------------------------------ + -- data in + readDataValid <= '1' when (read = '1') and (endOfCount = '1') else '0'; + + storeDataIn: process(reset, clock) + begin + if reset = '1' then + dataInReg <= (others => '0'); + elsif rising_edge(clock) then + if readDataValid = '1' then + dataInReg <= memDataIn; + end if; + end if; + end process storeDataIn; + + flashDataIn <= dataInReg when readDataValid = '0' else memDataIn; + + ------------------------------------------------------------------------------ + -- read/write sequence + busAccessFsm: process(reset, clock) + begin + if reset = '1' then + read <= '0'; + sequenceState <= idle; + elsif rising_edge(clock) then + case sequenceState is + when idle => + if flashRd = '1' then + read <= '1'; + sequenceState <= waitForBus1; + elsif flashWr = '1' then + read <= '0'; + sequenceState <= waitForBus1; + end if; + when waitForBus1 => + if memBusEn_n = '1' then + sequenceState <= waitForBus0; + end if; + when waitForBus0 => + if memBusEn_n = '0' then + sequenceState <= startAccess; + end if; + when startAccess => + sequenceState <= waitAcccessEnd; + when waitAcccessEnd => + if endOfCount = '1' then + sequenceState <= idle; + end if; + end case; + end if; + end process busAccessFsm; + + + startCounter <= '1' when sequenceState = startAccess else '0'; + endOfCount <= '1' + when ( (sequenceCounter = rdWaitState) and (read = '1') ) or + ( (sequenceCounter = wrWaitState) and (read = '0') ) + else '0'; + + countSequence: process(reset, clock) + begin + if reset = '1' then + sequenceCounter <= (others => '0'); + elsif rising_edge(clock) then + if sequenceCounter = 0 then + if startCounter = '1' then + sequenceCounter <= sequenceCounter + 1; + end if; + else + if endOfCount = '1' then + sequenceCounter <= (others => '0'); + else + sequenceCounter <= sequenceCounter + 1; + end if; + end if; + end if; + end process countSequence; + + flashCE <= '0' when sequenceCounter = 0 else '1'; + flashCE_n <= not flashCE; + memWR_n <= not '1' when (read = '0') and (flashCE = '1') and (endOfCount = '0') + else not '0'; + memOE_n <= not '1' when (read = '1') and (flashCE = '1') else not '0'; + + flashDataValid <= endOfCount; + +END ARCHITECTURE RTL; diff --git a/Libs/Memory/hdl/sdramControllerBuildAddress_RTL.vhd b/Libs/Memory/hdl/sdramControllerBuildAddress_RTL.vhd new file mode 100644 index 0000000..c2ba793 --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerBuildAddress_RTL.vhd @@ -0,0 +1,36 @@ +ARCHITECTURE RTL OF sdramControllerBuildAddress IS + + constant addressPrecharge: std_ulogic_vector(memAddress'range) + := (10=> '1', others => '-'); + constant addressModeRegU : unsigned(memAddress'range) + := resize("0" & "00" & "010" & "0" & "000", memAddress'length); + -- ll,10 = reserved, + -- 9 = '0' programmed burst length => burst length applicable for both rd and wr + -- 8,7 = Op mode = 00 => standard operation (all other states are reserved) + -- 6,5,4 = CAS latency = 010 => cas latency of 2 + -- 3 = Burst Type = '0' => Sequential (not interleaved) + -- 2,1,0 = Brust Length = 000 => brust length is 1 + constant addressModeReg : std_ulogic_vector(memAddress'range) + := std_ulogic_vector(addressModeRegU); + +BEGIN + + buildAddresses: process(ramAddr, addrSelPrecharge, addrSelModeReg, addrSelRow, addrSelCol) + begin + memBankAddress <= std_ulogic_vector(ramAddr(ramAddr'high downto ramAddr'high-memBankAddress'length+1)); + if addrSelPrecharge = '1' then + memAddress <= addressPrecharge; + elsif addrSelModeReg = '1' then + memAddress <= addressModeReg; + elsif addrSelRow = '1' then + memAddress <= std_ulogic_vector(ramAddr(rowAddressBitNb+colAddressBitNb-1 downto colAddressBitNb)); + elsif addrSelCol = '1' then + memAddress(memAddress'high downto colAddressBitNb) <= (others => '0'); + memAddress(10) <= '1'; + memAddress(colAddressBitNb-1 downto 0) <= std_ulogic_vector(ramAddr(colAddressBitNb-1 downto 0)); + else + memAddress <= (others => '-'); + end if; + end process buildAddresses; + +END ARCHITECTURE RTL; diff --git a/Libs/Memory/hdl/sdramControllerRefreshCounter_RTL.vhd b/Libs/Memory/hdl/sdramControllerRefreshCounter_RTL.vhd new file mode 100644 index 0000000..1392f04 --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerRefreshCounter_RTL.vhd @@ -0,0 +1,48 @@ +ARCHITECTURE RTL OF sdramControllerRefreshCounter IS + + signal delayCounter: unsigned(delayCounterBitNb-1 downto 0); + signal endOfDelay: std_ulogic; + +BEGIN + + countDelay : process(reset, clock) + begin + if reset = '1' then + delayCounter <= (others => '0'); + elsif rising_edge(clock) then + if endOfDelay = '1' then + delayCounter <= to_unsigned(1, delayCounter'length); + else + delayCounter <= delayCounter + 1; + end if; + end if; + end process countDelay; + + findEndOfDelay: process(powerUpDone, delayCounter) + begin + endOfDelay <= '0'; + if powerUpDone = '0' then + if delayCounter+1 = 0 then + endOfDelay <= '1'; + end if; + else + if delayCounter+1 >= refreshPeriodNb then + endOfDelay <= '1'; + end if; + end if; + end process findEndOfDelay; + + endOfRefreshCount <= endOfDelay; + + signalRefresh: process(powerUpDone, delayCounter) + begin + selectRefresh <= '0'; + if (powerUpDone = '1') and (delayCounter < 1024) then + if (delayCounter <= 16) or (delayCounter(3 downto 0) = 0) then + selectRefresh <= '1'; + end if; + end if; + end process signalRefresh; + + +END ARCHITECTURE RTL; diff --git a/Libs/Memory/hdl/sdramControllerSR_RTL.vhd b/Libs/Memory/hdl/sdramControllerSR_RTL.vhd new file mode 100644 index 0000000..2ec5bc8 --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerSR_RTL.vhd @@ -0,0 +1,18 @@ +ARCHITECTURE RTL OF sdramControllerSR IS +BEGIN + + setReset: process(reset, clock) + begin + if reset = '1' then + flag <= '0'; + elsif rising_edge(clock) then + if setFlag = '1' then + flag <= '1'; + elsif resetFlag = '1' then + flag <= '0'; + end if; + end if; + end process setReset; + +END ARCHITECTURE RTL; + diff --git a/Libs/Memory/hdl/sdramControllerSampleDataIn_RTL.vhd b/Libs/Memory/hdl/sdramControllerSampleDataIn_RTL.vhd new file mode 100644 index 0000000..29bf09f --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerSampleDataIn_RTL.vhd @@ -0,0 +1,17 @@ +ARCHITECTURE RTL OF sdramControllerSampleDataIn IS +BEGIN + + sampleRamData: process(reset, clock) + begin + if reset = '1' then + ramDataIn <= (others => '0'); + elsif falling_edge(clock) then + if sampleData = '1' then + ramDataIn <= memDataIn; + end if; + end if; + end process sampleRamData; + + +END ARCHITECTURE RTL; + diff --git a/Libs/Memory/hdl/sdramControllerStoreData_RTL.vhd b/Libs/Memory/hdl/sdramControllerStoreData_RTL.vhd new file mode 100644 index 0000000..d73bad4 --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerStoreData_RTL.vhd @@ -0,0 +1,14 @@ +ARCHITECTURE RTL OF sdramControllerStoreData IS +BEGIN + + storeData : process(reset, clock) + begin + if reset = '1' then + memDataOut <= (others => '0'); + elsif rising_edge(clock) then + memDataOut <= ramDataOut; + end if; + end process storeData; + +END ARCHITECTURE RTL; + diff --git a/Libs/Memory/hdl/sdramControllerTimingsShiftRegister_RTL.vhd b/Libs/Memory/hdl/sdramControllerTimingsShiftRegister_RTL.vhd new file mode 100644 index 0000000..352ef4a --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerTimingsShiftRegister_RTL.vhd @@ -0,0 +1,24 @@ +ARCHITECTURE RTL OF sdramControllerTimingsShiftRegister IS + + --constant leadingZeroesNb: positive := 2; + --constant leadingZeroes: std_ulogic_vector(1 to leadingZeroesNb) := (others => '0'); + --signal shiftReg: std_ulogic_vector(1 to timerDone'high-leadingZeroesNb); + signal shiftReg: std_ulogic_vector(1 to timerDone'high); + +BEGIN + + shiftToken : process(reset, clock) + begin + if reset = '1' then + shiftReg <= (others => '0'); + elsif rising_edge(clock) then + shiftReg(1) <= timerStart; + shiftReg(2 to shiftReg'right) <= shiftReg(1 to shiftReg'right-1); + end if; + end process shiftToken; + + --timerDone <= leadingZeroes & shiftReg; + timerDone <= shiftReg; + +END ARCHITECTURE RTL; + diff --git a/Libs/Memory/hds/.hdlsidedata/_bramDualportWritefirst_bhv.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bramDualportWritefirst_bhv.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bramDualportWritefirst_bhv.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bram_bhv.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bram_bhv.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bram_bhv.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bram_dualport_writefirst.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bram_dualport_writefirst.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bram_dualport_writefirst.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_bram_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_minimal.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_minimal.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_minimal.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_oneRegister_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_oneRegister_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_oneRegister_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_pim.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_pim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_pim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_rtl.vhd._fpf new file mode 100644 index 0000000..2acce3d --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_87 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_rtl_minimal.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_rtl_minimal.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_rtl_minimal.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifobridgerxtotx_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifobridgerxtotx_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifobridgerxtotx_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_flashController_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_flashController_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_flashController_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerBuildAddress_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerBuildAddress_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerBuildAddress_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerRefreshCounter_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerRefreshCounter_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerRefreshCounter_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerSR_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerSR_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerSR_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerSampleDataIn_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerSampleDataIn_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerSampleDataIn_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerStoreData_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerStoreData_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerStoreData_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerTimingsShiftRegister_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerTimingsShiftRegister_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerTimingsShiftRegister_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/@f@i@f@o/struct.bd b/Libs/Memory/hds/@f@i@f@o/struct.bd new file mode 100644 index 0000000..e7ca3f7 --- /dev/null +++ b/Libs/Memory/hds/@f@i@f@o/struct.bd @@ -0,0 +1,4408 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +frameInstances [ +(FrameInstance +name "g0" +style 1 +insts [ +(Instance +name "I1" +duLibraryName "Memory" +duName "FIFO_oneRegister" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +mwi 0 +uid 530,0 +) +] +) +(FrameInstance +name "g1" +style 1 +insts [ +(Instance +name "I0" +duLibraryName "Memory" +duName "FIFO_bram" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "depth" +type "positive" +value "depth" +) +] +mwi 0 +uid 237,0 +) +] +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.3 (Build 4)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "/home/francois/Favorites/ElN_local/ElN_inverter/Libs/Memory/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Favorites/ElN_local/ElN_inverter/Libs/Memory/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Favorites/ElN_local/ElN_inverter/Libs/Memory/hds/@f@i@f@o/struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Favorites/ElN_local/ElN_inverter/Libs/Memory/hds/@f@i@f@o/struct.bd.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Favorites/ElN_local/ElN_inverter/Libs/Memory/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Favorites/ElN_local/ElN_inverter/Libs/Memory/hds/@f@i@f@o" +) +(vvPair +variable "d_logical" +value "/home/francois/Favorites/ElN_local/ElN_inverter/Libs/Memory/hds/FIFO" +) +(vvPair +variable "date" +value "10/18/21" +) +(vvPair +variable "day" +value "Mon" +) +(vvPair +variable "day_long" +value "Monday" +) +(vvPair +variable "dd" +value "18" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "FIFO" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "10/18/21" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Hyperion" +) +(vvPair +variable "graphical_source_time" +value "10:55:04" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Hyperion" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Memory" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libraries/Memory/work" +) +(vvPair +variable "mm" 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"task_ModelSimPath" +value "C:\\eda\\MentorGraphics\\ModelSim\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "10:55:04" +) +(vvPair +variable "unit" +value "FIFO" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2019.3 (Build 4)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2021" +) +(vvPair +variable "yy" +value "21" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 148,0 +optionalChildren [ +*1 (PortIoIn +uid 9,0 +shape (CompositeShape +uid 10,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 11,0 +sl 0 +ro 270 +xt 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(MLText +uid 197,0 +va (VaSet +font "courier,8,0" +) +xt "2000,11400,17500,12300" +st "read : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "read" +t "std_ulogic" +o 5 +suid 5,0 +) +) +) +*75 (CptPort +uid 216,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 227,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33250,15625,34000,16375" +) +tg (CPTG +uid 218,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 219,0 +va (VaSet +) +xt "34999,15400,38999,16600" +st "dataIn" +blo "34999,16400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 220,0 +va (VaSet +font "courier,8,0" +) +xt "2000,12300,32000,13200" +st "dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 6 +suid 6,0 +) +) +) +*76 (CptPort +uid 221,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 228,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "50000,17625,50750,18375" +) +tg (CPTG +uid 223,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 224,0 +va (VaSet +) +xt "45200,17400,49000,18600" +st "empty" +ju 2 +blo "49000,18400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 225,0 +va (VaSet +font "courier,8,0" +) +xt "2000,13200,17500,14100" +st "empty : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "empty" +t "std_ulogic" +o 7 +suid 7,0 +) +) +) +*77 (CptPort +uid 229,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 230,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33250,17625,34000,18375" +) +tg (CPTG +uid 231,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 232,0 +va (VaSet +) +xt "35000,17400,37200,18600" +st "full" +blo "35000,18400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 233,0 +va (VaSet +font "courier,8,0" +) +xt "2000,14100,16500,15000" +st "full : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "full" +t "std_ulogic" +o 8 +suid 8,0 +) +) +) +] +shape (Rectangle +uid 81,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "34000,12000,50000,28000" +) +oxt "15000,6000,35000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +) +xt "34600,27800,38200,28800" +st "Memory" +blo "34600,28600" +) +second (Text +uid 12,0 +va (VaSet +) +xt "34600,28800,44800,29800" +st "FIFO_oneRegister" +blo "34600,29600" +) +) +gi *78 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "courier,8,0" +) +xt "34000,32000,45500,34700" +st "Generic Declarations + +dataBitNb positive 8 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "8" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sIVOD 1 +) +portVis (PortSigDisplay +sTC 0 +sIVOD 1 +) +) +*79 (Grouping +uid 16,0 +optionalChildren [ +*80 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,53000,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*81 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56800,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*82 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,52400,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*83 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,35800,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*84 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,66400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*85 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,72800,45000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*86 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "38000,44500,47000,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*87 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,35200,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*88 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,35800,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*89 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,51200,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *90 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*91 (Text +uid 49,0 +va (VaSet +font "courier,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*92 (MLText +uid 50,0 +va (VaSet +font "courier,8,0" +) +xt "0,1000,15500,3700" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all;" +tm "PackageList" +) +] +) +windowSize "81,31,1366,900" +viewArea "-1000,-1000,74686,50617" +cachedDiagramExtent "0,0,73000,49000" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +xMargin 49 +yMargin 49 +windowsPaperWidth 761 +windowsPaperHeight 1077 +paperType "Letter (8.5\" x 11\")" +windowsPaperName "A4" +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,8,0" +) +xt "200,200,2200,1100" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,8,0" +) +xt "450,2150,1450,3050" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +) +xt "600,1000,4800,2200" +st "Panel0" +blo "600,2000" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,35000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +) +xt "22600,14800,27900,16000" +st "" +blo "22600,15800" +) +second (Text +va (VaSet +) +xt "22600,16000,26500,17200" +st "" +blo "22600,17000" +) +) +gi *93 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *94 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,5800,7000,6800" +st "Declarations" +blo "0,6600" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,6800,3400,7800" +st "Ports:" +blo "0,7600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,15000,2500,15900" +st "User:" +blo "0,15700" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,5800,7600,6800" +st "Internal User:" +blo "0,6600" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,15900,2000,15900" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,5800,0,5800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 426,0 +activeModelName "Symbol" +) diff --git a/Libs/Memory/hds/_bram._epf b/Libs/Memory/hds/_bram._epf new file mode 100644 index 0000000..0041f9c --- /dev/null +++ b/Libs/Memory/hds/_bram._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom bram_bhv.vhd +DEFAULT_ARCHITECTURE atom bhv +TOP_MARKER atom 1 diff --git a/Libs/Memory/hds/_bramdualportwritefirst._epf b/Libs/Memory/hds/_bramdualportwritefirst._epf new file mode 100644 index 0000000..72f20fb --- /dev/null +++ b/Libs/Memory/hds/_bramdualportwritefirst._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom bramDualportWritefirst_bhv.vhd +DEFAULT_ARCHITECTURE atom bhv +TOP_MARKER atom 1 diff --git a/Libs/Memory/hds/_fifo._epf b/Libs/Memory/hds/_fifo._epf new file mode 100644 index 0000000..30bfe35 --- /dev/null +++ b/Libs/Memory/hds/_fifo._epf @@ -0,0 +1,3 @@ +TOP_MARKER atom 1 +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom @f@i@f@o/struct.bd diff --git a/Libs/Memory/hds/_fifo_bram._epf b/Libs/Memory/hds/_fifo_bram._epf new file mode 100644 index 0000000..0037371 --- /dev/null +++ b/Libs/Memory/hds/_fifo_bram._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom fifo_bram_rtl.vhd +DEFAULT_ARCHITECTURE atom RTL +TOP_MARKER atom 0 diff --git a/Libs/Memory/hds/_fifo_oneregister._epf b/Libs/Memory/hds/_fifo_oneregister._epf new file mode 100644 index 0000000..f095563 --- /dev/null +++ b/Libs/Memory/hds/_fifo_oneregister._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom fifo_oneRegister_rtl.vhd +DEFAULT_ARCHITECTURE atom oneRegister +TOP_MARKER atom 0 diff --git a/Libs/Memory/hds/_fifobridge._epf b/Libs/Memory/hds/_fifobridge._epf new file mode 100644 index 0000000..e35610c --- /dev/null +++ b/Libs/Memory/hds/_fifobridge._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom fifo@bridge/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory/hds/_fifobridgebuswidthadaption._epf b/Libs/Memory/hds/_fifobridgebuswidthadaption._epf new file mode 100644 index 0000000..cd1cbce --- /dev/null +++ b/Libs/Memory/hds/_fifobridgebuswidthadaption._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom fifo@bridge@bus@width@adaption/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory/hds/_fifobridgerxtotx._epf b/Libs/Memory/hds/_fifobridgerxtotx._epf new file mode 100644 index 0000000..93a8c4c --- /dev/null +++ b/Libs/Memory/hds/_fifobridgerxtotx._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom fifobridgerxtotx_rtl.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/Libs/Memory/hds/_fifobridgerxtotxbuswidthadaptionrxbigger._epf b/Libs/Memory/hds/_fifobridgerxtotxbuswidthadaptionrxbigger._epf new file mode 100644 index 0000000..08136c5 --- /dev/null +++ b/Libs/Memory/hds/_fifobridgerxtotxbuswidthadaptionrxbigger._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd +DEFAULT_ARCHITECTURE atom behavioral diff --git a/Libs/Memory/hds/_fifobridgerxtotxbuswidthadaptiontxbigger._epf b/Libs/Memory/hds/_fifobridgerxtotxbuswidthadaptiontxbigger._epf new file mode 100644 index 0000000..a4ff292 --- /dev/null +++ b/Libs/Memory/hds/_fifobridgerxtotxbuswidthadaptiontxbigger._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd +DEFAULT_ARCHITECTURE atom behavioral diff --git a/Libs/Memory/hds/_flashcontroller._epf b/Libs/Memory/hds/_flashcontroller._epf new file mode 100644 index 0000000..388eac4 --- /dev/null +++ b/Libs/Memory/hds/_flashcontroller._epf @@ -0,0 +1,3 @@ +TOP_MARKER atom 1 +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom flashController_RTL.vhd diff --git a/Libs/Memory/hds/_sdramcontroller._epf b/Libs/Memory/hds/_sdramcontroller._epf new file mode 100644 index 0000000..03cc304 --- /dev/null +++ b/Libs/Memory/hds/_sdramcontroller._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom sdram@controller/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory/hds/_sdramcontrollerbuildaddress._epf b/Libs/Memory/hds/_sdramcontrollerbuildaddress._epf new file mode 100644 index 0000000..7e31da3 --- /dev/null +++ b/Libs/Memory/hds/_sdramcontrollerbuildaddress._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom sdramControllerBuildAddress_RTL.vhd diff --git a/Libs/Memory/hds/_sdramcontrollerfsm._epf b/Libs/Memory/hds/_sdramcontrollerfsm._epf new file mode 100644 index 0000000..4c6b139 --- /dev/null +++ b/Libs/Memory/hds/_sdramcontrollerfsm._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom fsm +DEFAULT_FILE atom sdram@controller@fsm/fsm.sm diff --git a/Libs/Memory/hds/_sdramcontrollerrefreshcounter._epf b/Libs/Memory/hds/_sdramcontrollerrefreshcounter._epf new file mode 100644 index 0000000..79c67be --- /dev/null +++ b/Libs/Memory/hds/_sdramcontrollerrefreshcounter._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom sdramControllerRefreshCounter_RTL.vhd diff --git a/Libs/Memory/hds/_sdramcontrollersampledatain._epf b/Libs/Memory/hds/_sdramcontrollersampledatain._epf new file mode 100644 index 0000000..d41ad8f --- /dev/null +++ b/Libs/Memory/hds/_sdramcontrollersampledatain._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom 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+uid 815,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,14400,10000,15300" +st "rxRd1 : std_ulogic" +) +) +*22 (PortIoIn +uid 816,0 +shape (CompositeShape +uid 817,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 818,0 +sl 0 +ro 90 +xt "62500,38625,64000,39375" +) +(Line +uid 819,0 +sl 0 +ro 90 +xt "62000,39000,62500,39000" +pts [ +"62500,39000" +"62000,39000" +] +) +] +) +tg (WTG +uid 820,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 821,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "65000,38300,69900,39600" +st "txFull1" +blo "65000,39300" +tm "WireNameMgr" +) +) +) +*23 (Net +uid 828,0 +decl (Decl +n "txFull1" +t "std_ulogic" +o 7 +suid 16,0 +) +declText (MLText +uid 829,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,12600,10000,13500" +st "txFull1 : std_ulogic" +) +) +*24 (PortIoIn +uid 830,0 +shape (CompositeShape +uid 831,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 832,0 +sl 0 +ro 270 +xt "28000,14625,29500,15375" +) +(Line +uid 833,0 +sl 0 +ro 270 +xt "29500,15000,30000,15000" +pts [ +"29500,15000" +"30000,15000" +] +) +] +) +tg (WTG +uid 834,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 835,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "21400,14500,27000,15800" +st "rxEmpty1" +ju 2 +blo "27000,15500" +tm "WireNameMgr" +) +) +) +*25 (Net +uid 842,0 +decl (Decl +n "rxEmpty1" +t "std_ulogic" +o 5 +suid 17,0 +) +declText (MLText +uid 843,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,10800,10000,11700" +st "rxEmpty1 : std_ulogic" +) +) +*26 (PortIoOut +uid 844,0 +shape (CompositeShape +uid 845,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 846,0 +sl 0 +ro 270 +xt "62500,36625,64000,37375" +) +(Line +uid 847,0 +sl 0 +ro 270 +xt "62000,37000,62500,37000" +pts [ +"62000,37000" +"62500,37000" +] +) +] +) +tg (WTG +uid 848,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 849,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "65000,36500,88100,37800" +st "txData1 : (dataBitNb-1 DOWNTO 0)" +blo "65000,37500" +tm "WireNameMgr" +) +) +) +*27 (Net +uid 856,0 +decl (Decl +n "txData1" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 11 +suid 18,0 +) +declText (MLText +uid 857,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,16200,24500,17100" +st "txData1 : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*28 (PortIoOut +uid 858,0 +shape (CompositeShape +uid 859,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 860,0 +sl 0 +ro 90 +xt "28000,40625,29500,41375" +) +(Line +uid 861,0 +sl 0 +ro 90 +xt "29500,41000,30000,41000" +pts [ +"30000,41000" +"29500,41000" +] +) +] +) +tg (WTG +uid 862,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 863,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "23500,40300,27000,41600" +st "rxRd2" +ju 2 +blo "27000,41300" +tm "WireNameMgr" +) +) +) +*29 (Net +uid 870,0 +decl (Decl +n "rxRd2" +t "std_ulogic" +o 10 +suid 19,0 +) +declText (MLText +uid 871,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,15300,10000,16200" +st "rxRd2 : std_ulogic" +) +) +*30 (PortIoIn +uid 872,0 +shape (CompositeShape +uid 873,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 874,0 +sl 0 +ro 270 +xt "28000,36625,29500,37375" +) +(Line +uid 875,0 +sl 0 +ro 270 +xt "29500,37000,30000,37000" +pts [ +"29500,37000" +"30000,37000" +] +) +] +) +tg (WTG +uid 876,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 877,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "3900,36500,27000,37800" +st "rxData2 : (dataBitNb-1 DOWNTO 0)" +ju 2 +blo "27000,37500" +tm "WireNameMgr" +) +) +) +*31 (Net +uid 884,0 +decl (Decl +n "rxData2" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 20,0 +) +declText (MLText +uid 885,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,9900,24500,10800" +st "rxData2 : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*32 (PortIoOut +uid 886,0 +shape (CompositeShape +uid 887,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 888,0 +sl 0 +ro 270 +xt "62500,12625,64000,13375" +) +(Line +uid 889,0 +sl 0 +ro 270 +xt "62000,13000,62500,13000" +pts [ +"62000,13000" +"62500,13000" +] +) +] +) +tg (WTG +uid 890,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 891,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "65000,12500,88100,13800" +st "txData2 : (dataBitNb-1 DOWNTO 0)" +blo "65000,13500" +tm "WireNameMgr" +) +) +) +*33 (Net +uid 898,0 +decl (Decl +n "txData2" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 12 +suid 21,0 +) +declText (MLText +uid 899,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,17100,24500,18000" +st "txData2 : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*34 (PortIoIn +uid 900,0 +shape (CompositeShape +uid 901,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 902,0 +sl 0 +ro 90 +xt "62500,14625,64000,15375" +) +(Line +uid 903,0 +sl 0 +ro 90 +xt "62000,15000,62500,15000" +pts [ +"62500,15000" +"62000,15000" +] +) +] +) +tg (WTG +uid 904,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 905,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "65000,14300,69900,15600" +st "txFull2" +blo "65000,15300" +tm "WireNameMgr" +) +) +) +*35 (Net +uid 912,0 +decl (Decl +n "txFull2" +t "std_ulogic" +o 8 +suid 22,0 +) +declText (MLText +uid 913,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,13500,10000,14400" +st "txFull2 : std_ulogic" +) +) +*36 (PortIoIn +uid 914,0 +shape (CompositeShape +uid 915,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 916,0 +sl 0 +ro 270 +xt "28000,38625,29500,39375" +) +(Line +uid 917,0 +sl 0 +ro 270 +xt "29500,39000,30000,39000" +pts [ +"29500,39000" +"30000,39000" +] +) +] +) +tg (WTG +uid 918,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 919,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "21400,38500,27000,39800" +st "rxEmpty2" +ju 2 +blo "27000,39500" +tm "WireNameMgr" +) +) +) +*37 (Net +uid 926,0 +decl (Decl +n "rxEmpty2" +t "std_ulogic" +o 6 +suid 23,0 +) +declText (MLText +uid 927,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,11700,10000,12600" +st "rxEmpty2 : std_ulogic" +) +) +*38 (PortIoOut +uid 928,0 +shape (CompositeShape +uid 929,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 930,0 +sl 0 +ro 270 +xt "62500,16625,64000,17375" +) +(Line +uid 931,0 +sl 0 +ro 270 +xt "62000,17000,62500,17000" +pts [ +"62000,17000" +"62500,17000" +] +) +] +) +tg (WTG +uid 932,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 933,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "65000,16500,68500,17800" +st "txWr2" +blo "65000,17500" +tm "WireNameMgr" +) +) +) +*39 (Net +uid 940,0 +decl (Decl +n "txWr2" +t "std_ulogic" +o 14 +suid 24,0 +) +declText (MLText +uid 941,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,18900,10000,19800" +st "txWr2 : std_ulogic" +) +) +*40 (SaComponent +uid 1201,0 +optionalChildren [ +*41 (CptPort +uid 1169,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1170,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,20625,38000,21375" +) +tg (CPTG +uid 1171,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1172,0 +va (VaSet +font "courier,9,0" +) +xt "39000,20400,41500,21300" +st "clock" +blo "39000,21100" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*42 (CptPort +uid 1173,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1174,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,22625,38000,23375" +) +tg (CPTG +uid 1175,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1176,0 +va (VaSet +font "courier,9,0" +) +xt "39000,22400,41500,23300" +st "reset" +blo "39000,23100" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 2 +suid 2,0 +) +) +) +*43 (CptPort +uid 1177,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1178,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,12625,54750,13375" +) +tg (CPTG +uid 1179,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1180,0 +va (VaSet +font "courier,9,0" +) +xt "50500,12400,53000,13300" +st "data2" +ju 2 +blo "53000,13100" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "data2" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 3 +suid 3,0 +) +) +) +*44 (CptPort +uid 1181,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1182,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,14625,54750,15375" +) +tg (CPTG +uid 1183,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1184,0 +va (VaSet +font "courier,9,0" +) +xt "50500,14400,53000,15300" +st "full2" +ju 2 +blo "53000,15100" +) +) +thePort (LogicalPort +decl (Decl +n "full2" +t "std_ulogic" +o 4 +suid 4,0 +) +) +) +*45 (CptPort +uid 1185,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1186,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,16625,54750,17375" +) +tg (CPTG +uid 1187,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1188,0 +va (VaSet +font "courier,9,0" +) +xt "51500,16400,53000,17300" +st "wr2" +ju 2 +blo "53000,17100" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "wr2" +t "std_ulogic" +o 5 +suid 5,0 +) +) +) +*46 (CptPort +uid 1189,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1190,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,14625,38000,15375" +) +tg (CPTG +uid 1191,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1192,0 +va (VaSet +font "courier,9,0" +) +xt "39000,14400,42000,15300" +st "empty1" +blo "39000,15100" +) +) +thePort (LogicalPort +decl (Decl +n "empty1" +t "std_ulogic" +o 7 +suid 6,0 +) +) +) +*47 (CptPort +uid 1193,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1194,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,12625,38000,13375" +) +tg (CPTG +uid 1195,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1196,0 +va (VaSet +font "courier,9,0" +) +xt "39000,12400,41500,13300" +st "data1" +blo "39000,13100" +) +) +thePort (LogicalPort +decl (Decl +n "data1" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 6 +suid 7,0 +) +) +) +*48 (CptPort +uid 1197,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1198,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,16625,38000,17375" +) +tg (CPTG +uid 1199,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1200,0 +va (VaSet +font "courier,9,0" +) +xt "39000,16400,40500,17300" +st "rd1" +blo "39000,17100" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "rd1" +t "std_ulogic" +o 8 +suid 8,0 +) +) +) +] +shape (Rectangle +uid 1202,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "38000,9000,54000,25000" +) +oxt "35000,10000,51000,26000" +ttg (MlTextGroup +uid 1203,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*49 (Text +uid 1204,0 +va (VaSet +font "courier,9,1" +) +xt "38600,24800,41600,25700" +st "memory" +blo "38600,25500" +tm "BdLibraryNameMgr" +) +*50 (Text +uid 1205,0 +va (VaSet +font "courier,9,1" +) +xt "38600,26000,47100,26900" +st "fifoBridgeRxToTx" +blo "38600,26700" +tm "CptNameMgr" +) +*51 (Text +uid 1206,0 +va (VaSet +font "courier,9,1" +) +xt "38600,27200,42600,28100" +st "rx1ToTx2" +blo "38600,27900" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1207,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1208,0 +text (MLText +uid 1209,0 +va (VaSet +font "courier,8,0" +) +xt "38000,28400,103000,31100" +st "dataBitNb = dataBitNb ( positive ) +fifoDepth = fifoDepth ( positive ) +firstWordFallThrough = firstWordFallThrough ( boolean ) --first byte written into the FIFO immediately appears on the output " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "fifoDepth" +type "positive" +value "fifoDepth" +) +(GiElement +name "firstWordFallThrough" +type "boolean" +value "firstWordFallThrough" +e "first byte written into the FIFO immediately appears on the output" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*52 (SaComponent +uid 1242,0 +optionalChildren [ +*53 (CptPort +uid 1210,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1211,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,44625,38000,45375" +) +tg (CPTG +uid 1212,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1213,0 +va (VaSet +font "courier,9,0" +) +xt "39000,44400,41500,45300" +st "clock" +blo "39000,45100" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*54 (CptPort +uid 1214,0 +ps "OnEdgeStrategy" +shape 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(MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2600,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,8,0" +) +xt "450,2150,1450,3050" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "courier,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" 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"-2000,11200" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,11400,700,12400" +st "Ports:" +blo "-2000,12200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,28600,500,29500" +st "User:" +blo "-2000,29300" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "-2000,10400,3800,11400" +st "Internal User:" +blo "-2000,11200" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "0,29500,0,29500" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "-2000,10400,-2000,10400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 800,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol:GEN" +) diff --git a/Libs/Memory/hds/sdram@controller/struct.bd b/Libs/Memory/hds/sdram@controller/struct.bd new file mode 100644 index 0000000..d8adef0 --- /dev/null +++ b/Libs/Memory/hds/sdram@controller/struct.bd @@ -0,0 +1,9775 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "U_5" +duLibraryName "memory" +duName "sdramControllerSR" +elements [ +] +mwi 0 +uid 2332,0 +) +(Instance +name "U_6" +duLibraryName "memory" +duName "sdramControllerSR" +elements [ +] +mwi 0 +uid 2398,0 +) +(Instance +name "U_2" +duLibraryName "memory" +duName "sdramControllerTimingsShiftRegister" +elements [ +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "maxDelayPeriodNb" +) +] +mwi 0 +uid 3238,0 +) +(Instance +name "U_4" +duLibraryName "memory" +duName "sdramControllerStoreData" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +mwi 0 +uid 3306,0 +) +(Instance +name "U_7" +duLibraryName "memory" +duName "sdramControllerSampleDataIn" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +mwi 0 +uid 3336,0 +) +(Instance +name "U_1" +duLibraryName "memory" +duName "sdramControllerRefreshCounter" +elements [ +(GiElement +name "delayCounterBitNb" +type "positive" +value "delayCounterBitNb" +) +(GiElement +name "refreshPeriodNb" +type "positive" +value "refreshPeriodNb" +) +] +mwi 0 +uid 3568,0 +) +(Instance +name "U_3" +duLibraryName "memory" +duName "sdramControllerBuildAddress" +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "addressBitNb" +) +(GiElement +name "chipAddressBitNb" +type "positive" +value "chipAddressBitNb" +) +(GiElement +name "chipBankAddressBitNb" +type "positive" +value "chipBankAddressBitNb" +) +(GiElement +name "rowAddressBitNb" +type "positive" +value "rowAddressBitNb" +) +(GiElement +name "colAddressBitNb" +type "positive" +value "colAddressBitNb" +) +] +mwi 0 +uid 3925,0 +) +(Instance +name "U_0" +duLibraryName "memory" +duName "sdramControllerFsm" +elements [ +(GiElement +name "commandBusBitNb" +type "positive" +value "commandBusBitNb" +) +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "maxDelayPeriodNb" +) +(GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +(GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +(GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +(GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +(GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +] +mwi 0 +uid 4230,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +(EmbeddedInstance +name "eb2" +number "2" +) +] +libraryRefs [ +"ieee" +] +) +version "31.1" +appVersion "2018.1 (Build 12)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller/struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller/struct.bd.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramController" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "sdramController" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/28/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "13:45:15" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Memory" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../Demo/designcheck" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libs/Memory/work" +) +(vvPair +variable "mm" +value "08" +) +(vvPair +variable "module_name" +value "sdramController" +) +(vvPair +variable "month" +value "Aug" +) +(vvPair +variable "month_long" +value "August" +) +(vvPair +variable "p" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller/struct.bd" +) +(vvPair +variable "p_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramController/struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "13:45:15" +) +(vvPair +variable "unit" +value "sdramController" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2018.1 (Build 12)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 356,0 +optionalChildren [ +*1 (PortIoOut +uid 51,0 +shape (CompositeShape +uid 52,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 53,0 +sl 0 +ro 270 +xt "162500,36625,164000,37375" +) +(Line +uid 54,0 +sl 0 +ro 270 +xt "162000,37000,162500,37000" +pts [ +"162000,37000" +"162500,37000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 55,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 56,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "165000,36300,174700,37700" +st "memAddress" +blo "165000,37500" +tm "WireNameMgr" +) +) +) +*2 (Net +uid 63,0 +decl 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"-8000,91800,7500,92700" +st "sdClk : std_ulogic" +) +) +*23 (PortIoOut +uid 219,0 +shape (CompositeShape +uid 220,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 221,0 +sl 0 +ro 270 +xt "122500,76625,124000,77375" +) +(Line +uid 222,0 +sl 0 +ro 270 +xt "122000,77000,122500,77000" +pts [ +"122000,77000" +"122500,77000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 223,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 224,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "125000,76300,130500,77700" +st "sdCs_n" +blo "125000,77500" +tm "WireNameMgr" +) +) +) +*24 (Net +uid 231,0 +decl (Decl +n "sdCs_n" +t "std_ulogic" +o 18 +suid 16,0 +) +declText (MLText +uid 232,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,93000,7500,93900" +st "sdCs_n : std_ulogic" +) +) +*25 (PortIoOut +uid 261,0 +shape (CompositeShape +uid 262,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 263,0 +sl 0 +ro 270 +xt "122500,78625,124000,79375" +) +(Line +uid 264,0 +sl 0 +ro 270 +xt "122000,79000,122500,79000" +pts [ +"122000,79000" +"122500,79000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 265,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 266,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "125000,78300,131200,79700" +st "sdRas_n" +blo "125000,79500" +tm "WireNameMgr" +) +) +) +*26 (Net +uid 273,0 +decl (Decl +n "sdRas_n" +t "std_ulogic" +o 20 +suid 19,0 +) +declText (MLText +uid 274,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,95400,7500,96300" +st "sdRas_n : std_ulogic" +) +) +*27 (Grouping +uid 313,0 +optionalChildren [ +*28 (CommentText +uid 315,0 +shape (Rectangle +uid 316,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "136000,123000,153000,124000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 317,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "136200,123000,151200,124000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*29 (CommentText +uid 318,0 +shape (Rectangle +uid 319,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "153000,119000,157000,120000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 320,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "153200,119000,156800,120000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*30 (CommentText +uid 321,0 +shape (Rectangle +uid 322,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "136000,121000,153000,122000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 323,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "136200,121000,152400,122000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*31 (CommentText +uid 324,0 +shape (Rectangle +uid 325,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "132000,121000,136000,122000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 326,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "132200,121000,135800,122000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*32 (CommentText +uid 327,0 +shape (Rectangle +uid 328,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "153000,120000,173000,124000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 329,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "153200,120200,166400,121200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*33 (CommentText +uid 330,0 +shape (Rectangle +uid 331,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "157000,119000,173000,120000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 332,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "157200,119000,159000,120000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*34 (CommentText +uid 333,0 +shape (Rectangle +uid 334,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "132000,119000,153000,121000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 335,0 +va (VaSet +fg "32768,0,0" +) +xt "138000,119500,147000,120500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*35 (CommentText +uid 336,0 +shape (Rectangle +uid 337,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "132000,122000,136000,123000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 338,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "132200,122000,135200,123000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*36 (CommentText +uid 339,0 +shape (Rectangle +uid 340,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "132000,123000,136000,124000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 341,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "132200,123000,135800,124000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*37 (CommentText +uid 342,0 +shape (Rectangle +uid 343,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "136000,122000,153000,123000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 344,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "136200,122000,150600,123000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 314,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "132000,119000,173000,124000" +) +oxt "14000,66000,55000,71000" +) +*38 (PortIoIn +uid 599,0 +shape (CompositeShape +uid 600,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 601,0 +sl 0 +ro 270 +xt "52000,54625,53500,55375" +) +(Line +uid 602,0 +sl 0 +ro 270 +xt "53500,55000,54000,55000" +pts [ +"53500,55000" +"54000,55000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 603,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 604,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "47200,54300,51000,55700" +st "clock" +ju 2 +blo "51000,55500" +tm "WireNameMgr" +) +) +) +*39 (Net +uid 611,0 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 23,0 +) +declText (MLText +uid 612,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,72600,7500,73500" +st "clock : std_ulogic" +) +) +*40 (PortIoOut +uid 613,0 +shape (CompositeShape +uid 614,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 615,0 +sl 0 +ro 270 +xt "82500,52625,84000,53375" +) +(Line +uid 616,0 +sl 0 +ro 270 +xt "82000,53000,82500,53000" +pts [ +"82000,53000" +"82500,53000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 617,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 618,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "85000,52300,95000,53700" +st "ramDataValid" +blo "85000,53500" +tm "WireNameMgr" +) +) +) +*41 (Net +uid 625,0 +decl (Decl +n "ramDataValid" +t "std_ulogic" +o 14 +suid 24,0 +) +declText (MLText +uid 626,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,88200,7500,89100" +st "ramDataValid : std_ulogic" +) +) +*42 (PortIoIn +uid 627,0 +shape (CompositeShape +uid 628,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 629,0 +sl 0 +ro 270 +xt "128000,36625,129500,37375" +) +(Line +uid 630,0 +sl 0 +ro 270 +xt "129500,37000,130000,37000" +pts [ +"129500,37000" +"130000,37000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 631,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 632,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "120900,36300,127000,37700" +st "ramAddr" +ju 2 +blo "127000,37500" +tm "WireNameMgr" +) +) +) +*43 (Net +uid 639,0 +decl (Decl +n "ramAddr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 3 +suid 25,0 +) +declText (MLText +uid 640,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,75000,19000,75900" +st "ramAddr : unsigned(addressBitNb-1 DOWNTO 0)" +) +) +*44 (PortIoIn +uid 641,0 +shape (CompositeShape +uid 642,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 643,0 +sl 0 +ro 270 +xt "128000,60625,129500,61375" +) +(Line +uid 644,0 +sl 0 +ro 270 +xt "129500,61000,130000,61000" +pts [ +"129500,61000" +"130000,61000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 645,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 646,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "117700,60300,127000,61700" +st "ramDataOut" +ju 2 +blo "127000,61500" +tm "WireNameMgr" +) +) +) +*45 (Net +uid 653,0 +decl (Decl +n "ramDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 26,0 +) +declText (MLText +uid 654,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,76200,22000,77100" +st "ramDataOut : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*46 (PortIoOut +uid 655,0 +shape (CompositeShape +uid 656,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 657,0 +sl 0 +ro 90 +xt "48000,75625,49500,76375" +) +(Line +uid 658,0 +sl 0 +ro 90 +xt "49500,76000,50000,76000" +pts [ +"50000,76000" +"49500,76000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 659,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 660,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "39500,75300,47000,76700" +st "ramDataIn" +ju 2 +blo "47000,76500" +tm "WireNameMgr" +) +) +) +*47 (Net +uid 667,0 +decl (Decl +n "ramDataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 13 +suid 27,0 +) +declText (MLText +uid 668,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,87000,22000,87900" +st "ramDataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*48 (PortIoOut +uid 1316,0 +shape (CompositeShape +uid 1317,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1318,0 +sl 0 +ro 270 +xt "122500,84625,124000,85375" +) +(Line +uid 1319,0 +sl 0 +ro 270 +xt "122000,85000,122500,85000" +pts [ +"122000,85000" +"122500,85000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 1320,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1321,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "125000,84300,130100,85700" +st "sdDqm" +blo "125000,85500" +tm "WireNameMgr" +) +) +) +*49 (Net +uid 1328,0 +decl (Decl +n "sdDqm" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 19 +suid 28,0 +) +declText (MLText +uid 1329,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,94200,17000,95100" +st "sdDqm : std_ulogic_vector(1 DOWNTO 0)" +) +) +*50 (PortIoOut +uid 1330,0 +shape (CompositeShape +uid 1331,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1332,0 +sl 0 +ro 270 +xt "162500,38625,164000,39375" +) +(Line +uid 1333,0 +sl 0 +ro 270 +xt "162000,39000,162500,39000" +pts [ +"162000,39000" +"162500,39000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 1334,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1335,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "165000,38300,177800,39700" +st "memBankAddress" +blo "165000,39500" +tm "WireNameMgr" +) +) +) +*51 (Net +uid 1342,0 +decl (Decl +n "memBankAddress" +t "std_ulogic_vector" +b "( chipBankAddressBitNb-1 DOWNTO 0 )" +o 10 +suid 29,0 +) +declText (MLText +uid 1343,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,83400,28500,84300" +st "memBankAddress : std_ulogic_vector( chipBankAddressBitNb-1 DOWNTO 0 )" +) +) +*52 (HdlText +uid 1607,0 +optionalChildren [ +*53 (EmbeddedText +uid 1613,0 +commentText (CommentText +uid 1614,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1615,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "138000,18000,154000,24000" +) +oxt "0,0,18000,5000" +text (MLText +uid 1616,0 +va (VaSet +font "courier,9,0" +) +xt "138200,18200,148200,20000" +st " +sdCke <= '1'; +sdClk <= not clock; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 1608,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "138000,17000,154000,25000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1609,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*54 (Text +uid 1610,0 +va (VaSet +font "courier,9,0" +) +xt "138150,25000,140150,26200" +st "eb1" +blo "138150,25900" +tm "HdlTextNameMgr" +) +*55 (Text +uid 1611,0 +va (VaSet +font "courier,9,0" +) +xt "138150,26200,139150,27400" +st "1" +blo "138150,27100" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 1612,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "138250,23250,139750,24750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*56 (Net +uid 1665,0 +decl (Decl +n "powerUpDone" +t "std_ulogic" +o 28 +suid 32,0 +) +declText (MLText +uid 1666,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,112600,11000,113500" +st "SIGNAL powerUpDone : std_ulogic" +) +) +*57 (Net +uid 1681,0 +decl (Decl +n "endOfRefreshCount" +t "std_ulogic" +o 27 +suid 35,0 +) +declText (MLText +uid 1682,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,111400,11000,112300" +st "SIGNAL endOfRefreshCount : std_ulogic" +) +) +*58 (Net +uid 1695,0 +decl (Decl +n "commandBus" +t "std_ulogic_vector" +b "(commandBusBitNb-1 DOWNTO 0)" +o 26 +suid 37,0 +) +declText (MLText +uid 1696,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,110200,28500,111100" +st "SIGNAL commandBus : std_ulogic_vector(commandBusBitNb-1 DOWNTO 0)" +) +) +*59 (HdlText +uid 1697,0 +optionalChildren [ +*60 (EmbeddedText +uid 1703,0 +commentText (CommentText +uid 1704,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1705,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "98000,74000,114000,82000" +) +oxt "0,0,18000,5000" +text (MLText +uid 1706,0 +va (VaSet +font "courier,9,0" +) +xt "98200,74200,114200,79600" +st " +sdCs_n <= commandBus(5); +sdRas_n <= commandBus(4); +sdCas_n <= commandBus(3); +memWr_n <= commandBus(2); +sdDqm <= commandBus(1 downto 0); + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 8000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 1698,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "98000,73000,114000,89000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1699,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*61 (Text +uid 1700,0 +va (VaSet +font "courier,9,0" +) +xt "98150,89000,100150,90200" +st "eb2" +blo "98150,89900" +tm "HdlTextNameMgr" +) +*62 (Text +uid 1701,0 +va (VaSet +font "courier,9,0" +) +xt "98150,90200,99150,91400" +st "2" +blo "98150,91100" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 1702,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "98250,87250,99750,88750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*63 (Net +uid 1785,0 +decl (Decl +n "timerStart" +t "std_ulogic" +o 33 +suid 39,0 +) +declText (MLText +uid 1786,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,118600,11000,119500" +st "SIGNAL timerStart : std_ulogic" +) +) +*64 (Net +uid 1801,0 +decl (Decl +n "timerDone" +t "std_ulogic_vector" +b "(1 TO maxDelayPeriodNb)" +o 32 +suid 41,0 +) +declText (MLText +uid 1802,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,117400,26000,118300" +st "SIGNAL timerDone : std_ulogic_vector(1 TO maxDelayPeriodNb)" +) +) +*65 (Net +uid 1924,0 +decl (Decl +n "addrSelPrecharge" +t "std_ulogic" +o 24 +suid 43,0 +) +declText (MLText +uid 1925,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,107800,11000,108700" +st "SIGNAL addrSelPrecharge : std_ulogic" +) +) +*66 (Net +uid 2051,0 +decl (Decl +n "addrSelModeReg" +t "std_ulogic" +o 23 +suid 44,0 +) +declText (MLText +uid 2052,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,106600,11000,107500" +st "SIGNAL addrSelModeReg : std_ulogic" +) +) +*67 (Net +uid 2266,0 +decl (Decl +n "writeRequest" +t "std_ulogic" +o 35 +suid 45,0 +) +declText (MLText +uid 2267,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,121000,11000,121900" +st "SIGNAL writeRequest : std_ulogic" +) +) +*68 (Net +uid 2276,0 +decl (Decl +n "writeAck" +t "std_ulogic" +o 34 +suid 46,0 +) +declText (MLText +uid 2277,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,119800,11000,120700" +st "SIGNAL writeAck : std_ulogic" +) +) +*69 (SaComponent +uid 2332,0 +optionalChildren [ +*70 (CptPort +uid 2312,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2313,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "17250,32625,18000,33375" +) +tg (CPTG +uid 2314,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2315,0 +va (VaSet +) +xt "19000,32500,21100,33500" +st "clock" +blo "19000,33300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*71 (CptPort +uid 2316,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2317,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "17250,26625,18000,27375" +) +tg (CPTG +uid 2318,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2319,0 +va (VaSet +) +xt "19000,26500,22000,27500" +st "setFlag" +blo "19000,27300" +) +) +thePort (LogicalPort +decl (Decl +n "setFlag" +t "std_ulogic" +o 7 +suid 2,0 +) +) +) +*72 (CptPort +uid 2320,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2321,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "17250,34625,18000,35375" +) +tg (CPTG +uid 2322,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2323,0 +va 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"VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*89 (Net +uid 2456,0 +decl (Decl +n "readAck" +t "std_ulogic" +o 29 +suid 49,0 +) +declText (MLText +uid 2457,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,113800,11000,114700" +st "SIGNAL readAck : std_ulogic" +) +) +*90 (Net +uid 2458,0 +decl (Decl +n "readRequest" +t "std_ulogic" +o 30 +suid 50,0 +) +declText (MLText +uid 2459,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,115000,11000,115900" +st "SIGNAL readRequest : std_ulogic" +) +) +*91 (Net +uid 2516,0 +decl (Decl +n "sampleData" +t "std_ulogic" +o 31 +suid 52,0 +) +declText (MLText +uid 2517,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,116200,11000,117100" +st "SIGNAL sampleData : std_ulogic" +) +) +*92 (SaComponent +uid 3238,0 +optionalChildren [ +*93 (CptPort +uid 3222,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3223,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "97250,60625,98000,61375" +) +tg (CPTG +uid 3224,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3225,0 +va (VaSet +) +xt "99000,60500,101100,61500" +st "clock" +blo "99000,61300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 5,0 +) +) +) +*94 (CptPort +uid 3226,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3227,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "97250,62625,98000,63375" +) +tg (CPTG +uid 3228,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3229,0 +va (VaSet +) +xt "99000,62500,101100,63500" +st "reset" +blo "99000,63300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 8 +suid 6,0 +) +) +) +*95 (CptPort +uid 3230,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3231,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "114000,56625,114750,57375" +) +tg (CPTG +uid 3232,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3233,0 +va (VaSet +) +xt "109100,56500,113000,57500" +st "timerDone" +ju 2 +blo "113000,57300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "timerDone" +t "std_ulogic_vector" +b "(1 TO maxDelayPeriodNb)" +o 25 +suid 7,0 +) +) +) +*96 (CptPort +uid 3234,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3235,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "97250,56625,98000,57375" +) +tg (CPTG +uid 3236,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3237,0 +va (VaSet +) +xt "99000,56500,103100,57500" +st "timerStart" +blo "99000,57300" +) +) +thePort (LogicalPort +decl (Decl +n "timerStart" +t "std_ulogic" +o 24 +suid 8,0 +) +) +) +] +shape (Rectangle +uid 3239,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "98000,53000,114000,65000" +) +oxt "32000,16000,48000,28000" +ttg (MlTextGroup +uid 3240,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*97 (Text +uid 3241,0 +va (VaSet +font "courier,8,1" +) +xt "98400,65000,101700,66000" +st "memory" +blo "98400,65800" +tm "BdLibraryNameMgr" +) +*98 (Text +uid 3242,0 +va (VaSet +font "courier,8,1" +) +xt "98400,66000,113600,67000" +st "sdramControllerTimingsShiftRegister" +blo "98400,66800" +tm "CptNameMgr" +) +*99 (Text +uid 3243,0 +va (VaSet +font "courier,8,1" +) +xt "98400,67000,100200,68000" +st "U_2" +blo "98400,67800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3244,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3245,0 +text (MLText +uid 3246,0 +va (VaSet +font "courier,8,0" +) +xt "98000,68200,125000,69100" +st "maxDelayPeriodNb = maxDelayPeriodNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "maxDelayPeriodNb" +) +] +) +viewicon (ZoomableIcon +uid 3247,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "98250,63250,99750,64750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*100 (SaComponent +uid 3306,0 +optionalChildren [ +*101 (CptPort +uid 3286,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3287,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,66625,138000,67375" +) +tg (CPTG +uid 3288,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3289,0 +va (VaSet +) +xt "139000,66500,141100,67500" +st "clock" +blo "139000,67300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 11,0 +) +) +) +*102 (CptPort +uid 3290,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3291,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "154000,60625,154750,61375" +) +tg (CPTG +uid 3292,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3293,0 +va (VaSet +) +xt "147800,60500,153000,61500" +st "memDataOut" +ju 2 +blo "153000,61300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 11 +suid 12,0 +) +) +) +*103 (CptPort +uid 3294,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3295,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,60625,138000,61375" +) +tg (CPTG +uid 3296,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3297,0 +va (VaSet +) +xt "139000,60500,143900,61500" +st "ramDataOut" +blo "139000,61300" +) +) +thePort (LogicalPort +decl (Decl +n "ramDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 13,0 +) +) +) +*104 (CptPort +uid 3298,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3299,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,62625,138000,63375" +) +tg (CPTG +uid 3300,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3301,0 +va (VaSet +) +xt "139000,62500,141700,63500" +st "ramWr" +blo "139000,63300" +) +) +thePort (LogicalPort +decl (Decl +n "ramWr" +t "std_ulogic" +o 7 +suid 14,0 +) +) +) +*105 (CptPort +uid 3302,0 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(Text +uid 3311,0 +va (VaSet +font "courier,8,1" +) +xt "138500,73000,140300,74000" +st "U_4" +blo "138500,73800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3312,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3313,0 +text (MLText +uid 3314,0 +va (VaSet +font "courier,8,0" +) +xt "138000,74600,158000,75500" +st "dataBitNb = dataBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +) +viewicon (ZoomableIcon +uid 3315,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "138250,69250,139750,70750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*109 (SaComponent +uid 3336,0 +optionalChildren [ +*110 (CptPort +uid 3316,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3317,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,81625,58000,82375" +) +tg (CPTG +uid 3318,0 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+st "dataBitNb = dataBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +) +viewicon (ZoomableIcon +uid 3345,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "58250,84250,59750,85750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*118 (SaComponent +uid 3568,0 +optionalChildren [ +*119 (CptPort +uid 3548,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3549,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "97250,40625,98000,41375" +) +tg (CPTG +uid 3550,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3551,0 +va (VaSet +) +xt "99000,40500,101100,41500" +st "clock" +blo "99000,41300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 6,0 +) +) +) +*120 (CptPort +uid 3552,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3553,0 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+) +tg (CPTG +uid 3562,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3563,0 +va (VaSet +) +xt "99000,42500,101100,43500" +st "reset" +blo "99000,43300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 8 +suid 9,0 +) +) +) +*123 (CptPort +uid 3564,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3565,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "114000,38625,114750,39375" +) +tg (CPTG +uid 3566,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3567,0 +va (VaSet +) +xt "107500,38500,113000,39500" +st "selectRefresh" +ju 2 +blo "113000,39300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selectRefresh" +t "std_ulogic" +o 5 +suid 10,0 +) +) +) +] +shape (Rectangle +uid 3569,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "98000,33000,114000,45000" +) +oxt "32000,12000,48000,24000" +ttg (MlTextGroup +uid 3570,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*124 (Text +uid 3571,0 +va (VaSet +font "courier,8,1" +) +xt "98350,45000,101650,46000" +st "memory" +blo "98350,45800" +tm "BdLibraryNameMgr" +) +*125 (Text +uid 3572,0 +va (VaSet +font "courier,8,1" +) +xt "98350,46000,111650,47000" +st "sdramControllerRefreshCounter" +blo "98350,46800" +tm "CptNameMgr" +) +*126 (Text +uid 3573,0 +va (VaSet +font "courier,8,1" +) +xt "98350,47000,100150,48000" +st "U_1" +blo "98350,47800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3574,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3575,0 +text (MLText +uid 3576,0 +va (VaSet +font "courier,8,0" +) +xt "98000,48200,126000,50000" +st "delayCounterBitNb = delayCounterBitNb ( positive ) +refreshPeriodNb = refreshPeriodNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "delayCounterBitNb" +type "positive" +value "delayCounterBitNb" +) +(GiElement +name "refreshPeriodNb" +type "positive" +value "refreshPeriodNb" +) +] +) +viewicon (ZoomableIcon +uid 3577,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "98250,43250,99750,44750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*127 (Net +uid 3578,0 +decl (Decl +n "selectRefresh" +t "std_ulogic" +o 21 +suid 53,0 +) +declText (MLText +uid 3579,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,96600,7500,97500" +st "selectRefresh : std_ulogic" +) +) +*128 (PortIoOut +uid 3586,0 +shape (CompositeShape +uid 3587,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3588,0 +sl 0 +ro 270 +xt "122500,38625,124000,39375" +) +(Line +uid 3589,0 +sl 0 +ro 270 +xt "122000,39000,122500,39000" +pts [ +"122000,39000" +"122500,39000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3590,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3591,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "125000,38300,135100,39700" +st "selectRefresh" +blo "125000,39500" +tm "WireNameMgr" +) +) +) +*129 (SaComponent +uid 3925,0 +optionalChildren [ +*130 (CptPort +uid 3897,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3898,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,44625,138000,45375" +) +tg (CPTG +uid 3899,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3900,0 +va (VaSet +) +xt "139000,44500,143600,45500" +st "addrSelCol" +blo "139000,45300" +) +) +thePort (LogicalPort +decl (Decl +n "addrSelCol" +t "std_ulogic" +o 26 +suid 18,0 +) +) +) +*131 (CptPort +uid 3901,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3902,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,40625,138000,41375" +) +tg (CPTG +uid 3903,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3904,0 +va (VaSet +) +xt "139000,40500,145800,41500" +st "addrSelModeReg" +blo "139000,41300" +) +) +thePort (LogicalPort +decl (Decl +n "addrSelModeReg" +t "std_ulogic" +o 26 +suid 19,0 +) +) +) +*132 (CptPort +uid 3905,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3906,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,38625,138000,39375" +) +tg (CPTG +uid 3907,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3908,0 +va (VaSet +) +xt "139000,38500,146000,39500" +st "addrSelPrecharge" +blo "139000,39300" +) +) +thePort (LogicalPort +decl (Decl +n "addrSelPrecharge" +t "std_ulogic" +o 26 +suid 20,0 +) +) +) +*133 (CptPort +uid 3909,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3910,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,42625,138000,43375" +) +tg (CPTG +uid 3911,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3912,0 +va (VaSet +) +xt "139000,42500,143900,43500" +st "addrSelRow" +blo "139000,43300" +) +) +thePort (LogicalPort +decl (Decl +n "addrSelRow" +t "std_ulogic" +o 26 +suid 21,0 +) +) +) +*134 (CptPort +uid 3913,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3914,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "154000,36625,154750,37375" +) +tg (CPTG +uid 3915,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3916,0 +va (VaSet +) +xt "147800,36500,153000,37500" +st "memAddress" +ju 2 +blo "153000,37300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memAddress" +t "std_ulogic_vector" +b "( chipAddressBitNb-1 DOWNTO 0 )" +o 9 +suid 22,0 +) +) +) +*135 (CptPort +uid 3917,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3918,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "154000,38625,154750,39375" +) +tg (CPTG +uid 3919,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3920,0 +va (VaSet +) +xt "146200,38500,153000,39500" +st "memBankAddress" +ju 2 +blo "153000,39300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memBankAddress" +t "std_ulogic_vector" +b "( chipBankAddressBitNb-1 DOWNTO 0 )" +o 10 +suid 23,0 +) +) +) +*136 (CptPort +uid 3921,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3922,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,36625,138000,37375" +) +tg (CPTG +uid 3923,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3924,0 +va (VaSet +) +xt "139000,36500,142300,37500" +st "ramAddr" +blo "139000,37300" +) +) +thePort (LogicalPort +decl (Decl +n "ramAddr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 3 +suid 24,0 +) +) +) +] +shape (Rectangle +uid 3926,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "138000,33000,154000,49000" +) +oxt "34000,6000,50000,22000" +ttg (MlTextGroup +uid 3927,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*137 (Text +uid 3928,0 +va (VaSet +font "courier,8,1" +) +xt "137850,49500,141150,50500" +st "memory" +blo "137850,50300" +tm "BdLibraryNameMgr" +) +*138 (Text +uid 3929,0 +va (VaSet +font "courier,8,1" +) +xt "137850,50500,150150,51500" +st "sdramControllerBuildAddress" +blo "137850,51300" +tm "CptNameMgr" +) +*139 (Text +uid 3930,0 +va (VaSet +font "courier,8,1" +) +xt "137850,51500,139650,52500" +st "U_3" +blo "137850,52300" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3931,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3932,0 +text (MLText +uid 3933,0 +va (VaSet +font "courier,8,0" +) +xt "138000,53000,169000,57500" +st "addressBitNb = addressBitNb ( positive ) +chipAddressBitNb = chipAddressBitNb ( positive ) +chipBankAddressBitNb = chipBankAddressBitNb ( positive ) +rowAddressBitNb = rowAddressBitNb ( positive ) +colAddressBitNb = colAddressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "addressBitNb" +) +(GiElement +name "chipAddressBitNb" +type "positive" +value "chipAddressBitNb" +) +(GiElement +name "chipBankAddressBitNb" +type "positive" +value "chipBankAddressBitNb" +) +(GiElement +name "rowAddressBitNb" +type "positive" +value "rowAddressBitNb" +) +(GiElement +name "colAddressBitNb" +type "positive" +value "colAddressBitNb" +) +] +) +viewicon (ZoomableIcon +uid 3934,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "138250,47250,139750,48750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*140 (SaComponent +uid 4230,0 +optionalChildren [ +*141 (CptPort +uid 4158,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4159,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,46625,74750,47375" +) +tg (CPTG +uid 4160,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4161,0 +va (VaSet +) +xt "68400,46500,73000,47500" +st "addrSelCol" +ju 2 +blo "73000,47300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrSelCol" +t "std_ulogic" +o 8 +suid 149,0 +) +) +) +*142 (CptPort +uid 4162,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4163,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,42625,74750,43375" +) +tg (CPTG +uid 4164,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4165,0 +va (VaSet +) +xt "66200,42500,73000,43500" +st "addrSelModeReg" +ju 2 +blo "73000,43300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrSelModeReg" +t "std_ulogic" +o 9 +suid 150,0 +) +) +) +*143 (CptPort +uid 4166,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4167,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,40625,74750,41375" +) +tg (CPTG +uid 4168,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4169,0 +va (VaSet +) +xt "66000,40500,73000,41500" +st "addrSelPrecharge" +ju 2 +blo "73000,41300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrSelPrecharge" +t "std_ulogic" +o 10 +suid 151,0 +) +) +) +*144 (CptPort +uid 4170,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4171,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,44625,74750,45375" +) +tg (CPTG +uid 4172,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4173,0 +va (VaSet +) +xt "68100,44500,73000,45500" +st "addrSelRow" +ju 2 +blo "73000,45300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrSelRow" +t "std_ulogic" +o 11 +suid 152,0 +) +) +) +*145 (CptPort +uid 4174,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4175,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,54625,58000,55375" +) +tg (CPTG +uid 4176,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4177,0 +va (VaSet +) +xt "59000,54500,61100,55500" +st "clock" +blo "59000,55300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 153,0 +) +) +) +*146 (CptPort +uid 4178,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4179,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,54625,74750,55375" +) +tg (CPTG +uid 4180,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4181,0 +va (VaSet +) +xt "67700,54500,73000,55500" +st "commandBus" +ju 2 +blo "73000,55300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "commandBus" +t "std_ulogic_vector" +b "( commandBusBitNb-1 DOWNTO 0 )" +o 12 +suid 154,0 +) +) +) +*147 (CptPort +uid 4182,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4183,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,36625,58000,37375" +) +tg (CPTG +uid 4184,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4185,0 +va (VaSet +) +xt "59000,36500,66500,37500" +st "endOfRefreshCount" +blo "59000,37300" +) +) +thePort (LogicalPort +decl (Decl +n "endOfRefreshCount" +t "std_ulogic" +o 2 +suid 155,0 +) +) +) +*148 (CptPort +uid 4186,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4187,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,36625,74750,37375" +) +tg (CPTG +uid 4188,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4189,0 +va (VaSet +) +xt "67400,36500,73000,37500" +st "powerUpDone" +ju 2 +blo "73000,37300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "powerUpDone" +t "std_ulogic" +o 13 +suid 156,0 +) +) +) +*149 (CptPort +uid 4190,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4191,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,52625,74750,53375" +) +tg (CPTG +uid 4192,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4193,0 +va (VaSet +) +xt "67600,52500,73000,53500" +st "ramDataValid" +ju 2 +blo "73000,53300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ramDataValid" +t "std_ulogic" +o 14 +suid 157,0 +) +) +) +*150 (CptPort +uid 4194,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4195,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,52625,58000,53375" +) +tg (CPTG +uid 4196,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4197,0 +va (VaSet +) +xt "59000,52500,61600,53500" +st "ramEn" +blo "59000,53300" +) +) +thePort (LogicalPort +decl (Decl +n "ramEn" +t "std_ulogic" +o 3 +suid 158,0 +) +) +) +*151 (CptPort +uid 4198,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4199,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,48625,58000,49375" +) +tg (CPTG +uid 4200,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4201,0 +va (VaSet +) +xt "59000,48500,62100,49500" +st "readAck" +blo "59000,49300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "readAck" +t "std_ulogic" +o 15 +suid 159,0 +) +) +) +*152 (CptPort +uid 4202,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4203,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,46625,58000,47375" +) +tg (CPTG +uid 4204,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4205,0 +va (VaSet +) +xt "59000,46500,64200,47500" +st "readRequest" +blo "59000,47300" +) +) +thePort (LogicalPort +decl (Decl +n "readRequest" +t "std_ulogic" +o 4 +suid 160,0 +) +) +) +*153 (CptPort +uid 4206,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4207,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,56625,58000,57375" +) +tg (CPTG +uid 4208,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4209,0 +va (VaSet +) +xt "59000,56500,61100,57500" +st "reset" +blo "59000,57300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +suid 161,0 +) +) +) +*154 (CptPort +uid 4210,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4211,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,48625,74750,49375" +) +tg (CPTG +uid 4212,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4213,0 +va (VaSet +) +xt "68200,48500,73000,49500" +st "sampleData" +ju 2 +blo "73000,49300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sampleData" +t "std_ulogic" +o 16 +suid 162,0 +) +) +) +*155 (CptPort +uid 4214,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4215,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,38625,58000,39375" +) +tg (CPTG +uid 4216,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4217,0 +va (VaSet +) +xt "59000,38500,62900,39500" +st "timerDone" +blo "59000,39300" +) +) +thePort (LogicalPort +decl (Decl +n "timerDone" +t "std_ulogic_vector" +b "( 1 TO maxDelayPeriodNb )" +o 6 +suid 163,0 +) +) +) +*156 (CptPort +uid 4218,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4219,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,38625,74750,39375" +) +tg (CPTG +uid 4220,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4221,0 +va (VaSet +) +xt "68900,38500,73000,39500" +st "timerStart" +ju 2 +blo "73000,39300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "timerStart" +t "std_ulogic" +o 17 +suid 164,0 +) +) +) +*157 (CptPort +uid 4222,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4223,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,44625,58000,45375" +) +tg (CPTG +uid 4224,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4225,0 +va (VaSet +) +xt "59000,44500,62200,45500" +st "writeAck" +blo "59000,45300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "writeAck" +t "std_ulogic" +o 18 +suid 165,0 +) +) +) +*158 (CptPort +uid 4226,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4227,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,42625,58000,43375" +) +tg (CPTG +uid 4228,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4229,0 +va (VaSet +) +xt "59000,42500,64300,43500" +st "writeRequest" +blo "59000,43300" +) +) +thePort (LogicalPort +decl (Decl +n "writeRequest" +t "std_ulogic" +o 7 +suid 166,0 +) +) +) +] +shape (Rectangle +uid 4231,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "58000,33000,74000,59000" +) +oxt "35000,6000,51000,32000" +ttg (MlTextGroup +uid 4232,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*159 (Text +uid 4233,0 +va (VaSet +font "courier,8,1" +) +xt "58750,59000,62050,60000" +st "memory" +blo "58750,59800" +tm "BdLibraryNameMgr" +) +*160 (Text +uid 4234,0 +va (VaSet +font "courier,8,1" +) +xt "58750,60000,67250,61000" +st "sdramControllerFsm" +blo "58750,60800" +tm "CptNameMgr" +) +*161 (Text +uid 4235,0 +va (VaSet +font "courier,8,1" +) +xt "58750,61000,60550,62000" +st "U_0" +blo "58750,61800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4236,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4237,0 +text (MLText +uid 4238,0 +va (VaSet +font "courier,8,0" +) +xt "39000,62000,85000,71000" +st "commandBusBitNb = commandBusBitNb ( positive ) +maxDelayPeriodNb = maxDelayPeriodNb ( positive ) +prechargeToRefreshPeriodNb = 2 ( positive ) --66MHz * 20 ns = 1.32 +refreshDelayPeriodNb = 5 ( positive ) --66MHz * 66ns = 4.356 +loadModeToActivePeriodNb = 1 ( positive ) --1 CK +activeToWritePeriodNb = 2 ( positive ) --66MHz * 20ns = 1.32 +writeToActivePeriodNb = 3 ( positive ) --1 CK + 66MHz * 20ns = 2.32 +activeToReadPeriodNb = 2 ( positive ) --66MHz * 20ns = 1.32 +readToSamplePeriodNb = 2 ( positive ) --2 CK with latency = 2 +readToActivePeriodNb = 3 ( positive ) --1 CK + 66MHz * 20ns = 2.32 " +) +header "" +) +elements [ +(GiElement +name "commandBusBitNb" +type "positive" +value "commandBusBitNb" +) +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "maxDelayPeriodNb" +) +(GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +(GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +(GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +(GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +(GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +] +) +viewicon (ZoomableIcon +uid 4239,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "58250,57250,59750,58750" +iconName "StateMachineViewIcon.png" +iconMaskName "StateMachineViewIcon.msk" +ftype 3 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*162 (Wire +uid 57,0 +shape (OrthoPolyLine +uid 58,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "154750,37000,162000,37000" +pts [ +"162000,37000" +"154750,37000" +] +) +start &1 +end &134 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 61,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 62,0 +va (VaSet +font "courier,12,0" +) +xt "156000,35600,165700,37000" +st "memAddress" +blo "156000,36800" +tm "WireNameMgr" +) +) +on &2 +) +*163 (Wire +uid 85,0 +shape (OrthoPolyLine +uid 86,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "74750,76000,83000,76000" +pts [ +"83000,76000" +"74750,76000" +] +) +start &3 +end &111 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 89,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 90,0 +va (VaSet +font "courier,12,0" +) +xt "76000,74600,84100,76000" +st "memDataIn" +blo "76000,75800" +tm "WireNameMgr" +) +) +on &4 +) +*164 (Wire +uid 99,0 +shape (OrthoPolyLine +uid 100,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "154750,61000,162000,61000" +pts [ +"162000,61000" +"154750,61000" +] +) +start &5 +end &102 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 103,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 104,0 +va (VaSet +font "courier,12,0" +) +xt "161000,59600,170900,61000" +st "memDataOut" +blo "161000,60800" +tm "WireNameMgr" +) +) +on &6 +) +*165 (Wire +uid 113,0 +shape (OrthoPolyLine +uid 114,0 +va (VaSet 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+sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 145,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 146,0 +va (VaSet +font "courier,12,0" +) +xt "10000,47600,14800,49000" +st "ramRd" +blo "10000,48800" +tm "WireNameMgr" +) +) +on &12 +) +*168 (Wire +uid 169,0 +shape (OrthoPolyLine +uid 170,0 +va (VaSet +vasetType 3 +) +xt "54000,57000,57250,57000" +pts [ +"54000,57000" +"57250,57000" +] +) +start &15 +end &153 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 173,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 174,0 +va (VaSet +font "courier,12,0" +) +xt "53000,55600,57100,57000" +st "reset" +blo "53000,56800" +tm "WireNameMgr" +) +) +on &16 +) +*169 (Wire +uid 183,0 +shape (OrthoPolyLine +uid 184,0 +va (VaSet +vasetType 3 +) +xt "114000,81000,122000,81000" +pts [ +"122000,81000" +"114000,81000" +] +) +start &17 +end &59 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 187,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 188,0 +va (VaSet +font "courier,12,0" +) +xt "117000,79600,123300,81000" +st "sdCas_n" +blo "117000,80800" +tm "WireNameMgr" +) +) +on &18 +) +*170 (Wire +uid 197,0 +shape (OrthoPolyLine +uid 198,0 +va (VaSet +vasetType 3 +) +xt "154000,19000,162000,19000" +pts [ +"162000,19000" +"154000,19000" +] +) +start &19 +end &52 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 201,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 202,0 +va (VaSet +font "courier,12,0" +) +xt "159000,17600,163700,19000" +st "sdCke" +blo "159000,18800" +tm "WireNameMgr" +) +) +on &20 +) +*171 (Wire +uid 211,0 +shape (OrthoPolyLine +uid 212,0 +va (VaSet +vasetType 3 +) +xt "154000,21000,162000,21000" +pts [ +"162000,21000" +"154000,21000" +] +) +start &21 +end &52 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 215,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 216,0 +va (VaSet +font "courier,12,0" +) +xt "159000,19600,163200,21000" +st "sdClk" +blo "159000,20800" +tm "WireNameMgr" +) +) +on &22 +) +*172 (Wire +uid 225,0 +shape (OrthoPolyLine +uid 226,0 +va (VaSet +vasetType 3 +) +xt "114000,77000,122000,77000" +pts [ +"122000,77000" +"114000,77000" +] +) +start &23 +end &59 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 229,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 230,0 +va (VaSet +font "courier,12,0" +) +xt "118000,75600,123500,77000" +st "sdCs_n" +blo "118000,76800" +tm "WireNameMgr" +) +) +on &24 +) +*173 (Wire +uid 267,0 +shape (OrthoPolyLine +uid 268,0 +va (VaSet +vasetType 3 +) +xt "114000,79000,122000,79000" +pts [ +"122000,79000" +"114000,79000" +] +) +start &25 +end &59 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 271,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 272,0 +va (VaSet +font "courier,12,0" +) +xt "117000,77600,123200,79000" +st "sdRas_n" +blo "117000,78800" +tm "WireNameMgr" +) +) +on &26 +) +*174 (Wire +uid 605,0 +shape (OrthoPolyLine +uid 606,0 +va (VaSet +vasetType 3 +) +xt "54000,55000,57250,55000" +pts [ +"54000,55000" +"57250,55000" +] +) +start &38 +end &145 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 609,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 610,0 +va (VaSet +font "courier,12,0" +) +xt "54000,53600,57800,55000" +st "clock" +blo "54000,54800" +tm "WireNameMgr" +) +) +on &39 +) +*175 (Wire +uid 619,0 +shape (OrthoPolyLine +uid 620,0 +va (VaSet +vasetType 3 +) +xt "74750,53000,82000,53000" +pts [ +"74750,53000" +"82000,53000" +] +) +start &149 +end &40 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 623,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 624,0 +va (VaSet +font "courier,12,0" +) +xt "76000,51600,86000,53000" +st "ramDataValid" +blo "76000,52800" +tm "WireNameMgr" +) +) +on &41 +) +*176 (Wire +uid 633,0 +shape (OrthoPolyLine +uid 634,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "130000,37000,137250,37000" +pts [ +"130000,37000" +"137250,37000" +] +) +start &42 +end &136 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 637,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 638,0 +va (VaSet +font "courier,12,0" +) +xt "130000,35600,136100,37000" +st "ramAddr" +blo "130000,36800" +tm "WireNameMgr" +) +) +on &43 +) +*177 (Wire +uid 647,0 +shape (OrthoPolyLine +uid 648,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "130000,61000,137250,61000" +pts [ +"130000,61000" +"137250,61000" +] +) +start &44 +end &103 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 651,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 652,0 +va (VaSet +font "courier,12,0" +) +xt "129000,59600,138300,61000" +st "ramDataOut" +blo "129000,60800" +tm "WireNameMgr" +) +) +on &45 +) +*178 (Wire +uid 661,0 +shape (OrthoPolyLine +uid 662,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "50000,76000,57250,76000" +pts [ +"57250,76000" +"50000,76000" +] +) +start &112 +end &46 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 665,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 666,0 +va (VaSet +font "courier,12,0" +) +xt "50000,74600,57500,76000" +st "ramDataIn" +blo "50000,75800" +tm "WireNameMgr" +) +) +on &47 +) +*179 (Wire +uid 1322,0 +shape (OrthoPolyLine +uid 1323,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "114000,85000,122000,85000" +pts [ +"114000,85000" +"122000,85000" +] +) +start &59 +end &48 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1326,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1327,0 +va (VaSet +font "courier,12,0" +) +xt "117000,83600,122100,85000" +st "sdDqm" +blo "117000,84800" +tm "WireNameMgr" +) +) +on &49 +) +*180 (Wire +uid 1336,0 +shape (OrthoPolyLine +uid 1337,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "154750,39000,162000,39000" +pts [ +"154750,39000" +"162000,39000" +] +) +start &135 +end &50 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1340,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1341,0 +va (VaSet +font "courier,12,0" +) +xt "156000,37600,168800,39000" +st "memBankAddress" +blo "156000,38800" +tm "WireNameMgr" +) +) +on &51 +) +*181 (Wire +uid 1637,0 +shape (OrthoPolyLine +uid 1638,0 +va (VaSet +vasetType 3 +) +xt "94000,43000,97250,43000" +pts [ +"94000,43000" +"97250,43000" +] +) +end &122 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1643,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1644,0 +va (VaSet +font "courier,12,0" +) +xt "93000,41600,97100,43000" +st "reset" +blo "93000,42800" +tm "WireNameMgr" +) +) +on &16 +) +*182 (Wire +uid 1645,0 +shape (OrthoPolyLine +uid 1646,0 +va (VaSet +vasetType 3 +) +xt "94000,41000,97250,41000" +pts [ +"94000,41000" +"97250,41000" +] +) +end &119 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1651,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1652,0 +va (VaSet +font "courier,12,0" +) +xt "94000,39600,97800,41000" +st "clock" +blo "94000,40800" +tm "WireNameMgr" +) +) +on &39 +) +*183 (Wire +uid 1655,0 +shape (OrthoPolyLine +uid 1656,0 +va (VaSet +vasetType 3 +) +xt "74750,37000,97250,37000" +pts [ +"74750,37000" +"97250,37000" +] +) +start &148 +end &121 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1661,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1662,0 +va (VaSet +font "courier,12,0" +) +xt "76000,35600,86600,37000" +st "powerUpDone" +blo "76000,36800" +tm "WireNameMgr" +) +) +on &56 +) +*184 (Wire +uid 1671,0 +shape (OrthoPolyLine +uid 1672,0 +va (VaSet +vasetType 3 +) +xt "54000,29000,118000,37000" +pts [ +"114750,37000" +"118000,37000" +"118000,29000" +"54000,29000" +"54000,37000" +"57250,37000" +] +) +start &120 +end &147 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1677,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1678,0 +va (VaSet +font "courier,12,0" +) +xt "117000,35600,131000,37000" +st "endOfRefreshCount" +blo "117000,36800" +tm "WireNameMgr" +) +) +on &57 +) +*185 (Wire +uid 1687,0 +shape (OrthoPolyLine +uid 1688,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "74750,55000,98000,77000" +pts [ +"74750,55000" +"86000,55000" +"86000,77000" +"98000,77000" +] +) +start &146 +end &59 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1693,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1694,0 +va (VaSet +font "courier,12,0" +) +xt "88000,75600,97900,77000" +st "commandBus" +blo "88000,76800" +tm "WireNameMgr" +) +) +on &58 +) +*186 (Wire +uid 1761,0 +shape (OrthoPolyLine +uid 1762,0 +va (VaSet +vasetType 3 +) +xt "74750,39000,97250,57000" +pts [ +"74750,39000" +"90000,39000" +"90000,57000" +"97250,57000" +] +) +start &156 +end &96 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1767,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1768,0 +va (VaSet +font "courier,12,0" +) +xt "76000,37600,83900,39000" +st "timerStart" +blo "76000,38800" +tm "WireNameMgr" +) +) +on &63 +) +*187 (Wire +uid 1769,0 +shape (OrthoPolyLine +uid 1770,0 +va (VaSet +vasetType 3 +) +xt "94000,61000,97250,61000" +pts [ +"94000,61000" +"97250,61000" +] +) +end &93 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1775,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1776,0 +va (VaSet +font "courier,12,0" +) +xt "94000,59600,97800,61000" +st "clock" +blo "94000,60800" +tm "WireNameMgr" +) +) +on &39 +) +*188 (Wire +uid 1777,0 +shape (OrthoPolyLine +uid 1778,0 +va (VaSet +vasetType 3 +) +xt "94000,63000,97250,63000" +pts [ +"94000,63000" +"97250,63000" +] +) +end &94 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1783,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1784,0 +va (VaSet +font "courier,12,0" +) +xt "93000,61600,97100,63000" +st "reset" +blo "93000,62800" +tm "WireNameMgr" +) +) +on &16 +) +*189 (Wire +uid 1789,0 +shape (OrthoPolyLine +uid 1790,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "52000,27000,120000,57000" +pts [ +"114750,57000" +"120000,57000" +"120000,27000" +"52000,27000" +"52000,39000" +"57250,39000" +] +) +start &95 +end &155 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1795,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1796,0 +va (VaSet +font "courier,12,0" +) +xt "117000,55600,124300,57000" +st "timerDone" +blo "117000,56800" +tm "WireNameMgr" +) +) +on &64 +) +*190 (Wire +uid 1916,0 +shape (OrthoPolyLine +uid 1917,0 +va (VaSet +vasetType 3 +) +xt "130000,39000,137250,39000" +pts [ +"130000,39000" +"137250,39000" +] +) +end &132 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1922,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1923,0 +va (VaSet +font "courier,12,0" +) +xt "127000,37600,139800,39000" +st "addrSelPrecharge" +blo "127000,38800" +tm "WireNameMgr" +) +) +on &65 +) +*191 (Wire +uid 1926,0 +shape (OrthoPolyLine +uid 1927,0 +va (VaSet +vasetType 3 +) +xt "74750,41000,82000,41000" +pts [ +"74750,41000" +"82000,41000" +] +) +start &143 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 1932,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1933,0 +va (VaSet +font "courier,12,0" +) +xt "76000,39600,88800,41000" +st "addrSelPrecharge" +blo "76000,40800" +tm "WireNameMgr" +) +) +on &65 +) +*192 (Wire +uid 2043,0 +shape (OrthoPolyLine +uid 2044,0 +va (VaSet +vasetType 3 +) +xt "74750,43000,82000,43000" +pts [ +"74750,43000" +"82000,43000" +] +) +start &142 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 2049,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2050,0 +va (VaSet +font "courier,12,0" +) +xt "76000,41600,88200,43000" +st "addrSelModeReg" +blo "76000,42800" +tm "WireNameMgr" +) +) +on &66 +) +*193 (Wire +uid 2053,0 +shape (OrthoPolyLine +uid 2054,0 +va (VaSet +vasetType 3 +) +xt "130000,41000,137250,41000" +pts [ +"130000,41000" +"137250,41000" +] +) +end &131 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2059,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2060,0 +va (VaSet +font "courier,12,0" +) +xt "127000,39600,139200,41000" +st "addrSelModeReg" +blo "127000,40800" +tm "WireNameMgr" +) +) +on &66 +) +*194 (Wire +uid 2063,0 +shape (OrthoPolyLine +uid 2064,0 +va (VaSet +vasetType 3 +) +xt "130000,63000,137250,63000" +pts [ +"130000,63000" +"137250,63000" +] +) +end &104 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2069,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2070,0 +va (VaSet +font "courier,12,0" +) +xt "131000,61600,136000,63000" +st "ramWr" +blo "131000,62800" +tm "WireNameMgr" +) +) +on &14 +) +*195 (Wire +uid 2071,0 +shape (OrthoPolyLine +uid 2072,0 +va (VaSet +vasetType 3 +) +xt "134000,67000,137250,67000" +pts [ +"134000,67000" +"137250,67000" +] +) +end &101 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2077,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2078,0 +va (VaSet +font "courier,12,0" +) +xt "134000,65600,137800,67000" +st "clock" +blo "134000,66800" +tm "WireNameMgr" +) +) +on &39 +) +*196 (Wire +uid 2079,0 +shape (OrthoPolyLine +uid 2080,0 +va (VaSet +vasetType 3 +) +xt "134000,69000,137250,69000" +pts [ +"134000,69000" +"137250,69000" +] +) +end &105 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2085,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2086,0 +va (VaSet +font "courier,12,0" +) +xt "133000,67600,137100,69000" +st "reset" +blo "133000,68800" +tm "WireNameMgr" +) +) +on &16 +) +*197 (Wire +uid 2234,0 +shape (OrthoPolyLine +uid 2235,0 +va (VaSet +vasetType 3 +) +xt "10000,27000,17250,27000" +pts [ +"10000,27000" +"17250,27000" +] +) +start &13 +end &71 +es 0 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2240,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2241,0 +va (VaSet +font "courier,12,0" +) +xt "10000,25600,15000,27000" +st "ramWr" +blo "10000,26800" +tm "WireNameMgr" +) +) +on &14 +) +*198 (Wire +uid 2242,0 +shape (OrthoPolyLine +uid 2243,0 +va (VaSet +vasetType 3 +) +xt "14000,33000,17250,33000" +pts [ +"14000,33000" +"17250,33000" +] +) +end &70 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2248,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2249,0 +va (VaSet +font "courier,12,0" +) +xt "14000,31600,17800,33000" +st "clock" +blo "14000,32800" +tm "WireNameMgr" +) +) +on &39 +) +*199 (Wire +uid 2250,0 +shape (OrthoPolyLine +uid 2251,0 +va (VaSet +vasetType 3 +) +xt "14000,35000,17250,35000" +pts [ +"14000,35000" +"17250,35000" +] +) +end &72 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2256,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2257,0 +va (VaSet +font "courier,12,0" +) +xt "13000,33600,17100,35000" +st "reset" +blo "13000,34800" +tm "WireNameMgr" +) +) +on &16 +) +*200 (Wire +uid 2258,0 +shape (OrthoPolyLine +uid 2259,0 +va (VaSet +vasetType 3 +) +xt "34750,27000,42000,27000" +pts [ +"34750,27000" +"42000,27000" +] +) +start &74 +ss 0 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2264,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2265,0 +va (VaSet +font "courier,12,0" +) +xt "36000,25600,46000,27000" +st "writeRequest" +blo "36000,26800" +tm "WireNameMgr" +) +) +on &67 +) +*201 (Wire +uid 2268,0 +shape (OrthoPolyLine +uid 2269,0 +va (VaSet +vasetType 3 +) +xt "10000,29000,17250,29000" +pts [ +"17250,29000" +"10000,29000" +] +) +start &73 +ss 0 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2274,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2275,0 +va (VaSet +font "courier,12,0" +) +xt "11000,27600,17100,29000" +st "writeAck" +blo "11000,28800" +tm "WireNameMgr" +) +) +on &68 +) +*202 (Wire +uid 2342,0 +shape (OrthoPolyLine +uid 2343,0 +va (VaSet +vasetType 3 +) +xt "50000,45000,57250,45000" +pts [ +"57250,45000" +"50000,45000" +] +) +start &157 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2348,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2349,0 +va (VaSet +font "courier,12,0" +) +xt "49000,43600,55100,45000" +st "writeAck" +blo "49000,44800" +tm "WireNameMgr" +) +) +on &68 +) +*203 (Wire +uid 2350,0 +shape (OrthoPolyLine +uid 2351,0 +va (VaSet +vasetType 3 +) +xt "50000,43000,57250,43000" +pts [ +"57250,43000" +"50000,43000" +] +) +start &158 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2356,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2357,0 +va (VaSet +font "courier,12,0" +) +xt "48000,41600,58000,43000" +st "writeRequest" +blo "48000,42800" +tm "WireNameMgr" +) +) +on &67 +) +*204 (Wire +uid 2358,0 +shape (OrthoPolyLine +uid 2359,0 +va (VaSet +vasetType 3 +) +xt "74750,45000,82000,45000" +pts [ +"74750,45000" +"82000,45000" +] +) +start &144 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 2364,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2365,0 +va (VaSet +font "courier,12,0" +) +xt "76000,43600,85100,45000" +st "addrSelRow" +blo "76000,44800" +tm "WireNameMgr" +) +) +on &78 +) +*205 (Wire +uid 2368,0 +shape (OrthoPolyLine +uid 2369,0 +va (VaSet +vasetType 3 +) +xt "130000,43000,137250,43000" +pts [ +"130000,43000" +"137250,43000" +] +) +end &133 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2374,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2375,0 +va (VaSet +font "courier,12,0" +) +xt "128000,41600,137100,43000" +st "addrSelRow" +blo "128000,42800" +tm "WireNameMgr" +) +) +on &78 +) +*206 (Wire +uid 2376,0 +shape (OrthoPolyLine +uid 2377,0 +va (VaSet +vasetType 3 +) +xt "74750,47000,82000,47000" +pts [ +"74750,47000" +"82000,47000" +] +) +start &141 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 2382,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2383,0 +va (VaSet +font "courier,12,0" +) +xt "76000,45600,84400,47000" +st "addrSelCol" +blo "76000,46800" +tm "WireNameMgr" +) +) +on &79 +) +*207 (Wire +uid 2386,0 +shape (OrthoPolyLine +uid 2387,0 +va (VaSet +vasetType 3 +) +xt "130000,45000,137250,45000" +pts [ +"130000,45000" +"137250,45000" +] +) +end &130 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2392,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2393,0 +va (VaSet +font "courier,12,0" +) +xt "128000,43600,136400,45000" +st "addrSelCol" +blo "128000,44800" +tm "WireNameMgr" +) +) +on &79 +) +*208 (Wire +uid 2428,0 +shape (OrthoPolyLine +uid 2429,0 +va (VaSet +vasetType 3 +) +xt "14000,57000,17250,57000" +pts [ +"14000,57000" +"17250,57000" +] +) +end &83 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2432,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2433,0 +va (VaSet +font "courier,12,0" +) +xt "13000,55600,17100,57000" +st "reset" +blo "13000,56800" +tm "WireNameMgr" +) +) +on &16 +) +*209 (Wire +uid 2434,0 +shape (OrthoPolyLine +uid 2435,0 +va (VaSet +vasetType 3 +) +xt "14000,55000,17250,55000" +pts [ +"14000,55000" +"17250,55000" +] +) +end &81 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2438,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2439,0 +va (VaSet +font "courier,12,0" +) +xt "14000,53600,17800,55000" +st "clock" +blo "14000,54800" +tm "WireNameMgr" +) +) +on &39 +) +*210 (Wire +uid 2440,0 +shape (OrthoPolyLine +uid 2441,0 +va (VaSet +vasetType 3 +) +xt "10000,51000,17250,51000" +pts [ +"17250,51000" +"10000,51000" +] +) +start &84 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2446,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2447,0 +va (VaSet +font "courier,12,0" +) +xt "11000,49600,16800,51000" +st "readAck" +blo "11000,50800" +tm "WireNameMgr" +) +) +on &89 +) +*211 (Wire +uid 2448,0 +shape (OrthoPolyLine +uid 2449,0 +va (VaSet +vasetType 3 +) +xt "34750,49000,42000,49000" +pts [ +"34750,49000" +"42000,49000" +] +) +start &85 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2454,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2455,0 +va (VaSet +font "courier,12,0" +) +xt "36000,47600,45700,49000" +st "readRequest" +blo "36000,48800" +tm "WireNameMgr" +) +) +on &90 +) +*212 (Wire +uid 2460,0 +shape (OrthoPolyLine +uid 2461,0 +va (VaSet +vasetType 3 +) +xt "50000,47000,57250,47000" +pts [ +"57250,47000" +"50000,47000" +] +) +start &152 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2466,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2467,0 +va (VaSet +font "courier,12,0" +) +xt "49000,45600,58700,47000" +st "readRequest" +blo "49000,46800" +tm "WireNameMgr" +) +) +on &90 +) +*213 (Wire +uid 2468,0 +shape (OrthoPolyLine +uid 2469,0 +va (VaSet +vasetType 3 +) +xt "50000,49000,57250,49000" +pts [ +"57250,49000" +"50000,49000" +] +) +start &151 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG 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(RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*351 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*352 (GroupColHdr +tm "GroupColHdrMgr" +) +*353 (NameColHdr +tm "GenericNameColHdrMgr" +) +*354 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*355 (InitColHdr +tm "GenericValueColHdrMgr" +) +*356 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*357 (EolColHdr +tm "GenericEolColHdrMgr" +) +*358 (LogGeneric +generic (GiElement +name "addressBitNb" +type "positive" +value "24" +) +uid 852,0 +) +*359 (LogGeneric +generic (GiElement +name "dataBitNb" +type "positive" +value "16" +) +uid 854,0 +) +*360 (LogGeneric +generic (GiElement +name "chipAddressBitNb" +type "positive" +value "12" +) +uid 1038,0 +) +*361 (LogGeneric +generic (GiElement +name "chipBankAddressBitNb" +type "positive" +value "2" +) +uid 1444,0 +) +*362 (LogGeneric +generic (GiElement +name "rowAddressBitNb" +type "positive" +value "12" +) +uid 3935,0 +) +*363 (LogGeneric +generic (GiElement +name "colAddressBitNb" +type "positive" +value "9" +) +uid 3937,0 +) +*364 (LogGeneric +generic (GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +uid 4122,0 +) +*365 (LogGeneric +generic (GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +uid 4124,0 +) +*366 (LogGeneric +generic (GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +uid 4126,0 +) +*367 (LogGeneric +generic (GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +uid 4128,0 +) +*368 (LogGeneric +generic (GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +uid 4130,0 +) +*369 (LogGeneric +generic (GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +uid 4132,0 +) +*370 (LogGeneric +generic (GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +uid 4134,0 +) +*371 (LogGeneric +generic (GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +uid 4136,0 +) +*372 (LogGeneric +generic (GiElement +name "delayCounterbitNb" +type "positive" +value "13" +e "66MHz * 100us = 6600 < 8K" +) +uid 4138,0 +) +*373 (LogGeneric +generic (GiElement +name "refreshPeriodNb" +type "positive" +value "1031" +e "66MHz * 64ms / 4096" +) +uid 4140,0 +) +*374 (LogGeneric +generic (GiElement +name "maxDelayPeriodNb" +type "positive" +value "5" +e "66MHz*66ns = 4.356" +) +uid 4341,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 399,0 +optionalChildren [ +*375 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *376 (MRCItem +litem &346 +pos 17 +dimension 20 +) +uid 401,0 +optionalChildren [ +*377 (MRCItem +litem &347 +pos 0 +dimension 20 +uid 402,0 +) +*378 (MRCItem +litem &348 +pos 1 +dimension 23 +uid 403,0 +) +*379 (MRCItem +litem &349 +pos 2 +hidden 1 +dimension 20 +uid 404,0 +) +*380 (MRCItem +litem &358 +pos 0 +dimension 20 +uid 851,0 +) +*381 (MRCItem +litem &359 +pos 1 +dimension 20 +uid 853,0 +) +*382 (MRCItem +litem &360 +pos 2 +dimension 20 +uid 1037,0 +) +*383 (MRCItem +litem &361 +pos 3 +dimension 20 +uid 1443,0 +) +*384 (MRCItem +litem &362 +pos 4 +dimension 20 +uid 3936,0 +) +*385 (MRCItem +litem &363 +pos 5 +dimension 20 +uid 3938,0 +) +*386 (MRCItem +litem &364 +pos 6 +dimension 20 +uid 4123,0 +) +*387 (MRCItem +litem &365 +pos 7 +dimension 20 +uid 4125,0 +) +*388 (MRCItem +litem &366 +pos 8 +dimension 20 +uid 4127,0 +) +*389 (MRCItem +litem &367 +pos 9 +dimension 20 +uid 4129,0 +) +*390 (MRCItem +litem &368 +pos 10 +dimension 20 +uid 4131,0 +) +*391 (MRCItem +litem &369 +pos 11 +dimension 20 +uid 4133,0 +) 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386,0 +type 1 +) +activeModelName "BlockDiag:GEN" +) diff --git a/Libs/Memory/hds/sdram@controller/symbol.sb b/Libs/Memory/hds/sdram@controller/symbol.sb new file mode 100644 index 0000000..0ae9d39 --- /dev/null +++ b/Libs/Memory/hds/sdram@controller/symbol.sb @@ -0,0 +1,2973 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 44,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 186,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm 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"57000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 321,0 +va (VaSet +font "courier,8,0" +) +xt "0,21400,33500,22300" +st "memDataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "memDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 11 +suid 26,0 +) +) +) +*135 (CptPort +uid 322,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 323,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,19625,58750,20375" +) +tg (CPTG +uid 324,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 325,0 +va (VaSet +) +xt "53200,19500,57000,20500" +st "memWr_n" +ju 2 +blo "57000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 326,0 +va (VaSet +font "courier,8,0" +) +xt "0,22300,19000,23200" +st "memWr_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "memWr_n" +t "std_ulogic" +o 12 +suid 27,0 +) +) +) +*136 (CptPort +uid 327,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 328,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,27625,42000,28375" +) +tg (CPTG +uid 329,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 330,0 +va (VaSet +) +xt "43000,27500,45600,28500" +st "ramEn" +blo "43000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 331,0 +va (VaSet +font "courier,8,0" +) +xt "0,16000,19000,16900" +st "ramEn : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "ramEn" +t "std_ulogic" +o 5 +suid 28,0 +) +) +) +*137 (CptPort +uid 332,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 333,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,11625,42000,12375" +) +tg (CPTG +uid 334,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 335,0 +va (VaSet +) +xt "43000,11500,45700,12500" +st "ramRd" +blo "43000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 336,0 +va (VaSet +font "courier,8,0" +) +xt "0,16900,19000,17800" +st "ramRd : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "ramRd" +t "std_ulogic" +o 6 +suid 29,0 +) +) +) +*138 (CptPort +uid 337,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 338,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,13625,42000,14375" +) +tg (CPTG +uid 339,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 340,0 +va (VaSet +) +xt "43000,13500,45700,14500" +st "ramWr" +blo "43000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 341,0 +va (VaSet +font "courier,8,0" +) +xt "0,17800,19000,18700" +st "ramWr : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "ramWr" +t "std_ulogic" +o 7 +suid 30,0 +) +) +) +*139 (CptPort +uid 342,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 343,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,31625,42000,32375" +) +tg (CPTG +uid 344,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 345,0 +va (VaSet +) +xt "43000,31500,45100,32500" +st "reset" +blo "43000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 346,0 +va (VaSet +font "courier,8,0" +) +xt "0,18700,19000,19600" +st "reset : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 8 +suid 31,0 +) +) +) +*140 (CptPort +uid 347,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 348,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,17625,58750,18375" +) +tg (CPTG +uid 349,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 350,0 +va (VaSet +) +xt "53600,17500,57000,18500" +st "sdCas_n" +ju 2 +blo "57000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 351,0 +va (VaSet +font "courier,8,0" +) +xt "0,25000,19000,25900" +st "sdCas_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCas_n" +t "std_ulogic" +o 15 +suid 32,0 +) +) +) +*141 (CptPort +uid 352,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 353,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,23625,58750,24375" +) +tg (CPTG +uid 354,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 355,0 +va (VaSet +) +xt "54500,23500,57000,24500" +st "sdCke" +ju 2 +blo "57000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 356,0 +va (VaSet +font "courier,8,0" +) +xt "0,25900,19000,26800" +st "sdCke : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCke" +t "std_ulogic" +o 16 +suid 33,0 +) +) +) +*142 (CptPort +uid 357,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 358,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,25625,58750,26375" +) +tg (CPTG +uid 359,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 360,0 +va (VaSet +) +xt "54700,25500,57000,26500" +st "sdClk" +ju 2 +blo "57000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 361,0 +va (VaSet +font "courier,8,0" +) +xt "0,26800,19000,27700" +st "sdClk : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdClk" +t "std_ulogic" +o 17 +suid 34,0 +) +) +) +*143 (CptPort +uid 362,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 363,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,13625,58750,14375" +) +tg (CPTG +uid 364,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 365,0 +va (VaSet +) +xt "54000,13500,57000,14500" +st "sdCs_n" +ju 2 +blo "57000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 366,0 +va (VaSet +font "courier,8,0" +) +xt "0,27700,19000,28600" +st "sdCs_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCs_n" +t "std_ulogic" +o 18 +suid 35,0 +) +) +) +*144 (CptPort +uid 367,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 368,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,21625,58750,22375" +) +tg (CPTG +uid 369,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 370,0 +va (VaSet +) +xt "54100,21500,57000,22500" +st "sdDqm" +ju 2 +blo "57000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 371,0 +va (VaSet +font "courier,8,0" +) +xt "0,28600,28500,29500" +st "sdDqm : OUT std_ulogic_vector (1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdDqm" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 19 +suid 36,0 +) +) +) +*145 (CptPort +uid 377,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 378,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,15625,58750,16375" +) +tg (CPTG +uid 379,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 380,0 +va (VaSet +) +xt "53600,15500,57000,16500" +st "sdRas_n" +ju 2 +blo "57000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 381,0 +va (VaSet +font "courier,8,0" +) +xt "0,29500,19000,30400" +st "sdRas_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdRas_n" +t "std_ulogic" +o 20 +suid 38,0 +) +) +) +*146 (CptPort +uid 487,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 518,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,7625,42000,8375" +) +tg (CPTG +uid 489,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 490,0 +va (VaSet +) +xt "43000,7500,46900,8500" +st "ramDataIn" +blo "43000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 491,0 +va (VaSet +font "courier,8,0" +) +xt "0,23200,33500,24100" +st "ramDataIn : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ramDataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 13 +suid 42,0 +) +) +) +*147 (CptPort +uid 548,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 549,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,7625,58750,8375" +) +tg (CPTG +uid 550,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 551,0 +va (VaSet +) +xt "50200,7500,57000,8500" +st "memBankAddress" +ju 2 +blo "57000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 552,0 +va (VaSet +font "courier,8,0" +) +xt "0,20500,40000,21400" +st "memBankAddress : OUT std_ulogic_vector ( chipBankAddressBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "memBankAddress" +t "std_ulogic_vector" +b "( chipBankAddressBitNb-1 DOWNTO 0 )" +o 10 +suid 43,0 +) +) +) +*148 (CptPort +uid 651,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 652,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,29625,58750,30375" +) +tg (CPTG +uid 653,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 654,0 +va (VaSet +) +xt "51500,29500,57000,30500" +st "selectRefresh" +ju 2 +blo "57000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 655,0 +va (VaSet +font "courier,8,0" +) +xt "0,30400,18000,31300" +st "selectRefresh : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "selectRefresh" +t "std_ulogic" +o 21 +suid 44,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "42000,2000,58000,34000" +) +oxt "15000,6000,31000,34000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "courier,8,1" +) +xt "42550,34500,45550,35400" +st "Memory" +blo "42550,35200" +) +second (Text +uid 12,0 +va (VaSet +font "courier,8,1" +) +xt "42550,35400,50550,36300" +st "sdramController" +blo "42550,36100" +) +) +gi *149 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "courier,8,0" +) +xt "42000,38200,77500,55300" +st "Generic Declarations + +addressBitNb positive 24 +dataBitNb positive 16 +chipAddressBitNb positive 12 +chipBankAddressBitNb positive 2 +rowAddressBitNb positive 12 +colAddressBitNb positive 9 +activeToReadPeriodNb positive 2 --66MHz * 20ns = 1.32 +activeToWritePeriodNb positive 2 --66MHz * 20ns = 1.32 +loadModeToActivePeriodNb positive 1 --1 CK +prechargeToRefreshPeriodNb positive 2 --66MHz * 20 ns = 1.32 +readToActivePeriodNb positive 3 --1 CK + 66MHz * 20ns = 2.32 +readToSamplePeriodNb positive 2 --2 CK with latency = 2 +refreshDelayPeriodNb positive 5 --66MHz * 66ns = 4.356 +writeToActivePeriodNb positive 3 --1 CK + 66MHz * 20ns = 2.32 +delayCounterbitNb positive 13 --66MHz * 100us = 6600 < 8K +refreshPeriodNb positive 1031 --66MHz * 64ms / 4096 +maxDelayPeriodNb positive 5 --66MHz*66ns = 4.356 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "24" +) +(GiElement +name "dataBitNb" +type "positive" +value "16" +) +(GiElement +name "chipAddressBitNb" +type "positive" +value "12" +) +(GiElement +name "chipBankAddressBitNb" +type "positive" +value "2" +) +(GiElement +name "rowAddressBitNb" +type "positive" +value "12" +) +(GiElement +name "colAddressBitNb" +type "positive" +value "9" +) +(GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +(GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +(GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +(GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +(GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "delayCounterbitNb" +type "positive" +value "13" +e "66MHz * 100us = 6600 < 8K" +) +(GiElement +name "refreshPeriodNb" +type "positive" +value "1031" +e "66MHz * 64ms / 4096" +) +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "5" +e "66MHz*66ns = 4.356" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*150 (Grouping +uid 16,0 +optionalChildren [ +*151 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,48000,51000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,48000,49200,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*152 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,44000,55000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,44000,54800,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*153 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,46000,51000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,46000,50400,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*154 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,46000,34000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,46000,33800,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*155 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,45000,71000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,45200,64400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) 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"/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "fsm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@fsm" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerFsm" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "sdramControllerFsm" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "fsm.sm" +) +(vvPair +variable "f_logical" +value "fsm.sm" +) +(vvPair +variable "f_noext" +value "fsm" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/28/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "13:45:15" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Memory" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libs/Memory/work" +) +(vvPair +variable "mm" +value "08" +) +(vvPair +variable "module_name" +value "sdramControllerFsm" +) +(vvPair +variable "month" +value "Aug" +) +(vvPair +variable "month_long" +value "August" +) +(vvPair +variable "p" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@fsm/fsm.sm" +) +(vvPair +variable "p_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerFsm/fsm.sm" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sm" +) +(vvPair +variable "this_file" +value "fsm" +) +(vvPair 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"106200,96000,109800,97000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*18 (CommentText +uid 149,0 +shape (Rectangle +uid 150,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "110000,95000,127000,96000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 151,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "110200,95000,126400,96000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 121,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "106000,92000,147000,97000" +) +oxt "14000,66000,55000,71000" +) +*19 (State +uid 229,0 +shape (Circle +uid 230,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "22000,24000,30000,32000" +radius 4000 +) +name (Text +uid 231,0 +va (VaSet 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3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23600,29150,34400,29150" +pts [ +"23600,29150" +"34400,29150" +] +) +ttri (Triangle +uid 241,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23150,27925,23500,28275" +) +btri (Triangle +uid 242,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23150,26625,23500,26975" +) +entryActions (MLText +uid 243,0 +va (VaSet +) +xt "23600,28100,23600,28100" +tm "Actions" +) +inActions (MLText +uid 244,0 +va (VaSet +) +xt "23600,28500,38600,31500" +st "commandBus <= precharge; +addrSelPrecharge <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 245,0 +va (VaSet +) +xt "25000,26800,25000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 235,0 +ps "CenterOffsetStrategy" +text (MLText +uid 236,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt 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"43900,29900,44100,30100" +) +autoResize 1 +tline (Line +uid 295,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,29300,48850,29300" +pts [ +"39150,29300" +"48850,29300" +] +) +bline (Line +uid 296,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,28650,48850,28650" +pts [ +"39150,28650" +"48850,28650" +] +) +ttri (Triangle +uid 297,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,28925,39900,29275" +) +btri (Triangle +uid 298,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,26625,39900,26975" +) +entryActions (MLText +uid 299,0 +va (VaSet +) +xt "39150,29100,39150,29100" +tm "Actions" +) +inActions (MLText +uid 300,0 +va (VaSet +) +xt "39150,29500,48850,30500" +tm "Actions" +) +exitActions (MLText +uid 301,0 +va (VaSet +) +xt "40000,26800,40000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 291,0 +ps "CenterOffsetStrategy" +text (MLText +uid 292,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "40400,29000,45900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*21 (State +uid 334,0 +shape (Circle +uid 335,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "54000,24000,62000,32000" +radius 4000 +) +name (Text +uid 336,0 +va (VaSet +font "courier,10,1" +) +xt "55050,27400,60950,28600" +st "initialize3" +ju 0 +blo "58000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 337,0 +ps "CenterOffsetStrategy" +text (Text +uid 338,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "58100,28300,61700,29500" +st "wait 2" +blo "58100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 339,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "58000,29000,58000,29000" +blo "58000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 342,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 343,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "56200,28900,67800,31100" +) +autoResize 1 +tline (Line +uid 344,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56300,28800,67700,28800" +pts [ +"56300,28800" +"67700,28800" +] +) +bline (Line +uid 345,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56300,28900,67700,28900" +pts [ +"56300,28900" +"67700,28900" +] +) +ttri (Triangle +uid 346,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55850,28425,56200,28775" +) +btri (Triangle +uid 347,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55850,26625,56200,26975" +) +entryActions (MLText +uid 348,0 +va (VaSet +) +xt "56300,28600,56300,28600" +tm "Actions" +) +inActions (MLText +uid 349,0 +va (VaSet +) +xt "56300,29000,72500,31000" +st "commandBus <= autoRefresh; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 350,0 +va (VaSet +) +xt "58000,26800,58000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 340,0 +ps "CenterOffsetStrategy" +text (MLText +uid 341,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "56400,29000,61900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*22 (State +uid 361,0 +shape (Circle +uid 362,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "70000,24000,78000,32000" +radius 4000 +) +name (Text +uid 363,0 +va (VaSet +font "courier,10,1" +) +xt "71050,27400,76950,28600" +st "initialize4" +ju 0 +blo "74000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 364,0 +ps "CenterOffsetStrategy" +text (Text +uid 365,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "74100,28300,77700,29500" +st "wait 2" +blo "74100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 366,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "74000,29000,74000,29000" +blo "74000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 369,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 370,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "77900,29900,78100,30100" +) +autoResize 1 +tline (Line +uid 371,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,28800,84300,28800" +pts [ +"71700,28800" +"84300,28800" +] +) +bline (Line +uid 372,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,28900,84300,28900" +pts [ +"71700,28900" +"84300,28900" +] +) +ttri (Triangle +uid 373,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,28425,73900,28775" +) +btri (Triangle +uid 374,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,26625,73900,26975" +) +entryActions (MLText +uid 375,0 +va (VaSet +) +xt "71700,28600,71700,28600" +tm "Actions" +) +inActions (MLText +uid 376,0 +va (VaSet +) +xt "71700,29000,84300,31000" +tm "Actions" +) +exitActions (MLText +uid 377,0 +va (VaSet +) +xt "74000,26800,74000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 367,0 +ps "CenterOffsetStrategy" +text (MLText +uid 368,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "72400,29000,77900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*23 (State +uid 378,0 +shape (Circle +uid 379,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "86000,24000,94000,32000" +radius 4000 +) +name (Text +uid 380,0 +va (VaSet +font "courier,10,1" +) +xt "87050,27400,92950,28600" +st "initialize5" +ju 0 +blo "90000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 381,0 +ps "CenterOffsetStrategy" +text (Text +uid 382,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "90100,28300,93700,29500" +st "wait 2" +blo "90100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 383,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "90000,29000,90000,29000" +blo "90000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 386,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 387,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "88200,28900,99800,31100" +) +autoResize 1 +tline (Line +uid 388,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "88300,28800,99700,28800" +pts [ +"88300,28800" +"99700,28800" +] +) +bline (Line +uid 389,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "88300,28900,99700,28900" +pts [ +"88300,28900" +"99700,28900" +] +) +ttri (Triangle +uid 390,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87850,28425,88200,28775" +) +btri (Triangle +uid 391,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87850,26625,88200,26975" +) +entryActions (MLText +uid 392,0 +va (VaSet +) +xt "88300,28600,88300,28600" +tm "Actions" +) +inActions (MLText +uid 393,0 +va (VaSet +) +xt "88300,29000,104500,31000" +st "commandBus <= autoRefresh; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 394,0 +va (VaSet +) +xt "90000,26800,90000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 384,0 +ps "CenterOffsetStrategy" +text (MLText +uid 385,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "88400,29000,93900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*24 (State +uid 415,0 +shape (Circle +uid 416,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "102000,24000,110000,32000" +radius 4000 +) +name (Text +uid 417,0 +va (VaSet +font "courier,10,1" +) +xt "103050,27400,108950,28600" +st "initialize6" +ju 0 +blo "106000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 418,0 +ps "CenterOffsetStrategy" +text (Text +uid 419,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "106100,28300,109700,29500" +st "wait 2" +blo "106100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 420,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "106000,29000,106000,29000" +blo "106000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 423,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 424,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "109900,29900,110100,30100" +) +autoResize 1 +tline (Line +uid 425,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,28800,116300,28800" +pts [ +"103700,28800" +"116300,28800" +] +) +bline (Line +uid 426,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,28900,116300,28900" +pts [ +"103700,28900" +"116300,28900" +] +) +ttri (Triangle +uid 427,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,28425,105900,28775" +) +btri (Triangle +uid 428,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,26625,105900,26975" +) +entryActions (MLText +uid 429,0 +va (VaSet +) +xt "103700,28600,103700,28600" +tm "Actions" +) +inActions (MLText +uid 430,0 +va (VaSet +) +xt "103700,29000,116300,31000" +tm "Actions" +) +exitActions (MLText +uid 431,0 +va (VaSet +) +xt "106000,26800,106000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 421,0 +ps "CenterOffsetStrategy" +text (MLText +uid 422,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "104400,29000,109900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*25 (State +uid 502,0 +shape (Circle +uid 503,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "118000,24000,126000,32000" +radius 4000 +) +name (Text +uid 504,0 +va (VaSet +font "courier,10,1" +) +xt "119050,27400,124950,28600" +st "initialize7" +ju 0 +blo "122000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 505,0 +ps "CenterOffsetStrategy" +text (Text +uid 506,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "122100,28300,125700,29500" +st "wait 2" +blo "122100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 507,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "122000,29000,122000,29000" +blo "122000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 510,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 511,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "119850,28400,132150,31600" +) +autoResize 1 +tline (Line +uid 512,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "119950,28300,132050,28300" +pts [ +"119950,28300" +"132050,28300" +] +) +bline (Line +uid 513,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "119950,29150,132050,29150" +pts [ +"119950,29150" +"132050,29150" +] +) +ttri (Triangle +uid 514,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "119500,27925,119850,28275" +) +btri (Triangle +uid 515,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "119500,26625,119850,26975" +) +entryActions (MLText +uid 516,0 +va (VaSet +) +xt "119950,28100,119950,28100" +tm "Actions" +) +inActions (MLText +uid 517,0 +va (VaSet +) +xt "119950,28500,136150,31500" +st "commandBus <= loadModeReg; +timerStart <= '1'; +addrSelModeReg <= '1';" +tm "Actions" +) +exitActions (MLText +uid 518,0 +va (VaSet +) +xt "122000,26800,122000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 508,0 +ps "CenterOffsetStrategy" +text (MLText +uid 509,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "120400,29000,125900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*26 (State +uid 531,0 +shape (Circle +uid 532,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "134000,24000,142000,32000" +radius 4000 +) +name (Text +uid 533,0 +va (VaSet +font "courier,10,1" +) +xt "135050,27400,140950,28600" +st "initialize8" +ju 0 +blo "138000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 534,0 +ps "CenterOffsetStrategy" +text (Text +uid 535,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "138100,28300,141700,29500" +st "wait 2" +blo "138100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 536,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "138000,29000,138000,29000" +blo "138000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 539,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 540,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "141900,29900,142100,30100" +) +autoResize 1 +tline (Line +uid 541,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "135700,28800,148300,28800" +pts [ +"135700,28800" +"148300,28800" +] +) +bline (Line +uid 542,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "135700,28900,148300,28900" +pts [ +"135700,28900" +"148300,28900" +] +) +ttri (Triangle +uid 543,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "137550,28425,137900,28775" +) +btri (Triangle +uid 544,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "137550,26625,137900,26975" +) +entryActions (MLText +uid 545,0 +va (VaSet +) +xt "135700,28600,135700,28600" +tm "Actions" +) +inActions (MLText +uid 546,0 +va (VaSet +) +xt "135700,29000,148300,31000" +tm "Actions" +) +exitActions (MLText +uid 547,0 +va (VaSet +) +xt "138000,26800,138000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 537,0 +ps "CenterOffsetStrategy" +text (MLText +uid 538,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "136400,29000,141900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*27 (State +uid 558,0 +shape (Circle +uid 559,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "6000,40000,14000,48000" +radius 4000 +) +name (Text +uid 560,0 +va (VaSet +font "courier,10,1" +) +xt "8800,43400,11200,44600" +st "idle" +ju 0 +blo "10000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 561,0 +ps "CenterOffsetStrategy" +text (Text +uid 562,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "10100,44300,13700,45500" +st "wait 2" +blo "10100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 563,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "10000,45000,10000,45000" +blo "10000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 566,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 567,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "11900,45900,12100,46100" +) +autoResize 1 +tline (Line +uid 568,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "8000,45300,16000,45300" +pts [ +"8000,45300" +"16000,45300" +] +) +bline (Line +uid 569,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "8000,44650,16000,44650" +pts [ +"8000,44650" +"16000,44650" +] +) +ttri (Triangle +uid 570,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "7550,44925,7900,45275" +) +btri (Triangle +uid 571,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "7550,42625,7900,42975" +) +entryActions (MLText +uid 572,0 +va (VaSet +) +xt "8000,45100,8000,45100" +tm "Actions" +) +inActions (MLText +uid 573,0 +va (VaSet +) +xt "8000,45500,16000,46500" +tm "Actions" +) +exitActions (MLText +uid 574,0 +va (VaSet +) +xt "8000,42800,8000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 564,0 +ps "CenterOffsetStrategy" +text (MLText +uid 565,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "8400,45000,13900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*28 (Junction +uid 575,0 +shape (Diamond +uid 576,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "8350,34350,11650,37650" +) +symbol (Text +uid 577,0 +va (VaSet +font "courier,10,1" +) +xt "9350,35400,10650,36600" +st "&" +ju 0 +blo "10000,36400" +) +name (TextAssociate +uid 578,0 +ps "CenterOffsetStrategy" +text (Text +uid 579,0 +va (VaSet +font "courier,8,1" +) +xt "11500,36500,11500,36500" +blo "11500,36500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 580,0 +ps "CenterOffsetStrategy" +text (MLText +uid 581,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "7650,37500,13150,38400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*29 (Junction +uid 592,0 +shape (Diamond +uid 593,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "136350,34350,139650,37650" +) +symbol (Text +uid 594,0 +va (VaSet +font "courier,10,1" +) +xt "137350,35400,138650,36600" +st "&" +ju 0 +blo "138000,36400" +) +name (TextAssociate +uid 595,0 +ps "CenterOffsetStrategy" +text (Text +uid 596,0 +va (VaSet +font "courier,8,1" +) +xt "139500,36500,139500,36500" +blo "139500,36500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 597,0 +ps "CenterOffsetStrategy" +text (MLText +uid 598,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "135650,37500,141150,38400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*30 (State +uid 629,0 +shape (Circle +uid 630,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "22000,40000,30000,48000" +radius 4000 +) +name (Text +uid 631,0 +va (VaSet +font "courier,10,1" +) +xt "23650,43400,28350,44600" +st "refresh1" +ju 0 +blo "26000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 632,0 +ps "CenterOffsetStrategy" +text (Text +uid 633,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "26100,44300,29700,45500" +st "wait 2" +blo "26100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 634,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "26000,45000,26000,45000" +blo "26000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 637,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 638,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "23500,45400,34500,48600" +) +autoResize 1 +tline (Line +uid 639,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23600,45300,34400,45300" +pts [ +"23600,45300" +"34400,45300" +] +) +bline (Line +uid 640,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23600,46150,34400,46150" +pts [ +"23600,46150" +"34400,46150" +] +) +ttri (Triangle +uid 641,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23150,44925,23500,45275" +) +btri (Triangle +uid 642,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23150,43625,23500,43975" +) +entryActions (MLText +uid 643,0 +va (VaSet +) +xt "23600,45100,23600,45100" +tm "Actions" +) +inActions (MLText +uid 644,0 +va (VaSet +) +xt "23600,45500,38600,48500" +st "commandBus <= precharge; +addrSelPrecharge <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 645,0 +va (VaSet +) +xt "25000,43800,25000,43800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 635,0 +ps "CenterOffsetStrategy" +text (MLText +uid 636,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "24400,45000,29900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*31 (State +uid 656,0 +shape (Circle +uid 657,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "38000,40000,46000,48000" +radius 4000 +) +name (Text +uid 658,0 +va (VaSet +font "courier,10,1" +) +xt "39650,43400,44350,44600" +st "refresh2" +ju 0 +blo "42000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 659,0 +ps "CenterOffsetStrategy" +text (Text +uid 660,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "42100,44300,45700,45500" +st "wait 2" +blo "42100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 661,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,45000,42000,45000" +blo "42000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 664,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 665,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "43900,45900,44100,46100" +) +autoResize 1 +tline (Line +uid 666,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,45300,48850,45300" +pts [ +"39150,45300" +"48850,45300" +] +) +bline (Line +uid 667,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,44650,48850,44650" +pts [ +"39150,44650" +"48850,44650" +] +) +ttri (Triangle +uid 668,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,44925,39900,45275" +) +btri (Triangle +uid 669,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,42625,39900,42975" +) +entryActions (MLText +uid 670,0 +va (VaSet +) +xt "39150,45100,39150,45100" +tm "Actions" +) +inActions (MLText +uid 671,0 +va (VaSet +) +xt "39150,45500,48850,46500" +tm "Actions" +) +exitActions (MLText +uid 672,0 +va (VaSet +) +xt "40000,42800,40000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 662,0 +ps "CenterOffsetStrategy" +text (MLText +uid 663,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "40400,45000,45900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*32 (State +uid 673,0 +shape (Circle +uid 674,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "54000,40000,62000,48000" +radius 4000 +) +name (Text +uid 675,0 +va (VaSet +font "courier,10,1" +) +xt "55650,43400,60350,44600" +st "refresh3" +ju 0 +blo "58000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 676,0 +ps "CenterOffsetStrategy" +text (Text +uid 677,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "58100,44300,61700,45500" +st "wait 2" +blo "58100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 678,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "58000,45000,58000,45000" +blo "58000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 681,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 682,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "56200,44900,67800,47100" +) +autoResize 1 +tline (Line +uid 683,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56300,44800,67700,44800" +pts [ +"56300,44800" +"67700,44800" +] +) +bline (Line +uid 684,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56300,44900,67700,44900" +pts [ +"56300,44900" +"67700,44900" +] +) +ttri (Triangle +uid 685,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55850,44425,56200,44775" +) +btri (Triangle +uid 686,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55850,42625,56200,42975" +) +entryActions (MLText +uid 687,0 +va (VaSet +) +xt "56300,44600,56300,44600" +tm "Actions" +) +inActions (MLText +uid 688,0 +va (VaSet +) +xt "56300,45000,72500,47000" +st "commandBus <= autoRefresh; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 689,0 +va (VaSet +) +xt "58000,42800,58000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 679,0 +ps "CenterOffsetStrategy" +text (MLText +uid 680,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "56400,45000,61900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*33 (State +uid 690,0 +shape (Circle +uid 691,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "70000,40000,78000,48000" +radius 4000 +) +name (Text +uid 692,0 +va (VaSet +font "courier,10,1" +) +xt "71650,43400,76350,44600" +st "refresh4" +ju 0 +blo "74000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 693,0 +ps "CenterOffsetStrategy" +text (Text +uid 694,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "74100,44300,77700,45500" +st "wait 2" +blo "74100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 695,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "74000,45000,74000,45000" +blo "74000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 698,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 699,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "77900,45900,78100,46100" +) +autoResize 1 +tline (Line +uid 700,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,44800,84300,44800" +pts [ +"71700,44800" +"84300,44800" +] +) +bline (Line +uid 701,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,44900,84300,44900" +pts [ +"71700,44900" +"84300,44900" +] +) +ttri (Triangle +uid 702,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,44425,73900,44775" +) +btri (Triangle +uid 703,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,42625,73900,42975" +) +entryActions (MLText +uid 704,0 +va (VaSet +) +xt "71700,44600,71700,44600" +tm "Actions" +) +inActions (MLText +uid 705,0 +va (VaSet +) +xt "71700,45000,84300,47000" +tm "Actions" +) +exitActions (MLText +uid 706,0 +va (VaSet +) +xt "74000,42800,74000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 696,0 +ps "CenterOffsetStrategy" +text (MLText +uid 697,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "72400,45000,77900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*34 (State +uid 707,0 +shape (Circle +uid 708,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "86000,40000,94000,48000" +radius 4000 +) +name (Text +uid 709,0 +va (VaSet +font "courier,10,1" +) +xt "87650,43400,92350,44600" +st "refresh5" +ju 0 +blo "90000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 710,0 +ps "CenterOffsetStrategy" +text (Text +uid 711,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "90100,44300,93700,45500" +st "wait 2" +blo "90100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 712,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "90000,45000,90000,45000" +blo "90000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 715,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 716,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "88200,44900,99800,47100" +) +autoResize 1 +tline (Line +uid 717,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "88300,44800,99700,44800" +pts [ +"88300,44800" +"99700,44800" +] +) +bline (Line +uid 718,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "88300,44900,99700,44900" +pts [ +"88300,44900" +"99700,44900" +] +) +ttri (Triangle +uid 719,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87850,44425,88200,44775" +) +btri (Triangle +uid 720,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87850,42625,88200,42975" +) +entryActions (MLText +uid 721,0 +va (VaSet +) +xt "88300,44600,88300,44600" +tm "Actions" +) +inActions (MLText +uid 722,0 +va (VaSet +) +xt "88300,45000,104500,47000" +st "commandBus <= autoRefresh; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 723,0 +va (VaSet +) +xt "90000,42800,90000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 713,0 +ps "CenterOffsetStrategy" +text (MLText +uid 714,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "88400,45000,93900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*35 (State +uid 724,0 +shape (Circle +uid 725,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "102000,40000,110000,48000" +radius 4000 +) +name (Text +uid 726,0 +va (VaSet +font "courier,10,1" +) +xt "102750,43400,109250,44600" +st "initialize13" +ju 0 +blo "106000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 727,0 +ps "CenterOffsetStrategy" +text (Text +uid 728,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "106100,44300,109700,45500" +st "wait 2" +blo "106100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 729,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "106000,45000,106000,45000" +blo "106000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 732,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 733,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "109900,45900,110100,46100" +) +autoResize 1 +tline (Line +uid 734,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,44800,116300,44800" +pts [ +"103700,44800" +"116300,44800" +] +) +bline (Line +uid 735,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,44900,116300,44900" +pts [ +"103700,44900" +"116300,44900" +] +) +ttri (Triangle +uid 736,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,44425,105900,44775" +) +btri (Triangle +uid 737,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,42625,105900,42975" +) +entryActions (MLText +uid 738,0 +va (VaSet +) +xt "103700,44600,103700,44600" +tm "Actions" +) +inActions (MLText +uid 739,0 +va (VaSet +) +xt "103700,45000,116300,47000" +tm "Actions" +) +exitActions (MLText +uid 740,0 +va (VaSet +) +xt "106000,42800,106000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 730,0 +ps "CenterOffsetStrategy" +text (MLText +uid 731,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "104400,45000,109900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*36 (Junction +uid 791,0 +shape (Diamond +uid 792,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "112350,34350,115650,37650" +) +symbol (Text +uid 793,0 +va (VaSet +font "courier,10,1" +) +xt "113350,35400,114650,36600" +st "&" +ju 0 +blo "114000,36400" +) +name (TextAssociate +uid 794,0 +ps "CenterOffsetStrategy" +text (Text +uid 795,0 +va (VaSet +font "courier,8,1" +) +xt "115500,36500,115500,36500" +blo "115500,36500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 796,0 +ps "CenterOffsetStrategy" +text (MLText +uid 797,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "111650,37500,117150,38400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*37 (Junction +uid 798,0 +shape (Diamond +uid 799,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "112350,42350,115650,45650" +) +symbol (Text +uid 800,0 +va (VaSet +font "courier,10,1" +) +xt "113350,43400,114650,44600" +st "&" +ju 0 +blo "114000,44400" +) +name (TextAssociate +uid 801,0 +ps "CenterOffsetStrategy" +text (Text +uid 802,0 +va (VaSet +font "courier,8,1" +) +xt "115500,44500,115500,44500" +blo "115500,44500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 803,0 +ps "CenterOffsetStrategy" +text (MLText +uid 804,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "111650,45500,117150,46400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*38 (State +uid 870,0 +shape (Circle +uid 871,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "22000,56000,30000,64000" +radius 4000 +) +name (Text +uid 872,0 +va (VaSet +font "courier,10,1" +) +xt "24150,59400,27850,60600" +st "write1" +ju 0 +blo "26000,60400" +tm "ONodeName" +) +wait (TextAssociate +uid 873,0 +ps "CenterOffsetStrategy" +text (Text +uid 874,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "26100,60300,29700,61500" +st "wait 2" +blo "26100,61300" +tm "SmWaitText" +) +) +encoding (Text +uid 875,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "26000,61000,26000,61000" +blo "26000,61000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 878,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 879,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "24300,60900,33700,65100" +) +autoResize 1 +tline (Line +uid 880,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24400,60800,33600,60800" +pts [ +"24400,60800" +"33600,60800" +] +) +bline (Line +uid 881,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24400,62400,33600,62400" +pts [ +"24400,62400" +"33600,62400" +] +) +ttri (Triangle +uid 882,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23950,60425,24300,60775" +) +btri (Triangle +uid 883,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23950,59625,24300,59975" +) +entryActions (MLText +uid 884,0 +va (VaSet +) +xt "24400,60600,24400,60600" +tm "Actions" +) +inActions (MLText +uid 885,0 +va (VaSet +) +xt "24400,61000,37600,65000" +st "commandBus <= active; +writeAck <= '1'; +addrSelRow <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 886,0 +va (VaSet +) +xt "25000,59800,25000,59800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 876,0 +ps "CenterOffsetStrategy" +text (MLText +uid 877,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "24400,61000,29900,61900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*39 (State +uid 887,0 +shape (Circle +uid 888,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "38000,56000,46000,64000" +radius 4000 +) +name (Text +uid 889,0 +va (VaSet +font "courier,10,1" +) +xt "40150,59400,43850,60600" +st "write2" +ju 0 +blo "42000,60400" +tm "ONodeName" +) +wait (TextAssociate +uid 890,0 +ps "CenterOffsetStrategy" +text (Text +uid 891,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "42100,60300,45700,61500" +st "wait 2" +blo "42100,61300" +tm "SmWaitText" +) +) +encoding (Text +uid 892,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,61000,42000,61000" +blo "42000,61000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 895,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 896,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "43900,61900,44100,62100" +) +autoResize 1 +tline (Line +uid 897,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,61300,48850,61300" +pts [ +"39150,61300" +"48850,61300" +] +) +bline (Line +uid 898,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,60650,48850,60650" +pts [ +"39150,60650" +"48850,60650" +] +) +ttri (Triangle +uid 899,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,60925,39900,61275" +) +btri (Triangle +uid 900,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,58625,39900,58975" +) +entryActions (MLText +uid 901,0 +va (VaSet +) +xt "39150,61100,39150,61100" +tm "Actions" +) +inActions (MLText +uid 902,0 +va (VaSet +) +xt "39150,61500,48850,62500" +tm "Actions" +) +exitActions (MLText +uid 903,0 +va (VaSet +) +xt "40000,58800,40000,58800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 893,0 +ps "CenterOffsetStrategy" +text (MLText +uid 894,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "40400,61000,45900,61900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*40 (State +uid 904,0 +shape (Circle +uid 905,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "54000,56000,62000,64000" +radius 4000 +) +name (Text +uid 906,0 +va (VaSet +font "courier,10,1" +) +xt "56150,59400,59850,60600" +st "write3" +ju 0 +blo "58000,60400" +tm "ONodeName" +) +wait (TextAssociate +uid 907,0 +ps "CenterOffsetStrategy" +text (Text +uid 908,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "58100,60300,61700,61500" +st "wait 2" +blo "58100,61300" +tm "SmWaitText" +) +) +encoding (Text +uid 909,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "58000,61000,58000,61000" +blo "58000,61000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 912,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 913,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "56450,60400,65550,63600" +) +autoResize 1 +tline (Line +uid 914,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56550,60300,65450,60300" +pts [ +"56550,60300" +"65450,60300" +] +) +bline (Line +uid 915,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56550,61150,65450,61150" +pts [ +"56550,61150" +"65450,61150" +] +) +ttri (Triangle +uid 916,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56100,59925,56450,60275" +) +btri (Triangle +uid 917,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56100,58625,56450,58975" +) +entryActions (MLText +uid 918,0 +va (VaSet +) +xt "56550,60100,56550,60100" +tm "Actions" +) +inActions (MLText +uid 919,0 +va (VaSet +) +xt "56550,60500,69150,63500" +st "commandBus <= write; +addrSelCol <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 920,0 +va (VaSet +) +xt "57000,58800,57000,58800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 910,0 +ps "CenterOffsetStrategy" +text (MLText +uid 911,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "56400,61000,61900,61900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*41 (State +uid 921,0 +shape (Circle +uid 922,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "70000,56000,78000,64000" +radius 4000 +) +name (Text +uid 923,0 +va (VaSet +font "courier,10,1" +) +xt "72150,59400,75850,60600" +st "write4" +ju 0 +blo "74000,60400" +tm "ONodeName" +) +wait (TextAssociate +uid 924,0 +ps "CenterOffsetStrategy" +text (Text +uid 925,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "74100,60300,77700,61500" +st "wait 2" +blo "74100,61300" +tm "SmWaitText" +) +) +encoding (Text +uid 926,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "74000,61000,74000,61000" +blo "74000,61000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 929,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 930,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "77900,61900,78100,62100" +) +autoResize 1 +tline (Line +uid 931,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,60800,84300,60800" +pts [ +"71700,60800" +"84300,60800" +] +) +bline (Line +uid 932,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,60900,84300,60900" +pts [ +"71700,60900" +"84300,60900" +] +) +ttri (Triangle +uid 933,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,60425,73900,60775" +) +btri (Triangle +uid 934,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,58625,73900,58975" +) +entryActions (MLText +uid 935,0 +va (VaSet +) +xt "71700,60600,71700,60600" +tm "Actions" +) +inActions (MLText +uid 936,0 +va (VaSet +) +xt "71700,61000,84300,63000" +tm "Actions" +) +exitActions (MLText +uid 937,0 +va (VaSet +) +xt "74000,58800,74000,58800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 927,0 +ps "CenterOffsetStrategy" +text (MLText +uid 928,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "72400,61000,77900,61900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*42 (Junction +uid 978,0 +shape (Diamond +uid 979,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "8350,58350,11650,61650" +) +symbol (Text +uid 980,0 +va (VaSet +font "courier,10,1" +) +xt "9350,59400,10650,60600" +st "&" +ju 0 +blo "10000,60400" +) +name (TextAssociate +uid 981,0 +ps "CenterOffsetStrategy" +text (Text +uid 982,0 +va (VaSet +font "courier,8,1" +) +xt "11500,60500,11500,60500" +blo "11500,60500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 983,0 +ps "CenterOffsetStrategy" +text (MLText +uid 984,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "7650,61500,13150,62400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*43 (Junction +uid 999,0 +shape (Diamond +uid 1000,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "112350,58350,115650,61650" +) +symbol (Text +uid 1001,0 +va (VaSet +font "courier,10,1" +) +xt "113350,59400,114650,60600" +st "&" +ju 0 +blo "114000,60400" +) +name (TextAssociate +uid 1002,0 +ps "CenterOffsetStrategy" +text (Text +uid 1003,0 +va (VaSet +font "courier,8,1" +) +xt "115500,60500,115500,60500" +blo "115500,60500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 1004,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1005,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "111650,61500,117150,62400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*44 (State +uid 1026,0 +shape (Circle +uid 1027,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "22000,72000,30000,80000" +radius 4000 +) +name (Text +uid 1028,0 +va (VaSet +font "courier,10,1" +) +xt "24300,75400,27700,76600" +st "read1" +ju 0 +blo "26000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1029,0 +ps "CenterOffsetStrategy" +text (Text +uid 1030,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "26100,76300,29700,77500" +st "wait 2" +blo "26100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1031,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "26000,77000,26000,77000" +blo "26000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1034,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1035,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "24300,76900,33700,81100" +) +autoResize 1 +tline (Line +uid 1036,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24400,76800,33600,76800" +pts [ +"24400,76800" +"33600,76800" +] +) +bline (Line +uid 1037,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24400,78400,33600,78400" +pts [ +"24400,78400" +"33600,78400" +] +) +ttri (Triangle +uid 1038,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23950,76425,24300,76775" +) +btri (Triangle +uid 1039,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23950,75625,24300,75975" +) +entryActions (MLText +uid 1040,0 +va (VaSet +) +xt "24400,76600,24400,76600" +tm "Actions" +) +inActions (MLText +uid 1041,0 +va (VaSet +) +xt "24400,77000,37600,81000" +st "commandBus <= active; +readAck <= '1'; +addrSelRow <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 1042,0 +va (VaSet +) +xt "25000,75800,25000,75800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1032,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1033,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "24400,77000,29900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*45 (State +uid 1043,0 +shape (Circle +uid 1044,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "38000,72000,46000,80000" +radius 4000 +) +name (Text +uid 1045,0 +va (VaSet +font "courier,10,1" +) +xt "40300,75400,43700,76600" +st "read2" +ju 0 +blo "42000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1046,0 +ps "CenterOffsetStrategy" +text (Text +uid 1047,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "42100,76300,45700,77500" +st "wait 2" +blo "42100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1048,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,77000,42000,77000" +blo "42000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1051,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1052,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "43900,77900,44100,78100" +) +autoResize 1 +tline (Line +uid 1053,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,77300,48850,77300" +pts [ +"39150,77300" +"48850,77300" +] +) +bline (Line +uid 1054,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,76650,48850,76650" +pts [ +"39150,76650" +"48850,76650" +] +) +ttri (Triangle +uid 1055,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,76925,39900,77275" +) +btri (Triangle +uid 1056,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,74625,39900,74975" +) +entryActions (MLText +uid 1057,0 +va (VaSet +) +xt "39150,77100,39150,77100" +tm "Actions" +) +inActions (MLText +uid 1058,0 +va (VaSet +) +xt "39150,77500,48850,78500" +tm "Actions" +) +exitActions (MLText +uid 1059,0 +va (VaSet +) +xt "40000,74800,40000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1049,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1050,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "40400,77000,45900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*46 (State +uid 1060,0 +shape (Circle +uid 1061,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "54000,72000,62000,80000" +radius 4000 +) +name (Text +uid 1062,0 +va (VaSet +font "courier,10,1" +) +xt "56300,75400,59700,76600" +st "read3" +ju 0 +blo "58000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1063,0 +ps "CenterOffsetStrategy" +text (Text +uid 1064,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "58100,76300,61700,77500" +st "wait 2" +blo "58100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1065,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "58000,77000,58000,77000" +blo "58000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1068,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1069,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "56700,76400,65300,79600" +) +autoResize 1 +tline (Line +uid 1070,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56800,76300,65200,76300" +pts [ +"56800,76300" +"65200,76300" +] +) +bline (Line +uid 1071,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56800,77150,65200,77150" +pts [ +"56800,77150" +"65200,77150" +] +) +ttri (Triangle +uid 1072,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56350,75925,56700,76275" +) +btri (Triangle +uid 1073,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56350,74625,56700,74975" +) +entryActions (MLText +uid 1074,0 +va (VaSet +) +xt "56800,76100,56800,76100" +tm "Actions" +) +inActions (MLText +uid 1075,0 +va (VaSet +) +xt "56800,76500,68800,79500" +st "commandBus <= read; +addrSelCol <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 1076,0 +va (VaSet +) +xt "57000,74800,57000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1066,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1067,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "56400,77000,61900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*47 (State +uid 1077,0 +shape (Circle +uid 1078,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "70000,72000,78000,80000" +radius 4000 +) +name (Text +uid 1079,0 +va (VaSet +font "courier,10,1" +) +xt "72300,75400,75700,76600" +st "read4" +ju 0 +blo "74000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1080,0 +ps "CenterOffsetStrategy" +text (Text +uid 1081,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "74100,76300,77700,77500" +st "wait 2" +blo "74100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1082,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "74000,77000,74000,77000" +blo "74000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1085,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1086,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "77900,77900,78100,78100" +) +autoResize 1 +tline (Line +uid 1087,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,76800,84300,76800" +pts [ +"71700,76800" +"84300,76800" +] +) +bline (Line +uid 1088,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,76900,84300,76900" +pts [ +"71700,76900" +"84300,76900" +] +) +ttri (Triangle +uid 1089,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,76425,73900,76775" +) +btri (Triangle +uid 1090,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,74625,73900,74975" +) +entryActions (MLText +uid 1091,0 +va (VaSet +) +xt "71700,76600,71700,76600" +tm "Actions" +) +inActions (MLText +uid 1092,0 +va (VaSet +) +xt "71700,77000,84300,79000" +tm "Actions" +) +exitActions (MLText +uid 1093,0 +va (VaSet +) +xt "74000,74800,74000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1083,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1084,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "72400,77000,77900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*48 (Junction +uid 1094,0 +shape (Diamond +uid 1095,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "112350,74350,115650,77650" +) +symbol (Text +uid 1096,0 +va (VaSet +font "courier,10,1" +) +xt "113350,75400,114650,76600" +st "&" +ju 0 +blo "114000,76400" +) +name (TextAssociate +uid 1097,0 +ps "CenterOffsetStrategy" +text (Text +uid 1098,0 +va (VaSet +font "courier,8,1" +) +xt "115500,76500,115500,76500" +blo "115500,76500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 1099,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1100,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "111650,77500,117150,78400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*49 (Junction +uid 1151,0 +shape (Diamond +uid 1152,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "8350,74350,11650,77650" +) +symbol (Text +uid 1153,0 +va (VaSet +font "courier,10,1" +) +xt "9350,75400,10650,76600" +st "&" +ju 0 +blo "10000,76400" +) +name (TextAssociate +uid 1154,0 +ps "CenterOffsetStrategy" +text (Text +uid 1155,0 +va (VaSet +font "courier,8,1" +) +xt "11500,76500,11500,76500" +blo "11500,76500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 1156,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1157,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "7650,77500,13150,78400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*50 (State +uid 1217,0 +shape (Circle +uid 1218,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "86000,72000,94000,80000" +radius 4000 +) +name (Text +uid 1219,0 +va (VaSet +font "courier,10,1" +) +xt "88300,75400,91700,76600" +st "read5" +ju 0 +blo "90000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1220,0 +ps "CenterOffsetStrategy" +text (Text +uid 1221,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "90100,76300,93700,77500" +st "wait 2" +blo "90100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1222,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "90000,77000,90000,77000" +blo "90000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1225,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1226,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "87800,76900,96200,79100" +) +autoResize 1 +tline (Line +uid 1227,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87900,76800,96100,76800" +pts [ +"87900,76800" +"96100,76800" +] +) +bline (Line +uid 1228,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87900,76900,96100,76900" +pts [ +"87900,76900" +"96100,76900" +] +) +ttri (Triangle +uid 1229,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87450,76425,87800,76775" +) +btri (Triangle +uid 1230,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87450,74625,87800,74975" +) +entryActions (MLText +uid 1231,0 +va (VaSet +) +xt "87900,76600,87900,76600" +tm "Actions" +) +inActions (MLText +uid 1232,0 +va (VaSet +) +xt "87900,77000,100500,79000" +st "sampleData <= '1'; +ramDataValid <= '1';" +tm "Actions" +) +exitActions (MLText +uid 1233,0 +va (VaSet +) +xt "88000,74800,88000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1223,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1224,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "88400,77000,93900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*51 (State +uid 1234,0 +shape (Circle +uid 1235,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "102000,72000,110000,80000" +radius 4000 +) +name (Text +uid 1236,0 +va (VaSet +font "courier,10,1" +) +xt "104300,75400,107700,76600" +st "read6" +ju 0 +blo "106000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1237,0 +ps "CenterOffsetStrategy" +text (Text +uid 1238,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "106100,76300,109700,77500" +st "wait 2" +blo "106100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1239,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "106000,77000,106000,77000" +blo "106000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1242,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1243,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "109900,77900,110100,78100" +) +autoResize 1 +tline (Line +uid 1244,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,76800,116300,76800" +pts [ +"103700,76800" +"116300,76800" +] +) +bline (Line +uid 1245,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,76900,116300,76900" +pts [ +"103700,76900" +"116300,76900" +] +) +ttri (Triangle +uid 1246,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,76425,105900,76775" +) +btri (Triangle +uid 1247,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,74625,105900,74975" +) +entryActions (MLText +uid 1248,0 +va (VaSet +) +xt "103700,76600,103700,76600" +tm "Actions" +) +inActions (MLText +uid 1249,0 +va (VaSet +) +xt "103700,77000,116300,79000" +tm "Actions" +) +exitActions (MLText +uid 1250,0 +va (VaSet +) +xt "106000,74800,106000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1240,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1241,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "104400,77000,109900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*52 (Transition +uid 100,0 +shape (Spline +uid 101,0 +va (VaSet +vasetType 3 +) +xt "5500,15000,13000,15000" +pts [ +"5500,15000" +"13000,15000" +] +) +start &4 +end &5 +ss 0 +es 0 +cond "reset = '1'" +tb (TransitionBlock +uid 102,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 103,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "7250,14000,15450,16000" +) +autoResize 1 +lineShape (Line +uid 104,0 +va (VaSet +vasetType 3 +) +xt "7750,15400,14950,15400" +pts [ +"7750,15400" +"14950,15400" +] +) +condition (MLText +uid 105,0 +va (VaSet +) +xt "7750,14000,14950,15000" +st "reset = '1'" +tm "Condition" +) +actions (MLText +uid 106,0 +va (VaSet +isHidden 1 +) +xt "7150,15800,15550,16800" +st "< Automatic >" +tm "Actions" +) +) +tp (TransitionPriority +uid 107,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 108,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "5469,14219,7031,15781" +radius 781 +) +pr (Text +uid 109,0 +va (VaSet +isHidden 1 +) +xt "5850,14500,6650,15500" +st "1" +ju 0 +blo "6250,15300" +tm "TransitionPriority" +) +padding "100,100" +) +) +*53 (Transition +uid 110,0 +shape (Spline +uid 111,0 +va (VaSet +vasetType 3 +) +xt "5050,13000,13000,13000" +pts [ +"5050,13000" +"13000,13000" +] +) +start &6 +end &7 +ss 0 +es 0 +tb (TransitionBlock +uid 112,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 113,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "6825,12495,11225,13505" +) +autoResize 1 +lineShape (Line +uid 114,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "9025,13900,9025,13900" +pts [ +"9025,13900" +"9025,13900" +] +) +condition (MLText +uid 115,0 +va (VaSet +) +xt "7325,12500,10725,13500" +tm "Condition" +) +actions (MLText +uid 116,0 +va (VaSet +) +xt "9025,13900,9025,13900" +tm "Actions" +) +) +tp (TransitionPriority +uid 117,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 118,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "5064,12219,6626,13781" +radius 781 +) +pr (Text +uid 119,0 +va (VaSet +isHidden 1 +) +xt "5445,12500,6245,13500" +st "1" +ju 0 +blo "5845,13300" +tm "TransitionPriority" +) +padding "100,100" +) +) +*54 (Transition +uid 246,0 +shape (Spline +uid 247,0 +va (VaSet +vasetType 3 +) +xt "14000,27968,22000,27970" +pts [ +"14000,27970" +"22000,27968" +] +arrow 1 +) +start &2 +end &19 +cond "endOfRefreshCount = '1'" +tb (TransitionBlock +uid 248,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 249,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "11700,24550,22300,26550" +) +autoResize 1 +lineShape (Line +uid 250,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "12200,26450,21800,26450" +pts [ +"12200,26450" +"21800,26450" +] +) +condition (MLText +uid 251,0 +va (VaSet +) +xt "12200,25050,26600,26050" +st "endOfRefreshCount = '1'" +tm "Condition" +) +actions (MLText +uid 252,0 +va (VaSet +) +xt "12200,26450,21800,27450" +tm "Actions" +) +) +tp (TransitionPriority +uid 253,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 254,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "14019,27188,15581,28750" +radius 781 +) +pr (Text +uid 255,0 +va (VaSet +isHidden 1 +) +xt "14400,27469,15200,28469" +st "1" +ju 0 +blo "14800,28269" +tm "TransitionPriority" +) +padding "100,100" +) +) +*55 (Transition +uid 312,0 +shape (Spline +uid 313,0 +va (VaSet +vasetType 3 +) +xt "30000,28035,38000,28036" +pts [ +"30000,28035" +"38000,28036" +] +arrow 1 +) +start &19 +end &20 +tb (TransitionBlock +uid 314,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 315,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "33500,28031,37900,29041" +) +autoResize 1 +lineShape (Line +uid 316,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "35700,29436,35700,29436" +pts [ +"35700,29436" +"35700,29436" +] +) +condition (MLText +uid 317,0 +va (VaSet +) +xt "34000,28036,37400,29036" +tm "Condition" +) +actions (MLText +uid 318,0 +va (VaSet +) +xt "35700,29436,35700,29436" +tm "Actions" +) +) +tp (TransitionPriority +uid 319,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 320,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "30019,27254,31581,28816" +radius 781 +) +pr (Text +uid 321,0 +va (VaSet +isHidden 1 +) +xt "30400,27535,31200,28535" +st "1" +ju 0 +blo "30800,28335" +tm "TransitionPriority" +) +padding "100,100" +) +) +*56 (Transition +uid 351,0 +shape (Spline +uid 352,0 +va (VaSet +vasetType 3 +) +xt "46000,27955,54000,27955" +pts [ +"46000,27955" +"54000,27955" +] +arrow 1 +) +start &20 +end &21 +cond "unsigned(timerDone(1 to prechargeToRefreshPeriodNb)) = 0" +tb (TransitionBlock +uid 353,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 354,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "41950,25000,65350,27000" +) +autoResize 1 +lineShape (Line +uid 355,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "44150,26900,44150,26900" +pts [ +"44150,26900" +"44150,26900" +] +) +condition (MLText +uid 356,0 +va (VaSet +) +xt "42450,25500,76650,26500" +st "unsigned(timerDone(1 to prechargeToRefreshPeriodNb)) = 0" +tm "Condition" +) +actions (MLText +uid 357,0 +va (VaSet +) +xt "53650,26900,53650,26900" +tm "Actions" +) +) +tp (TransitionPriority +uid 358,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 359,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "46019,27174,47581,28736" +radius 781 +) +pr (Text +uid 360,0 +va (VaSet +isHidden 1 +) +xt "46400,27455,47200,28455" +st "1" +ju 0 +blo "46800,28255" +tm "TransitionPriority" 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(Spline +uid 939,0 +va (VaSet +vasetType 3 +) +xt "62000,60002,70000,60006" +pts [ +"62000,60006" +"70000,60002" +] +arrow 1 +) +start &40 +end &41 +es 0 +tb (TransitionBlock +uid 940,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 941,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "65500,59999,69900,61009" +) +autoResize 1 +lineShape (Line +uid 942,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "67700,61404,67700,61404" +pts [ +"67700,61404" +"67700,61404" +] +) +condition (MLText +uid 943,0 +va (VaSet +) +xt "66000,60004,69400,61004" +tm "Condition" +) +actions (MLText +uid 944,0 +va (VaSet +) +xt "67700,61404,67700,61404" +tm "Actions" +) +) +tp (TransitionPriority +uid 945,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 946,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "62019,59224,63581,60786" +radius 781 +) +pr (Text +uid 947,0 +va (VaSet +isHidden 1 +) +xt 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"15138,58747,15138,58747" +pts [ +"15138,58747" +"15138,58747" +] +) +condition (MLText +uid 973,0 +va (VaSet +) +xt "13438,57347,36838,58347" +st "(ramEn = '1') and (writeRequest = '1')" +tm "Condition" +) +actions (MLText +uid 974,0 +va (VaSet +) +xt "20488,58747,20488,58747" +tm "Actions" +) +) +tp (TransitionPriority +uid 975,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 976,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "11882,59194,13444,60756" +radius 781 +) +pr (Text +uid 977,0 +va (VaSet +) +xt "12263,59475,13063,60475" +st "1" +ju 0 +blo "12663,60275" +tm "TransitionPriority" +) +padding "100,100" +) +) +*78 (Transition +uid 985,0 +shape (Spline +uid 986,0 +va (VaSet +vasetType 3 +) +xt "10008,48000,10009,58358" +pts [ +"10009,48000" +"10008,58358" +] +arrow 1 +) +start &27 +end &42 +tb (TransitionBlock +uid 987,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 988,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" 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(Transition +uid 1016,0 +shape (Spline +uid 1017,0 +va (VaSet +vasetType 3 +) +xt "114010,45640,114015,58365" +pts [ +"114015,58365" +"114010,45640" +] +arrow 1 +) +start &43 +end &37 +tb (TransitionBlock +uid 1018,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1019,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "113512,51997,117912,53007" +) +autoResize 1 +lineShape (Line +uid 1020,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "115712,53402,115712,53402" +pts [ +"115712,53402" +"115712,53402" +] +) +condition (MLText +uid 1021,0 +va (VaSet +) +xt "114012,52002,117412,53002" +tm "Condition" +) +actions (MLText +uid 1022,0 +va (VaSet +) +xt "115712,53402,115712,53402" +tm "Actions" +) +) +tp (TransitionPriority +uid 1023,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 1024,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "113233,56312,114795,57874" +radius 781 +) +pr (Text +uid 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+) +localPreDecl *100 (SmLocalDecl +uid 1648,0 +stg "VerticalLayoutStrategy" +first (Text +uid 1649,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,0,13000,900" +st "Architecture Declarations" +blo "0,700" +) +second (MLText +uid 1650,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,900,0,900" +tm "LocalDeclTextMgr" +) +declType 1 +) +localDecl *101 (SmLocalDecl +uid 3,0 +stg "VerticalLayoutStrategy" +first (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "40000,-1400,53000,-500" +st "Architecture Declarations" +blo "40000,-700" +) +second (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "40000,-400,79500,18500" +st "-- 20120621 -- zas -- added to generics +--constant prechargeToRefreshPeriodNb: positive := 2; -- 66MHz * 20 ns = 1.32 +--constant refreshDelayPeriodNb: positive := 5; -- 66MHz * 66ns = 4.356 +--constant loadModeToActivePeriodNb: positive := 1; -- 1 CK +--constant activeToWritePeriodNb: positive := 2; -- 66MHz * 20ns = 1.32 +--constant writeToActivePeriodNb: positive := 3; -- 1 CK + 66MHz * 20ns = 2.32 +--constant activeToReadPeriodNb: positive := 2; -- 66MHz * 20ns = 1.32 +--constant readToSamplePeriodNb: positive := 2; -- 2 CK with latency = 2 +--constant readToActivePeriodNb: positive := 3; -- 1 CK + 66MHz * 20ns = 2.32 + +subtype commandBusType is std_ulogic_vector(commandBusBitNb-1 downto 0); +-- bits: 5 = cs, 4 = ras, 3 = cas, 2 = we, 1 = dqm(1), 0 = dqm(0) +constant inhibit : commandBusType := \"1-----\"; +constant nop : commandBusType := \"0111--\"; +constant active : commandBusType := \"0011--\"; +constant read : commandBusType := \"010100\"; +constant write : commandBusType := \"010000\"; +constant burstTerminate : commandBusType := \"0110--\"; +constant precharge : commandBusType := \"0010--\"; +constant autoRefresh : commandBusType := \"0001--\"; +constant loadModeReg : commandBusType := \"0000--\";" +tm "LocalDeclTextMgr" +) +declType 2 +) +localPostDecl *102 (SmLocalDecl +uid 1651,0 +stg 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+decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 153,0 +) +) +) +*113 (CptPort +uid 2595,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2596,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,27625,51750,28375" +) +tg (CPTG +uid 2597,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2598,0 +va (VaSet +) +xt "44700,27500,50000,28500" +st "commandBus" +ju 2 +blo "50000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2599,0 +va (VaSet +font "courier,8,0" +) +xt "0,20500,39000,21400" +st "commandBus : OUT std_ulogic_vector ( commandBusBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "commandBus" +t "std_ulogic_vector" +b "( commandBusBitNb-1 DOWNTO 0 )" +o 12 +suid 154,0 +) +) +) +*114 (CptPort +uid 2600,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2601,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,9625,35000,10375" +) +tg (CPTG +uid 2602,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2603,0 +va (VaSet +) +xt "36000,9500,43500,10500" +st "endOfRefreshCount" +blo "36000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2604,0 +va (VaSet +font "courier,8,0" +) +xt "0,11500,20500,12400" +st "endOfRefreshCount : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "endOfRefreshCount" +t "std_ulogic" +o 2 +suid 155,0 +) +) +) +*115 (CptPort +uid 2605,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2606,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,9625,51750,10375" +) +tg (CPTG +uid 2607,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2608,0 +va (VaSet +) +xt "44400,9500,50000,10500" +st "powerUpDone" +ju 2 +blo "50000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2609,0 +va (VaSet +font "courier,8,0" +) +xt "0,21400,20500,22300" +st "powerUpDone : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "powerUpDone" +t "std_ulogic" +o 13 +suid 156,0 +) +) +) +*116 (CptPort +uid 2610,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2611,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,25625,51750,26375" +) +tg (CPTG +uid 2612,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2613,0 +va (VaSet +) +xt "44600,25500,50000,26500" +st "ramDataValid" +ju 2 +blo "50000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2614,0 +va (VaSet +font "courier,8,0" +) +xt "0,22300,20500,23200" +st "ramDataValid : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ramDataValid" +t "std_ulogic" +o 14 +suid 157,0 +) +) +) +*117 (CptPort +uid 2615,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2616,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,25625,35000,26375" +) +tg (CPTG +uid 2617,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2618,0 +va (VaSet +) +xt "36000,25500,38600,26500" +st "ramEn" +blo "36000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2619,0 +va (VaSet +font "courier,8,0" +) +xt "0,12400,20500,13300" +st "ramEn : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "ramEn" +t "std_ulogic" +o 3 +suid 158,0 +) +) +) +*118 (CptPort +uid 2620,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2621,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,21625,35000,22375" +) +tg (CPTG +uid 2622,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2623,0 +va (VaSet +) +xt "36000,21500,39100,22500" +st "readAck" +blo "36000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2624,0 +va (VaSet +font "courier,8,0" +) +xt "0,23200,20500,24100" +st "readAck : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "readAck" +t "std_ulogic" +o 15 +suid 159,0 +) +) +) +*119 (CptPort +uid 2625,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2626,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,19625,35000,20375" +) +tg (CPTG +uid 2627,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2628,0 +va (VaSet +) +xt "36000,19500,41200,20500" +st "readRequest" +blo "36000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2629,0 +va (VaSet +font "courier,8,0" +) +xt "0,13300,20500,14200" +st "readRequest : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "readRequest" +t "std_ulogic" +o 4 +suid 160,0 +) +) +) +*120 (CptPort +uid 2630,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2631,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,29625,35000,30375" +) +tg (CPTG +uid 2632,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2633,0 +va (VaSet +) +xt "36000,29500,38100,30500" +st "reset" +blo "36000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2634,0 +va (VaSet +font "courier,8,0" +) +xt "0,14200,20500,15100" +st "reset : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +suid 161,0 +) +) +) +*121 (CptPort +uid 2635,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2636,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,21625,51750,22375" +) +tg (CPTG +uid 2637,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2638,0 +va (VaSet +) +xt "45200,21500,50000,22500" +st "sampleData" +ju 2 +blo "50000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2639,0 +va (VaSet +font "courier,8,0" +) +xt "0,24100,20500,25000" +st "sampleData : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sampleData" +t "std_ulogic" +o 16 +suid 162,0 +) +) +) +*122 (CptPort +uid 2640,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2641,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,11625,35000,12375" +) +tg (CPTG +uid 2642,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2643,0 +va (VaSet +) +xt "36000,11500,39900,12500" +st "timerDone" +blo "36000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2644,0 +va (VaSet +font "courier,8,0" +) +xt "0,15100,36500,16000" +st "timerDone : IN std_ulogic_vector ( 1 TO maxDelayPeriodNb ) ;" +) +thePort (LogicalPort +decl (Decl +n "timerDone" +t "std_ulogic_vector" +b "( 1 TO maxDelayPeriodNb )" +o 6 +suid 163,0 +) +) +) +*123 (CptPort +uid 2645,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2646,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,11625,51750,12375" +) +tg (CPTG +uid 2647,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2648,0 +va (VaSet +) +xt "45900,11500,50000,12500" +st "timerStart" +ju 2 +blo "50000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2649,0 +va (VaSet +font "courier,8,0" +) +xt "0,25000,20500,25900" +st "timerStart : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "timerStart" +t "std_ulogic" +o 17 +suid 164,0 +) +) +) +*124 (CptPort +uid 2650,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2651,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,17625,35000,18375" +) +tg (CPTG +uid 2652,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2653,0 +va (VaSet +) +xt "36000,17500,39200,18500" +st "writeAck" +blo "36000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2654,0 +va (VaSet +font "courier,8,0" +) +xt "0,25900,19500,26800" +st "writeAck : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "writeAck" +t "std_ulogic" +o 18 +suid 165,0 +) +) +) +*125 (CptPort +uid 2655,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2656,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,15625,35000,16375" +) +tg (CPTG +uid 2657,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2658,0 +va (VaSet +) +xt "36000,15500,41300,16500" +st "writeRequest" +blo "36000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2659,0 +va (VaSet +font "courier,8,0" +) +xt "0,16000,20500,16900" +st "writeRequest : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "writeRequest" +t "std_ulogic" +o 7 +suid 166,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "35000,6000,51000,32000" +) +oxt "15000,6000,31000,30000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "courier,8,1" +) +xt "35750,32000,38750,32900" +st "Memory" +blo "35750,32700" +) +second (Text +uid 12,0 +va (VaSet +font "courier,8,1" +) +xt "35750,32900,45250,33800" +st "sdramControllerFsm" +blo "35750,33600" +) +) +gi *126 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "courier,8,0" +) +xt "35000,35200,69500,46000" +st "Generic Declarations + +commandBusBitNb positive 6 +maxDelayPeriodNb positive 10 +prechargeToRefreshPeriodNb positive 2 --66MHz * 20 ns = 1.32 +refreshDelayPeriodNb positive 5 --66MHz * 66ns = 4.356 +loadModeToActivePeriodNb positive 1 --1 CK +activeToWritePeriodNb positive 2 --66MHz * 20ns = 1.32 +writeToActivePeriodNb positive 3 --1 CK + 66MHz * 20ns = 2.32 +activeToReadPeriodNb positive 2 --66MHz * 20ns = 1.32 +readToSamplePeriodNb positive 2 --2 CK with latency = 2 +readToActivePeriodNb positive 3 --1 CK + 66MHz * 20ns = 2.32 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "commandBusBitNb" +type "positive" +value "6" +) +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "10" +) +(GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +(GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +(GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +(GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +(GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*127 (Grouping +uid 16,0 +optionalChildren [ +*128 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,48000,51000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,48000,49200,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*129 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,44000,55000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,44000,54800,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*130 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,46000,51000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,46000,50400,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*131 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,46000,34000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,46000,33800,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*132 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,45000,71000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,45200,64400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*133 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "55000,44000,71000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "55200,44000,57000,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*134 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,44000,51000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "36000,44500,45000,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*135 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,47000,34000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,47000,33200,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*136 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,48000,34000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,48000,33800,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*137 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,47000,51000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,47000,50400,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "30000,44000,71000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *138 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*139 (Text +uid 49,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,0,3400,1000" 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(VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *82 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,16800,3400,17800" +st "Declarations" +blo "-2000,17600" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,17800,700,18800" +st "Ports:" +blo "-2000,18600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,22400,500,23300" +st "User:" +blo "-2000,23100" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "-2000,16800,3800,17800" +st "Internal User:" +blo "-2000,17600" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "0,23300,0,23300" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "-2000,16800,-2000,16800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 234,0 +activeModelName "Symbol" +) diff --git a/Libs/Memory_test/hdl/Flash_behav.vhd b/Libs/Memory_test/hdl/Flash_behav.vhd new file mode 100644 index 0000000..3400d3a --- /dev/null +++ b/Libs/Memory_test/hdl/Flash_behav.vhd @@ -0,0 +1,528 @@ +use std.textio.all; + +ARCHITECTURE behav OF flash_28F128J3A IS + -- controls + signal chipSelect : std_ulogic; + signal writePulse : std_ulogic; + signal writePulseDelayed : std_ulogic; + signal memoryCommand : unsigned(7 downto 0); + signal wordProgramBusy : std_ulogic := '0'; + signal blockEraseBusy : std_ulogic := '0'; + signal busy : std_ulogic; + signal readPulseCs : std_ulogic := '0'; + signal readPulseOe : std_ulogic := '0'; + signal readPulse : std_ulogic; + + signal memoryAddressDebug : unsigned(A'range); + + type state_type is ( + READ_ARRAY, + READ_ID_CODES, + READ_QUERY, + READ_STATUS, + WRITE_BUFFER, + WORD_PROGRAM_1, + WORD_PROGRAM_2, + BLOCK_ERASE_1, + BLOCK_ERASE_2, + CONFIG, + PROG_LOCK_BITS, + PROG_PROT, + BOTCH_LOCK,-- + BOTCH_LOCK_ERS_SUSP,-- + LOCK_DONE, + PROG_LOCK_BITS_ERS_SUSP,-- + LOCK_DONE_ERS_SUSP, + PROT_PROG_BUSY,-- + PROT_PROG_DONE,-- + WORD_PROGRAM_1_ERS_SUSP,-- + PROG_BUSY,-- + PROG_BUSY_ERS_SUSP,-- + READ_STATUS_PROG_SUSP,-- + READ_ARRAY_PROG_SUSP,-- + READ_CONFIG_PROG_SUSP,-- + READ_QUERY_PROG_SUSP,-- + PROGRAM_DONE,-- + PROGRAM_DONE_ERS_SUSP,-- + BOTCH_ERS,-- + ERASE_BUSY,-- + READ_STATUS_ERS_SUSP,-- + READ_ARRAY_ERS_SUSP,-- + READ_CONFIG_ERS_SUSP,-- + READ_QUERY_ERS_SUSP,-- + ERASE_DONE-- + ); + + signal currentState : state_type; + signal nextState : state_type; + -- storage + constant blockLength : positive:= 16#10000#; -- 64 Kword blocks + constant memoryLength: positive := 2**(A'length-1); +-- constant memoryLength : positive := 2*blockLength; + subtype memoryWord is std_ulogic_vector(DQ'range); + type memoryArray is array(0 to memoryLength-1) of memoryWord; + signal memoryDataWord : memoryWord; + +BEGIN + + --############################################################################ + -- Controls + ------------------------------------------------------------------------------ + + chipSelect <= ( (not CE(2)) and (not CE(1)) and (not CE(0)) ) or + ( CE(2) and ( (not CE(1)) or (not CE(0)) ) ); + writePulse <= chipSelect and not(WE_n); + writePulseDelayed <= writePulse after 1 ns; + + memoryCommand <= unsigned(DQ(memoryCommand'range)); + + process(chipSelect) + begin + if rising_edge(chipSelect) then + readPulseCs <= '1' after T_R3; + elsif falling_edge(chipSelect) then + readPulseCs <= '0' after T_R8; + end if; + end process; + + process(OE_n) + begin + if falling_edge(OE_n) then + readPulseOe <= '1' after T_R7; + elsif rising_edge(OE_n) then + readPulseOe <= '0' after T_R9; + end if; + end process; + + readPulse <= readPulseCs and readPulseOe; + + ------------------------------------------------------------------------------ + -- Programming delays + ------------------------------------------------------------------------------ + + wordProgramBusy <= '1', '0' after T_W16_program when currentState = WORD_PROGRAM_2; + blockEraseBusy <= '1', '0' after T_W16_erase when currentState = BLOCK_ERASE_2; + busy <= wordProgramBusy or blockEraseBusy; + + + ------------------------------------------------------------------------------ + -- FSM: find next state + ------------------------------------------------------------------------------ + -- Table 4 p. 12 + process(writePulse, busy) + begin + case currentState is + when READ_ARRAY | READ_ID_CODES | READ_QUERY | READ_STATUS => + case to_integer(memoryCommand) is + when 16#FF# => nextState <= READ_ARRAY; + when 16#90# => nextState <= READ_ID_CODES; + when 16#98# => nextState <= READ_QUERY; + when 16#70# => nextState <= READ_STATUS; + when 16#E8# => nextState <= WRITE_BUFFER; + when 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; + when 16#20# => nextState <= BLOCK_ERASE_1; + when 16#B8# => nextState <= CONFIG; + when 16#60# => nextState <= PROG_LOCK_BITS; + when 16#C0# => nextState <= PROG_PROT; + when others => nextState <= READ_ARRAY; + end case; + + when WORD_PROGRAM_1 => + nextState <= WORD_PROGRAM_2; + + when WORD_PROGRAM_2 => + nextState <= READ_ARRAY; + + when BLOCK_ERASE_1 => + if to_integer(memoryCommand) = 16#D0# then + nextState <= BLOCK_ERASE_2; + else + nextState <= READ_ARRAY; + end if; + + when BLOCK_ERASE_2 => + nextState <= READ_ARRAY; + +-- WHEN PROG_LOCK_BITS => +-- IF rising_edge(WENeg) THEN +-- -- SECOND CYCLE CHECK +-- IF data=16#D0# OR data=16#01# OR data=16#2F# THEN +-- nextState<=READ_ARRAY; +-- ELSE +-- nextState <= BOTCH_LOCK; +-- END IF; +-- END IF; +-- +-- WHEN PROG_LOCK_BITS_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- IF data=16#D0# OR data=16#01# OR data=16#2F# THEN +-- nextState<=READ_ARRAY_ERS_SUSP; +-- ELSE +-- nextState <= BOTCH_LOCK_ERS_SUSP; +-- END IF; +-- END IF; +-- +-- +-- WHEN LOCK_DONE => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- WHEN LOCK_DONE_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1_ERS_SUSP; +-- WHEN 16#70# => nextState <= READ_STATUS_ERS_SUSP; +-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP; +-- WHEN 16#D0# => nextState <= ERASE_BUSY; +-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP; +-- END CASE; +-- END IF; +-- +-- WHEN BOTCH_LOCK => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- WHEN BOTCH_LOCK_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => +-- nextState <= WORD_PROGRAM_1_ERS_SUSP; +-- WHEN 16#70# => nextState <= READ_STATUS_ERS_SUSP; +-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP; +-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP; +-- END CASE; +-- END IF; +-- +-- +-- WHEN BOTCH_ERS => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => +-- nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <=BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- +-- WHEN PROG_PROT => +-- IF rising_edge(WENeg) THEN +-- nextState <= PROT_PROG_BUSY; +-- END IF; +-- +-- WHEN PROT_PROG_BUSY => +-- IF S_Reg(7)='1' THEN +-- nextState <= PROT_PROG_DONE; +-- ELSE +-- nextState <= PROT_PROG_BUSY; +-- END IF; +-- +-- WHEN PROT_PROG_DONE => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- WHEN WORD_PROGRAM_1 => +-- IF rising_edge(WENeg) THEN +-- nextState <= PROG_BUSY; +-- END IF; +-- +-- WHEN WORD_PROGRAM_1_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- nextState <= PROG_BUSY_ERS_SUSP; +-- END IF; +-- +-- WHEN PROG_BUSY => +-- IF WDone THEN +-- nextState<=PROGRAM_DONE; +-- ELSIF rising_edge(WENeg) THEN +-- IF data= 16#B0# THEN +-- nextState <= READ_STATUS_PROG_SUSP; +-- ELSE +-- nextState <= PROG_BUSY; +-- END IF; +-- END IF; +-- +-- WHEN PROG_BUSY_ERS_SUSP => +-- IF WDone THEN +-- nextState<=PROGRAM_DONE_ERS_SUSP; +-- ELSIF rising_edge(WENeg) THEN +-- nextState <= PROG_BUSY_ERS_SUSP; +-- END IF; +-- +-- WHEN READ_STATUS_PROG_SUSP | READ_ARRAY_PROG_SUSP | +-- READ_CONFIG_PROG_SUSP | READ_QUERY_PROG_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- --WHEN 16#D0# => nextState <= READ_ARRAY_PROG_SUSP; +-- WHEN 16#D0# => nextState <= PROG_BUSY; +-- WHEN 16#B0# | 16#70# => nextState <= READ_STATUS_PROG_SUSP; +-- WHEN 16#90# => nextState <= READ_CONFIG_PROG_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_PROG_SUSP; +-- WHEN OTHERS => nextState <= READ_ARRAY_PROG_SUSP; +-- END CASE; +-- END IF; +-- +-- WHEN PROGRAM_DONE => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- WHEN PROGRAM_DONE_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1_ERS_SUSP; +-- WHEN 16#B0# | 16#70# => nextState <= READ_STATUS_ERS_SUSP; +-- WHEN 16#D0# => nextState <= ERASE_BUSY; +-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP; +-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP; +-- END CASE; +-- END IF; +-- +-- +-- WHEN ERASE_BUSY => +-- IF rising_edge(WENeg) AND data= 16#B0# THEN +-- nextState <= READ_STATUS_ERS_SUSP; +-- ELSIF EDone AND ECount=31 THEN +-- nextState<=ERASE_DONE; +-- ELSE +-- nextState <= ERASE_BUSY; +-- END IF; +-- +-- WHEN READ_STATUS_ERS_SUSP | READ_ARRAY_ERS_SUSP | +-- READ_CONFIG_ERS_SUSP | READ_QUERY_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <=WORD_PROGRAM_1_ERS_SUSP; +-- WHEN 16#B0# | 16#70# | 16#80# => +-- nextState<= READ_STATUS_ERS_SUSP; +-- WHEN 16#D0# => nextState <= ERASE_BUSY; +-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP; +-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP; +-- END CASE; +-- END IF; +-- +-- WHEN ERASE_DONE => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; + +when others => nextState <= READ_ARRAY; + + end case; + end process; + + + ------------------------------------------------------------------------------ + -- FSM: update state + ------------------------------------------------------------------------------ + process(RP_N, writePulseDelayed, busy) + begin + if RP_n = '0' then + currentState <= READ_ARRAY; + elsif falling_edge(writePulseDelayed) then + currentState <= nextState; + elsif falling_edge(busy) then + currentState <= nextState; + end if; + end process; + + + ------------------------------------------------------------------------------ + -- STS + ------------------------------------------------------------------------------ + process + begin + STS <= '1'; + wait on busy; + if rising_edge(busy) then + STS <= '0' after T_W13; + wait until falling_edge(busy); + end if; + end process; + + + --############################################################################ + -- Storage + ------------------------------------------------------------------------------ + process(writePulse, A) + variable memContent : memoryArray; -- much faster than using a signal + variable loadMemFromFile : boolean := true; + file memoryFile : text open read_mode is fileSpec; + variable srecLine : line; + variable srecChar : character; + variable srecType : natural; + variable srecAddrLength : natural; + variable srecWordAscii : string(8 downto 1); + variable srecLength : natural; + variable srecAddress : natural; + variable memoryAddress : natural; + variable srecData : natural; + + function readNumber(hexString: string) return natural is + variable currentCharPos: natural; + variable intValue: natural; + variable accValue: natural; + begin + accValue := 0; + for index in hexString'range loop + currentCharPos := character'pos(hexString(index)); + if currentCharPos <= character'pos('9') then + intValue := currentCharPos - character'pos('0'); + else + intValue := currentCharPos - character'pos('A') + 10; + end if; + accValue := accValue * 16 + intValue; + end loop; + return accValue; + end readNumber; + + begin + if loadMemFromFile then + -- only happens at simulation start + while not endfile(memoryFile) loop + readline(memoryFile, srecLine); + --report "-> " & srecLine.all; + -- trim leading whitespaces + while (not (srecLine'length=0)) and (srecLine(srecLine'left) = ' ') loop + read(srecLine, srecChar); + end loop; + -- get record type + if srecLine'length > 0 then + read(srecLine, srecChar); + if (srecChar = 'S') or (srecChar = 's') then + read(srecLine, srecChar); + srecType := character'pos(srecChar) - character'pos('0'); + --report "-> srec type: " & integer'image(srecType); + srecAddrLength := srecType + 1; + if (srecType >= 1) and (srecType <= 3) then + -- get record length + srecWordAscii := (others => '0'); + read(srecLine, srecWordAscii(2)); + read(srecLine, srecWordAscii(1)); + srecLength := readNumber(srecWordAscii); + -- get record base address + srecWordAscii := (others => '0'); + for index in 2*(srecAddrLength) downto 1 loop + read(srecLine, srecWordAscii(index)); + end loop; + srecAddress := readNumber(srecWordAscii); + memoryAddress := srecAddress/2; + -- get record data + for index1 in 1 to (srecLength - srecAddrLength - 1) / 2 loop + srecWordAscii := (others => '0'); + for index2 in 4 downto 1 loop + read(srecLine, srecWordAscii(index2)); + end loop; + srecData := readNumber(srecWordAscii); + if memoryAddress < memoryLength then + memContent(memoryAddress) := std_ulogic_vector(to_unsigned(srecData, memoryWord'length)); + end if; + memoryAddress := memoryAddress + 1; + end loop; + end if; + end if; + end if; + end loop; + loadMemFromFile := false; + else + -- normal functionality + if falling_edge(writePulse) then + -- program a word + if currentState = WORD_PROGRAM_1 then + memoryAddress := to_integer(A(A'high downto 1)); +memoryAddressDebug <= to_unsigned(memoryAddress, memoryAddressDebug'length); + memContent(memoryAddress) := std_ulogic_vector(DQ); + -- erase a block + elsif currentState = BLOCK_ERASE_1 then + memoryAddress := to_integer(A and not(to_unsigned(blockLength-1, A'length))); + for index in 0 to blockLength-1 loop + if memoryAddress < memoryLength then + memContent(memoryAddress) := (others => '1'); + memoryAddress := memoryAddress + 1; + end if; + end loop; + end if; + end if; + -- update readout data + if A'event then + memoryAddress := to_integer(A(A'high downto 1)); +memoryAddressDebug <= to_unsigned(memoryAddress, memoryAddressDebug'length); + memoryDataWord <= memContent(memoryAddress) after T_R2; + end if; + end if; + end process; + + process(memoryDataWord, readPulse) + begin + if readPulse = '1' then + DQ <= std_logic_vector(memoryDataWord); + else + DQ <= (others => 'Z'); + end if; + end process; + + + +END ARCHITECTURE behav; + diff --git a/Libs/Memory_test/hdl/bram_tester_test.vhd b/Libs/Memory_test/hdl/bram_tester_test.vhd new file mode 100644 index 0000000..36c3016 --- /dev/null +++ b/Libs/Memory_test/hdl/bram_tester_test.vhd @@ -0,0 +1,83 @@ +ARCHITECTURE test OF bram_tester IS + + constant clockFrequencyA: real := 66.0E6; + constant clockFrequencyB: real := 20.0E6; + constant clockPeriodA: time := (1.0/clockFrequencyA) * 1 sec; + constant clockPeriodB: time := (1.0/clockFrequencyB) * 1 sec; + signal clockA_int: std_uLogic := '1'; + signal clockB_int: std_uLogic := '1'; + + signal addressA_int: natural; + signal dataA_int: integer; + + signal addressB_int: natural; + signal dataB_int: integer; + +BEGIN + ------------------------------------------------------------------------------ + -- clocks + clockA_int <= not clockA_int after clockPeriodA/2; + clockA <= transport clockA_int after clockPeriodA*9/10; + + clockB_int <= not clockB_int after clockPeriodB/2; + clockB <= transport clockB_int after clockPeriodB*9/10; + + ------------------------------------------------------------------------------ + -- test sequence + portA: process + begin + enA <= '0'; + writeEnA <= '0'; + addressA_int <= 0; + dataA_int <= 0; + -- read initial BRAM data + wait for 5*clockPeriodA; + addressA_int <= 40; + enA <= '1'; + wait for clockPeriodA; + enA <= '0'; + -- write data on port A + wait for 10*clockPeriodA; + addressA_int <= 10; + dataA_int <= 5; + enA <= '1'; + writeEnA <= '1'; + wait for clockPeriodA; + enA <= '0'; + writeEnA <= '0'; + + wait; + end process portA; + + addressA <= std_ulogic_vector(to_unsigned(addressA_int, addressA'length)); + dataInA <= std_ulogic_vector(to_signed(dataA_int, dataInA'length)); + + portB: process + begin + enB <= '0'; + writeEnB <= '0'; + addressB_int <= 0; + dataB_int <= 0; + -- write data on port B + wait for 10*clockPeriodB; + addressB_int <= 20; + dataB_int <= 10; + enB <= '1'; + writeEnB <= '1'; + wait for clockPeriodB; + enB <= '0'; + writeEnB <= '0'; + -- read data written on port A + wait for 2*clockPeriodB; + addressB_int <= 10; + enB <= '1'; + wait for clockPeriodB; + enB <= '0'; + + wait; + end process portB; + + addressB <= std_ulogic_vector(to_unsigned(addressB_int, addressB'length)); + dataInB <= std_ulogic_vector(to_signed(dataB_int, dataInB'length)); + +END ARCHITECTURE test; diff --git a/Libs/Memory_test/hdl/fifo_tester_test.vhd b/Libs/Memory_test/hdl/fifo_tester_test.vhd new file mode 100644 index 0000000..388de8a --- /dev/null +++ b/Libs/Memory_test/hdl/fifo_tester_test.vhd @@ -0,0 +1,339 @@ +--LIBRARY std; +-- USE std.textio.ALL; +LIBRARY COMMON_TEST; + USE COMMON_TEST.testUtils.all; + +ARCHITECTURE test OF fifo_tester IS + + constant clockFrequency: real := 66.0E6; + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_ulogic := '1'; + + constant testInterval: time := 10*clockPeriod; + signal dataIn_int: integer; + signal read_int: std_ulogic; + signal dataOffset: integer; + + signal dataValid: std_ulogic; + signal dataRead: integer; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- test sequence + process + variable readIndex: integer; + begin + write <= '0'; + read_int <= '0'; + dataOffset <= -16#10#; + wait for 5*clockPeriod; + print( + lf & lf & lf & + "----------------------------------------------------------------" & lf & + "Starting testbench" & lf & + lf & lf + ); + + --.......................................................................... + -- full write / read after end of write + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", full FIFO write direclty followed by full read" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1'; + for index in 0 to fifoDepth-1 loop + dataIn_int <= dataOffset + index; + wait for clockPeriod; + end loop; + write <= '0'; + -- read FIFO + read_int <= '1'; + readIndex := 0; + while empty = '0' loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + + --.......................................................................... + -- full write / read after some time + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", full FIFO write and delay before read" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1'; + for index in 0 to fifoDepth-1 loop + dataIn_int <= dataOffset + index; + wait for clockPeriod; + end loop; + write <= '0'; + -- wait before read + wait for 4*clockPeriod; + -- read FIFO + read_int <= '1'; + readIndex := 0; + while empty = '0' loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + + --.......................................................................... + -- write / read direct + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", full FIFO write with asynchronous direct read" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1', '0' after 8*clockPeriod; + dataIn_int <= dataOffset + 16#00#, + dataOffset + 16#01# after 1*clockPeriod, + dataOffset + 16#02# after 2*clockPeriod, + dataOffset + 16#03# after 3*clockPeriod, + dataOffset + 16#04# after 4*clockPeriod, + dataOffset + 16#05# after 5*clockPeriod, + dataOffset + 16#06# after 6*clockPeriod, + dataOffset + 16#07# after 7*clockPeriod; + -- read FIFO + wait until empty = '0'; + read_int <= '1'; + readIndex := -1; + while empty = '0' loop + if readIndex >= 0 then + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + end if; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + + --.......................................................................... + -- write / read direct with clock period delay + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", full FIFO write with synchronous direct read" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1', '0' after 8*clockPeriod; + dataIn_int <= dataOffset + 16#00#, + dataOffset + 16#01# after 1*clockPeriod, + dataOffset + 16#02# after 2*clockPeriod, + dataOffset + 16#03# after 3*clockPeriod, + dataOffset + 16#04# after 4*clockPeriod, + dataOffset + 16#05# after 5*clockPeriod, + dataOffset + 16#06# after 6*clockPeriod, + dataOffset + 16#07# after 7*clockPeriod; + -- read FIFO + wait until empty = '0'; + wait until rising_edge(clock_int); + read_int <= '1'; + readIndex := 0; + while empty = '0' loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + + --.......................................................................... + -- slow read sets FIFO full + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", slow reading sets FIFO full and requires waiting before writing on" & + lf & lf + ); + -- prepare slow FIFO reading + wait until rising_edge(clock_int); + wait for 2*clockPeriod; + read_int <= '1' after 4*clockPeriod, + '0' after 5*clockPeriod, + '1' after 14*clockPeriod, + '0' after 15*clockPeriod, + '1' after 24*clockPeriod, + '0' after 25*clockPeriod, + '1' after 34*clockPeriod, + '0' after 35*clockPeriod, + '1' after 44*clockPeriod, + '0' after (45+2*fifoDepth-5)*clockPeriod; + -- write 2*FIFO depth + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + for index in 0 to 2*fifoDepth-1 loop + dataIn_int <= dataOffset + index; + if full = '1' then + wait until full = '0'; + wait for clockPeriod/8; + end if; + write <= '1'; + wait until rising_edge(clock_int); + write <= '0'; + end loop; + + --.......................................................................... + -- write over full + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", attempt to write after FIFO full" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1'; + for index in 0 to fifoDepth+3 loop + dataIn_int <= dataOffset + index; + wait for clockPeriod; + end loop; + write <= '0'; + + --.......................................................................... + -- read FIFO once too much + print( + "At time " & sprintf("%9.3tu", now) & + ", attempt to read after FIFO empty" & + lf & lf + ); + read_int <= '1'; + wait for clockPeriod; + wait until empty = '1'; + wait for clockPeriod; + read_int <= '0'; + -- read when empty + wait until rising_edge(clock_int); + wait for 2*clockPeriod; + read_int <= '1'; + wait for 2*clockPeriod; + read_int <= '0'; + + --.......................................................................... + -- read constantly + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", reading FIFO constantly (data valid when empty = '0')" & + lf & lf + ); + + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + read_int <= '1'; + wait for 2*clockPeriod; + wait until rising_edge(clock_int); + readIndex := -1; + write <= '1'; + for index in 0 to fifoDepth-1 loop + if empty = '0' then + readIndex := readIndex + 1; + end if; + if (readIndex >= 0) and (empty = '0') then + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + end if; + dataIn_int <= dataOffset + index; + wait until rising_edge(clock_int); + end loop; + write <= '0'; + + wait until empty = '1'; + wait for 2*clockPeriod; + read_int <= '0'; + + --.......................................................................... + -- full write / read with breaks + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", reading FIFO with breaks" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1'; + for index in 0 to fifoDepth-1 loop + dataIn_int <= dataOffset + index; + wait for clockPeriod; + end loop; + write <= '0'; + -- wait before read + wait for 2*clockPeriod; + -- read FIFO + wait until rising_edge(clock_int); + readIndex := 0; + for index in 0 to fifoDepth/4-1 loop + read_int <= '1'; + for rdIndex in 1 to 2 loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + wait for 2*clockPeriod; + end loop; + read_int <= '1'; + while empty = '0' loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + --.......................................................................... + -- end of tests + wait for testInterval; + assert false + report "END SIMULATION" + severity failure; + wait; + end process; + + dataIn <= std_ulogic_vector(to_signed(dataIn_int, dataIn'length)); + read <= read_int; + + dataValid <= '1' when (read_int = '1') and (empty = '0') + else '0'; + dataRead <= to_integer(signed(dataOut)) when dataValid = '1' + else 0; + +END ARCHITECTURE test; diff --git a/Libs/Memory_test/hdl/flashController_tester_test.vhd b/Libs/Memory_test/hdl/flashController_tester_test.vhd new file mode 100644 index 0000000..77157e6 --- /dev/null +++ b/Libs/Memory_test/hdl/flashController_tester_test.vhd @@ -0,0 +1,88 @@ +LIBRARY BoardTester_test; + USE BoardTester_test.testUtils.all; + +ARCHITECTURE test OF flashController_tester IS + + constant clockFrequency: real := 66.0E6; + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + + signal flashAddr_int: natural := 0; + signal flashDataOut_int: natural := 0; + + signal refreshEn: std_uLogic := '0'; + + constant separator : string(1 to 80) := (others => '-'); + constant indent : string(1 to 2) := (others => ' '); + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- flash access + process + begin + flashRd <= '0'; + flashWr <= '0'; + flashEn <= '1'; + wait for 1 us; + print(cr & separator); + -- erase block 0 + print(sprintf("%tu", now) & ": Erasing block 0"); + flashAddr_int <= 16#10000#; + flashDataOut_int <= 16#0020#; + flashWr <= '1', '0' after clockPeriod; + wait until falling_edge(flashDataValid); + wait for clockPeriod/10; + flashDataOut_int <= 16#00D0#; + flashWr <= '1', '0' after clockPeriod; + wait for 2 us; + -- program word + print(sprintf("%tu", now) & ": Writing data into Flash"); + flashAddr_int <= 16#0000#; + flashDataOut_int <= 16#0040#; + flashWr <= '1', '0' after clockPeriod; + wait until falling_edge(flashDataValid); + wait for clockPeriod/10; + flashAddr_int <= 16#0010#; + flashDataOut_int <= 16#CAFE#; + flashWr <= '1', '0' after clockPeriod; + wait for 2 us; + -- read word + print(sprintf("%tu", now) & ": Reading data from Flash"); + flashAddr_int <= 16#0000#; + flashRd <= '1', '0' after clockPeriod; + wait for 1 us; + -- read word + print(sprintf("%tu", now) & ": Reading data from Flash"); + flashAddr_int <= 16#000F#; + flashRd <= '1', '0' after clockPeriod; + wait for 500 ns; + flashAddr_int <= 16#0010#; + flashRd <= '1', '0' after clockPeriod; + wait for 500 ns; + flashAddr_int <= 16#0011#; + flashRd <= '1', '0' after clockPeriod; + wait for 500 ns; + + wait; + end process; + + ------------------------------------------------------------------------------ + -- address and data + flashAddr <= to_unsigned(flashAddr_int, flashAddr'length); + flashDataOut <= std_ulogic_vector(to_unsigned(flashDataOut_int, flashDataOut'length)); + + ------------------------------------------------------------------------------ + -- memory bus hold + refreshEn <= '1' after 15*clockPeriod when refreshEn = '0' + else '0' after clockPeriod; + memBusEn_n <= refreshEn; + +END ARCHITECTURE test; + diff --git a/Libs/Memory_test/hdl/flash_tester_test.vhd b/Libs/Memory_test/hdl/flash_tester_test.vhd new file mode 100644 index 0000000..023ea1a --- /dev/null +++ b/Libs/Memory_test/hdl/flash_tester_test.vhd @@ -0,0 +1,102 @@ +LIBRARY BoardTester_test; + USE BoardTester_test.testUtils.all; + +ARCHITECTURE test OF flash_tester IS + + constant T_W2: time := 0 ns; + constant T_W3: time := 70 ns; + constant T_W4: time := 50 ns; + constant T_W5: time := 55 ns; + constant T_W6: time := 10 ns; + constant T_R3: time := 120 ns; + + signal addr: natural; + signal data: integer; + + signal writeFlash: std_ulogic := '0'; + signal readFlash: std_ulogic := '0'; + + constant separator : string(1 to 80) := (others => '-'); + constant indent : string(1 to 2) := (others => ' '); + +BEGIN + + ------------------------------------------------------------------------------ + -- Test + ------------------------------------------------------------------------------ + process + begin + RP_n <= '1'; + wait for 1 us; + print(cr & separator); + -- erase block 0 + print(sprintf("%tu", now) & ": Erasing block 0"); + addr <= 16#10000#; + data <= 16#20#; + writeFlash <= '1', '0' after 1 ns; + wait for 100 ns; + data <= 16#D0#; + writeFlash <= '1', '0' after 1 ns; + wait for 2 us; + -- program word + print(sprintf("%tu", now) & ": Writing data into Flash"); + addr <= 16#0000#; + data <= 16#0040#; + writeFlash <= '1', '0' after 1 ns; + wait for 100 ns; + addr <= 16#0010#; + data <= 16#CAFE#; + writeFlash <= '1', '0' after 1 ns; + wait for 2 us; + -- read word + print(sprintf("%tu", now) & ": Reading data from Flash"); + addr <= 16#0000#; + readFlash <= '1', '0' after 1 ns; + wait for 500 ns; + -- read word + print(sprintf("%tu", now) & ": Reading data from Flash"); + addr <= 16#0010#; + readFlash <= '1', '0' after 1 ns; + wait for 500 ns; + + wait; + end process; + + ------------------------------------------------------------------------------ + -- Board connections + ------------------------------------------------------------------------------ + CE(2 downto 1) <= (others => '0'); + BYTE_n <= '1'; + + + ------------------------------------------------------------------------------ + -- Write access + ------------------------------------------------------------------------------ + process + begin + CE(0) <= '1'; + WE_N <= '1'; + OE_N <= '1'; + DQ <= (others => 'Z'); + wait on writeFlash, readFlash; + if rising_edge(writeFlash) then + A <= to_unsigned(addr, A'length) after T_W3 - T_W5; + DQ <= std_logic_vector(to_unsigned(data, DQ'length)) after T_W3 - T_W4; + CE(0) <= '0'; + wait for T_W2; + WE_N <= '0'; + wait for T_W3; + WE_N <= '1'; + wait for T_W6; +-- CE(0) <= '1'; + elsif rising_edge(readFlash) then + OE_N <= '0'; + A <= to_unsigned(addr, A'length); + CE(0) <= '0'; + wait for T_R3 + 10 ns; +-- CE(0) <= '1'; + end if; + end process; + +END ARCHITECTURE test; + diff --git a/Libs/Memory_test/hdl/mti_pkg_pkg.vhd b/Libs/Memory_test/hdl/mti_pkg_pkg.vhd new file mode 100644 index 0000000..a83599d --- /dev/null +++ b/Libs/Memory_test/hdl/mti_pkg_pkg.vhd @@ -0,0 +1,18 @@ +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE std.textio.all; + +PACKAGE mti_pkg IS + + FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC; + FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER; + FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER; + FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER; + FUNCTION TO_INTEGER (input : STD_ULOGIC_VECTOR) RETURN INTEGER; + PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR); + + function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector; + procedure hexread(L : inout line; value:out bit_vector); + procedure hexread(L : inout line; value:out std_logic_vector); + +END mti_pkg; diff --git a/Libs/Memory_test/hdl/mti_pkg_pkg_body.vhd b/Libs/Memory_test/hdl/mti_pkg_pkg_body.vhd new file mode 100644 index 0000000..422a4ab --- /dev/null +++ b/Libs/Memory_test/hdl/mti_pkg_pkg_body.vhd @@ -0,0 +1,234 @@ +LIBRARY ieee; + USE ieee.numeric_std.all; + +PACKAGE BODY mti_pkg IS + + -- Convert BIT to STD_LOGIC + FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS + BEGIN + CASE s IS + WHEN '0' => RETURN ('0'); + WHEN '1' => RETURN ('1'); + WHEN OTHERS => RETURN ('0'); + END CASE; + END; + + -- Convert STD_LOGIC to INTEGER + FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + IF input = '1' THEN + result := weight; + ELSE + result := 0; -- if unknowns, default to logic 0 + END IF; + RETURN result; + END TO_INTEGER; + + -- Convert BIT_VECTOR to INTEGER + FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + FOR i IN input'LOW TO input'HIGH LOOP + IF input(i) = '1' THEN + result := result + weight; + ELSE + result := result + 0; -- if unknowns, default to logic 0 + END IF; + weight := weight * 2; + END LOOP; + RETURN result; + END TO_INTEGER; + + -- Convert STD_LOGIC_VECTOR to INTEGER + FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + FOR i IN input'LOW TO input'HIGH LOOP + IF input(i) = '1' THEN + result := result + weight; + ELSE + result := result + 0; -- if unknowns, default to logic 0 + END IF; + weight := weight * 2; + END LOOP; + RETURN result; + END TO_INTEGER; + + -- Convert STD_ULOGIC_VECTOR to INTEGER + FUNCTION TO_INTEGER (input : STD_ULOGIC_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + FOR i IN input'LOW TO input'HIGH LOOP + IF input(i) = '1' THEN + result := result + weight; + ELSE + result := result + 0; -- if unknowns, default to logic 0 + END IF; + weight := weight * 2; + END LOOP; + RETURN result; + END TO_INTEGER; + + -- Conver INTEGER to BIT_VECTOR + PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS + VARIABLE work,offset,outputlen,j : INTEGER := 0; + BEGIN + --length of vector + IF output'LENGTH > 32 THEN --' + outputlen := 32; + offset := output'LENGTH - 32; --' + IF input >= 0 THEN + FOR i IN offset-1 DOWNTO 0 LOOP + output(output'HIGH - i) := '0'; --' + END LOOP; + ELSE + FOR i IN offset-1 DOWNTO 0 LOOP + output(output'HIGH - i) := '1'; --' + END LOOP; + END IF; + ELSE + outputlen := output'LENGTH; --' + END IF; + --positive value + IF (input >= 0) THEN + work := input; + j := outputlen - 1; + FOR i IN 1 to 32 LOOP + IF j >= 0 then + IF (work MOD 2) = 0 THEN + output(output'HIGH-j-offset) := '0'; --' + ELSE + output(output'HIGH-j-offset) := '1'; --' + END IF; + END IF; + work := work / 2; + j := j - 1; + END LOOP; + IF outputlen = 32 THEN + output(output'HIGH) := '0'; --' + END IF; + --negative value + ELSE + work := (-input) - 1; + j := outputlen - 1; + FOR i IN 1 TO 32 LOOP + IF j>= 0 THEN + IF (work MOD 2) = 0 THEN + output(output'HIGH-j-offset) := '1'; --' + ELSE + output(output'HIGH-j-offset) := '0'; --' + END IF; + END IF; + work := work / 2; + j := j - 1; + END LOOP; + IF outputlen = 32 THEN + output(output'HIGH) := '1'; --' + END IF; + END IF; + END TO_BITVECTOR; + + + function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is + variable tmp : std_logic_vector(w-1 downto 0); + begin + tmp := std_logic_vector(to_unsigned(i, w)); + return(tmp); + end; + + procedure char2hex(C: character; result: out bit_vector(3 downto 0); + good: out boolean; report_error: in boolean) is + begin + good := true; + case C is + when '0' => result := x"0"; + when '1' => result := x"1"; + when '2' => result := X"2"; + when '3' => result := X"3"; + when '4' => result := X"4"; + when '5' => result := X"5"; + when '6' => result := X"6"; + when '7' => result := X"7"; + when '8' => result := X"8"; + when '9' => result := X"9"; + when 'A' => result := X"A"; + when 'B' => result := X"B"; + when 'C' => result := X"C"; + when 'D' => result := X"D"; + when 'E' => result := X"E"; + when 'F' => result := X"F"; + + when 'a' => result := X"A"; + when 'b' => result := X"B"; + when 'c' => result := X"C"; + when 'd' => result := X"D"; + when 'e' => result := X"E"; + when 'f' => result := X"F"; + when others => + if report_error then + assert false report + "hexread error: read a '" & C & "', expected a hex character (0-F)."; + end if; + good := false; + end case; + end; + + procedure hexread(L:inout line; value:out bit_vector) is + variable OK: boolean; + variable C: character; + constant NE: integer := value'length/4; --' + variable BV: bit_vector(0 to value'length-1); --' + variable S: string(1 to NE-1); + begin + if value'length mod 4 /= 0 then --' + assert false report + "hexread Error: Trying to read vector " & + "with an odd (non multiple of 4) length"; + return; + end if; + + loop -- skip white space + read(L,C); + exit when ((C /= ' ') and (C /= CR) and (C /= HT)); + end loop; + + char2hex(C, BV(0 to 3), OK, false); + if not OK then + return; + end if; + + read(L, S, OK); +-- if not OK then +-- assert false report "hexread Error: Failed to read the STRING"; +-- return; +-- end if; + + for I in 1 to NE-1 loop + char2hex(S(I), BV(4*I to 4*I+3), OK, false); + if not OK then + return; + end if; + end loop; + value := BV; + end hexread; + + procedure hexread(L:inout line; value:out std_ulogic_vector) is + variable tmp: bit_vector(value'length-1 downto 0); --' + begin + hexread(L, tmp); + value := TO_X01(tmp); + end hexread; + + procedure hexread(L:inout line; value:out std_logic_vector) is + variable tmp: std_ulogic_vector(value'length-1 downto 0); --' + begin + hexread(L, tmp); + value := std_logic_vector(tmp); + end hexread; + +END mti_pkg; diff --git a/Libs/Memory_test/hdl/sdramController_tester_test.vhd b/Libs/Memory_test/hdl/sdramController_tester_test.vhd new file mode 100644 index 0000000..317fb6d --- /dev/null +++ b/Libs/Memory_test/hdl/sdramController_tester_test.vhd @@ -0,0 +1,82 @@ +ARCHITECTURE test OF sdramController_tester IS + + constant clockFrequency: real := 66.0E6; + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + + signal ramAddr_int: natural := 0; + signal ramDataOut_int: natural := 0; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- test sequence + process + begin + ramRd <= '0'; + ramWr <= '0'; + ramEn <= '1'; + -- wait for SDRAM ready + wait for 154.3 us - now; + -- write AAAA at address 000010 + ramAddr_int <= 16#000010#; + ramDataOut_int <= 16#AAAA#; + ramWr <= '1', '0' after clockPeriod; + -- wait for SDRAM ready + wait for 164.5 us - now; + -- write AAAA at address 000011 + ramAddr_int <= 16#000011#; + ramDataOut_int <= 16#BBBD#; + ramWr <= '1', '0' after clockPeriod; + -- wait for SDRAM ready + wait for 196.1 us - now; + -- read back from address 000010 + ramAddr_int <= 16#000010#; + ramRd <= '1', '0' after clockPeriod; +-- -- wait for SDRAM ready +-- wait for 130 us; +-- -- write AAAA at address 000010 +-- ramAddr_int <= 16#000010#; +-- ramDataOut_int <= 16#AAAA#; +-- ramWr <= '1', '0' after clockPeriod; +-- -- read back from same address +-- wait for 10*clockPeriod; +-- ramRd <= '1', '0' after clockPeriod; +-- -- wait for a refresh +-- wait for 140.3 us - now; +-- -- write 5555 at address 600010 +-- ramAddr_int <= 16#600020#; +-- ramDataOut_int <= 16#5555#; +-- ramWr <= '1', '0' after clockPeriod; +-- -- read back from same address +-- wait for 1*clockPeriod; +-- ramRd <= '1', '0' after clockPeriod; +-- -- read back from address 600010 +-- addr_from_up_int <= 16#600010#; +-- mem_read <= '1', '0' after clockPeriod; +-- wait for 10*clockPeriod; +-- -- wait for 3 refresh periods +-- wait until falling_edge(dram_busy); +-- wait until falling_edge(dram_busy); +-- wait until falling_edge(dram_busy); +-- -- read back from address 000010 +-- addr_from_up_int <= 16#000010#; +-- mem_read <= '1', '0' after clockPeriod; +-- wait for 10*clockPeriod; + -- end of tests + wait; + end process; + + ------------------------------------------------------------------------------ + -- address and data + ramAddr <= to_unsigned(ramAddr_int, ramAddr'length); + ramDataOut <= std_ulogic_vector(to_unsigned(ramDataOut_int, ramDataOut'length)); + +END ARCHITECTURE test; + diff --git a/Libs/Memory_test/hdl/sdram_mt48lc16m16a2_sim.vhd b/Libs/Memory_test/hdl/sdram_mt48lc16m16a2_sim.vhd new file mode 100644 index 0000000..a31c3fd --- /dev/null +++ b/Libs/Memory_test/hdl/sdram_mt48lc16m16a2_sim.vhd @@ -0,0 +1,1363 @@ +----------------------------------------------------------------------------------------- +-- +-- File Name: MT48LC16M16A2.VHD +-- Version: 0.0g +-- Date: June 29th, 2000 +-- Model: Behavioral +-- Simulator: Model Technology (PC version 5.3 PE) +-- +-- Dependencies: None +-- +-- Author: Son P. Huynh +-- Email: sphuynh@micron.com +-- Phone: (208) 368-3825 +-- Company: Micron Technology, Inc. +-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks) +-- +-- Description: Micron 256Mb SDRAM +-- +-- Limitation: - Doesn't check for 4096-cycle refresh --' +-- +-- Note: - Set simulator resolution to "ps" accuracy +-- +-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +-- +-- Copyright (c) 1998 Micron Semiconductor Products, Inc. +-- All rights researved +-- +-- Rev Author Phone Date Changes +-- ---- ---------------------------- ---------- ------------------------------------- +-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array +-- Micron Technology Inc. Modify tWR + tRAS timing check +-- +-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto) +-- Micron Technology Inc. Fix tWR = 15 ns (Manual) +-- Fix tRP (Autoprecharge to AutoRefresh) +-- +-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP +-- Micron Technology Inc. Fix tRC check in Load Mode Register +-- +-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model +-- Micron Technology Inc. +-- +----------------------------------------------------------------------------------------- + +--LIBRARY STD; +-- use std.textio.all; +--LIBRARY IEEE; +-- USE IEEE.STD_LOGIC_1164.ALL; +--LIBRARY WORK; +-- USE WORK.MTI_PKG.ALL; +LIBRARY memory_test; + USE memory_test.mti_pkg.all; + +--library grlib; +--use grlib.stdlib.all; +--library gaisler; +--use gaisler.sim.all; + +--ENTITY mt48lc16m16a2 IS +-- GENERIC ( +-- -- Timing Parameters for -75 (PC133) and CAS Latency = 2 +-- tAC : TIME := 6.0 ns; +-- tHZ : TIME := 7.0 ns; +-- tOH : TIME := 2.7 ns; +-- tMRD : INTEGER := 2; -- 2 Clk Cycles +-- tRAS : TIME := 44.0 ns; +-- tRC : TIME := 66.0 ns; +-- tRCD : TIME := 20.0 ns; +-- tRP : TIME := 20.0 ns; +-- tRRD : TIME := 15.0 ns; +-- tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) +-- tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns) +-- +-- tAH : TIME := 0.8 ns; +-- tAS : TIME := 1.5 ns; +-- tCH : TIME := 2.5 ns; +-- tCL : TIME := 2.5 ns; +-- tCK : TIME := 10.0 ns; +-- tDH : TIME := 0.8 ns; +-- tDS : TIME := 1.5 ns; +-- tCKH : TIME := 0.8 ns; +-- tCKS : TIME := 1.5 ns; +-- tCMH : TIME := 0.8 ns; +-- tCMS : TIME := 1.5 ns; +-- +-- addr_bits : INTEGER := 13; +-- data_bits : INTEGER := 16; +-- col_bits : INTEGER := 9; +-- index : INTEGER := 0; +-- fname : string := "sdram.srec" -- File to read from +-- ); +-- PORT ( +-- Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); +-- Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); +-- Ba : IN STD_LOGIC_VECTOR := "00"; +-- Clk : IN STD_LOGIC := '0'; +-- Cke : IN STD_LOGIC := '1'; +-- Cs_n : IN STD_LOGIC := '1'; +-- Ras_n : IN STD_LOGIC := '1'; +-- Cas_n : IN STD_LOGIC := '1'; +-- We_n : IN STD_LOGIC := '1'; +-- Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00" +-- ); +--END mt48lc16m16a2; + +ARCHITECTURE sim OF sdram_mt48lc16m16a2 IS + + TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE); + TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER; + TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME; + TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT; + TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0); + TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0); + TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State; + SIGNAL Operation : State := NOP; + SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0'; + SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0'; + SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0'; + SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0'; + SIGNAL Ras_in, Cas_in, We_in : BIT := '0'; + SIGNAL Write_burst_mode : BIT := '0'; + SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0'; + + -- Checking internal wires + SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000"; + SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000"; + SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0'; + SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00"; + SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + +BEGIN + -- CS# Decode + WITH Cs_n SELECT + Cas_in <= TO_BIT (Cas_n, '1') WHEN '0', + '1' WHEN '1', + '1' WHEN OTHERS; + WITH Cs_n SELECT + Ras_in <= TO_BIT (Ras_n, '1') WHEN '0', + '1' WHEN '1', + '1' WHEN OTHERS; + WITH Cs_n SELECT + We_in <= TO_BIT (We_n, '1') WHEN '0', + '1' WHEN '1', + '1' WHEN OTHERS; + + -- Commands Decode + Active_enable <= NOT(Ras_in) AND Cas_in AND We_in; + Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in; + Burst_term <= Ras_in AND Cas_in AND NOT(We_in); + Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in); + Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in); + Read_enable <= Ras_in AND NOT(Cas_in) AND We_in; + Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in); + + -- Burst Length Decode + Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0)); + Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); + Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); + Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + + -- CAS Latency Decode + Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); + + -- Write Burst Mode + Write_burst_mode <= Mode_reg(9); + + -- RAS Clock for checking tWR and tRP + PROCESS + variable Clk0, Clk1 : integer := 0; + begin + RAS_clk <= '1'; + wait for 0.5 ns; + RAS_clk <= '0'; + wait for 0.5 ns; + if Clk0 > 100 or Clk1 > 100 then + wait; + else + if Clk = '1' and Cke = '1' then + Clk0 := 0; + Clk1 := Clk1 + 1; + elsif Clk = '0' and Cke = '1' then + Clk0 := Clk0 + 1; + Clk1 := 0; + end if; + end if; + END PROCESS; + + -- System Clock + int_clk : PROCESS (Clk) + begin + IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --' + CkeZ <= TO_BIT(Cke, '1'); + END IF; + Sys_clk <= CkeZ AND TO_BIT(Clk, '0'); + END PROCESS; + + state_register : PROCESS + -- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means + -- the location is in use. This will be checked when doing memory DUMP. + TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0); + TYPE ram_pntr IS ACCESS ram_type; + TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr; + VARIABLE Bank0 : ram_stor; + VARIABLE Bank1 : ram_stor; + VARIABLE Bank2 : ram_stor; + VARIABLE Bank3 : ram_stor; + VARIABLE Row_index, Col_index : INTEGER := 0; + VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0'); + + VARIABLE Col_addr : Array4xCBV; + VARIABLE Bank_addr : Array4x2BV; + VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00"; + + VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Burst_counter : INTEGER := 0; + + VARIABLE Command : Array_state; + VARIABLE Bank_precharge : Array4x2BV; + VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns); + VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0); + + VARIABLE Data_in_enable, Data_out_enable : BIT := '0'; + VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0'; + VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0'; + + -- Timing Check + VARIABLE MRD_chk : INTEGER := 0; + VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0); + VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns); + VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns); + VARIABLE RC_chk, RRD_chk : TIME := 0 ns; + VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; + VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; + VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; + + -- Load and Dumb variables + FILE file_load : TEXT open read_mode is fname; -- Data load + FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump + VARIABLE bank_load : bit_vector ( 1 DOWNTO 0); + VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0); + VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0); + VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0); + VARIABLE i, j : INTEGER; + VARIABLE good_load : BOOLEAN; + VARIABLE l : LINE; + variable load : std_logic := '1'; + variable dump : std_logic := '0'; + variable ch : character; + variable rectype : bit_vector(3 downto 0); + variable recaddr : bit_vector(31 downto 0); + variable reclen : bit_vector(7 downto 0); + variable recdata : bit_vector(0 to 16*8-1); + + -- Initialize empty rows + PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS + VARIABLE i, j : INTEGER := 0; + BEGIN + IF Bank = "00" THEN + IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty + Bank0 (Row_index) := NEW ram_type; -- Open new row for access + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros + FOR j IN (data_bits) DOWNTO 0 LOOP + Bank0 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "01" THEN + IF Bank1 (Row_index) = NULL THEN + Bank1 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits) DOWNTO 0 LOOP + Bank1 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "10" THEN + IF Bank2 (Row_index) = NULL THEN + Bank2 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits) DOWNTO 0 LOOP + Bank2 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "11" THEN + IF Bank3 (Row_index) = NULL THEN + Bank3 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits) DOWNTO 0 LOOP + Bank3 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + END IF; + END; + + -- Burst Counter + PROCEDURE Burst_decode IS + VARIABLE Col_int : INTEGER := 0; + VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + BEGIN + -- Advance Burst Counter + Burst_counter := Burst_counter + 1; + + -- Burst Type + IF Mode_reg (3) = '0' THEN + Col_int := TO_INTEGER(Col); + Col_int := Col_int + 1; + TO_BITVECTOR (Col_int, Col_temp); + ELSIF Mode_reg (3) = '1' THEN + TO_BITVECTOR (Burst_counter, Col_vec); + Col_temp (2) := Col_vec (2) XOR Col_brst (2); + Col_temp (1) := Col_vec (1) XOR Col_brst (1); + Col_temp (0) := Col_vec (0) XOR Col_brst (0); + END IF; + + -- Burst Length + IF Burst_length_2 = '1' THEN + Col (0) := Col_temp (0); + ELSIF Burst_length_4 = '1' THEN + Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0); + ELSIF Burst_length_8 = '1' THEN + Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0); + ELSE + Col := Col_temp; + END IF; + + -- Burst Read Single Write + IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Data counter + IF Burst_length_1 = '1' THEN + IF Burst_counter >= 1 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_2 = '1' THEN + IF Burst_counter >= 2 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_4 = '1' THEN + IF Burst_counter >= 4 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_8 = '1' THEN + IF Burst_counter >= 8 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + END IF; + END; + + BEGIN + WAIT ON Sys_clk, RAS_clk; + IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --' + -- Internal Command Pipeline + Command(0) := Command(1); + Command(1) := Command(2); + Command(2) := Command(3); + Command(3) := NOP; + + Col_addr(0) := Col_addr(1); + Col_addr(1) := Col_addr(2); + Col_addr(2) := Col_addr(3); + Col_addr(3) := (OTHERS => '0'); + + Bank_addr(0) := Bank_addr(1); + Bank_addr(1) := Bank_addr(2); + Bank_addr(2) := Bank_addr(3); + Bank_addr(3) := "00"; + + Bank_precharge(0) := Bank_precharge(1); + Bank_precharge(1) := Bank_precharge(2); + Bank_precharge(2) := Bank_precharge(3); + Bank_precharge(3) := "00"; + + A10_precharge(0) := A10_precharge(1); + A10_precharge(1) := A10_precharge(2); + A10_precharge(2) := A10_precharge(3); + A10_precharge(3) := '0'; + + -- Operation Decode (Optional for showing current command on posedge clock / debug feature) + IF Active_enable = '1' THEN + Operation <= ACT; + ELSIF Aref_enable = '1' THEN + Operation <= A_REF; + ELSIF Burst_term = '1' THEN + Operation <= BST; + ELSIF Mode_reg_enable = '1' THEN + Operation <= LMR; + ELSIF Prech_enable = '1' THEN + Operation <= PRECH; + ELSIF Read_enable = '1' THEN + IF Addr(10) = '0' THEN + Operation <= READ; + ELSE + Operation <= READ_A; + END IF; + ELSIF Write_enable = '1' THEN + IF Addr(10) = '0' THEN + Operation <= WRITE; + ELSE + Operation <= WRITE_A; + END IF; + ELSE + Operation <= NOP; + END IF; + + -- Dqm pipeline for Read + Dqm_reg0 := Dqm_reg1; + Dqm_reg1 := TO_BITVECTOR(Dqm); + + -- Read or Write with Auto Precharge Counter + IF Auto_precharge (0) = '1' THEN + Count_precharge (0) := Count_precharge (0) + 1; + END IF; + IF Auto_precharge (1) = '1' THEN + Count_precharge (1) := Count_precharge (1) + 1; + END IF; + IF Auto_precharge (2) = '1' THEN + Count_precharge (2) := Count_precharge (2) + 1; + END IF; + IF Auto_precharge (3) = '1' THEN + Count_precharge (3) := Count_precharge (3) + 1; + END IF; + + -- Auto Precharge Timer for tWR + if (Burst_length_1 = '1' OR Write_burst_mode = '1') then + if (Count_precharge(0) = 1) then + Count_time(0) := NOW; + end if; + if (Count_precharge(1) = 1) then + Count_time(1) := NOW; + end if; + if (Count_precharge(2) = 1) then + Count_time(2) := NOW; + end if; + if (Count_precharge(3) = 1) then + Count_time(3) := NOW; + end if; + elsif (Burst_length_2 = '1') then + if (Count_precharge(0) = 2) then + Count_time(0) := NOW; + end if; + if (Count_precharge(1) = 2) then + Count_time(1) := NOW; + end if; + if (Count_precharge(2) = 2) then + Count_time(2) := NOW; + end if; + if (Count_precharge(3) = 2) then + Count_time(3) := NOW; + end if; + elsif (Burst_length_4 = '1') then + if (Count_precharge(0) = 4) then + Count_time(0) := NOW; + end if; + if (Count_precharge(1) = 4) then + Count_time(1) := NOW; + end if; + if (Count_precharge(2) = 4) then + Count_time(2) := NOW; + end if; + if (Count_precharge(3) = 4) then + Count_time(3) := NOW; + end if; + elsif (Burst_length_8 = '1') then + if (Count_precharge(0) = 8) then + Count_time(0) := NOW; + end if; + if (Count_precharge(1) = 8) then + Count_time(1) := NOW; + end if; + if (Count_precharge(2) = 8) then + Count_time(2) := NOW; + end if; + if (Count_precharge(3) = 8) then + Count_time(3) := NOW; + end if; + end if; + + -- tMRD Counter + MRD_chk := MRD_chk + 1; + + -- tWR Counter + WR_counter(0) := WR_counter(0) + 1; + WR_counter(1) := WR_counter(1) + 1; + WR_counter(2) := WR_counter(2) + 1; + WR_counter(3) := WR_counter(3) + 1; + + + -- Auto Refresh + IF Aref_enable = '1' THEN + -- Auto Refresh to Auto Refresh + ASSERT (NOW - RC_chk >= tRC) + REPORT "tRC violation during Auto Refresh" + SEVERITY WARNING; + -- Precharge to Auto Refresh + ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Auto Refresh" + SEVERITY WARNING; + -- All banks must be idle before refresh + IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN + ASSERT (FALSE) + REPORT "All banks must be Precharge before Auto Refresh" + SEVERITY WARNING; + END IF; + -- Record current tRC time + RC_chk := NOW; + END IF; + + -- Load Mode Register + IF Mode_reg_enable = '1' THEN + Mode_reg <= TO_BITVECTOR (Addr); + IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN + ASSERT (FALSE) + REPORT "All bank must be Precharge before Load Mode Register" + SEVERITY WARNING; + END IF; + -- REF to LMR + ASSERT (NOW - RC_chk >= tRC) + REPORT "tRC violation during Load Mode Register" + SEVERITY WARNING; + -- LMR to LMR + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Load Mode Register" + SEVERITY WARNING; + -- Record current tMRD time + MRD_chk := 0; + END IF; + + -- Active Block (latch Bank and Row Address) + IF Active_enable = '1' THEN + IF Ba = "00" AND Pc_b0 = '1' THEN + Act_b0 := '1'; + Pc_b0 := '0'; + B0_row_addr := TO_BITVECTOR (Addr); + RCD_chk0 := NOW; + RAS_chk0 := NOW; + -- Precharge to Active Bank 0 + ASSERT (NOW - RP_chk0 >= tRP) + REPORT "tRP violation during Activate Bank 0" + SEVERITY WARNING; + ELSIF Ba = "01" AND Pc_b1 = '1' THEN + Act_b1 := '1'; + Pc_b1 := '0'; + B1_row_addr := TO_BITVECTOR (Addr); + RCD_chk1 := NOW; + RAS_chk1 := NOW; + -- Precharge to Active Bank 1 + ASSERT (NOW - RP_chk1 >= tRP) + REPORT "tRP violation during Activate Bank 1" + SEVERITY WARNING; + ELSIF Ba = "10" AND Pc_b2 = '1' THEN + Act_b2 := '1'; + Pc_b2 := '0'; + B2_row_addr := TO_BITVECTOR (Addr); + RCD_chk2 := NOW; + RAS_chk2 := NOW; + -- Precharge to Active Bank 2 + ASSERT (NOW - RP_chk2 >= tRP) + REPORT "tRP violation during Activate Bank 2" + SEVERITY WARNING; + ELSIF Ba = "11" AND Pc_b3 = '1' THEN + Act_b3 := '1'; + Pc_b3 := '0'; + B3_row_addr := TO_BITVECTOR (Addr); + RCD_chk3 := NOW; + RAS_chk3 := NOW; + -- Precharge to Active Bank 3 + ASSERT (NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Activate Bank 3" + SEVERITY WARNING; + ELSIF Ba = "00" AND Pc_b0 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 0 is not Precharged" + SEVERITY WARNING; + ELSIF Ba = "01" AND Pc_b1 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 1 is not Precharged" + SEVERITY WARNING; + ELSIF Ba = "10" AND Pc_b2 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 2 is not Precharged" + SEVERITY WARNING; + ELSIF Ba = "11" AND Pc_b3 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 3 is not Precharged" + SEVERITY WARNING; + END IF; + -- Active Bank A to Active Bank B + IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN + ASSERT (FALSE) + REPORT "tRRD violation during Activate" + SEVERITY WARNING; + END IF; + -- LMR to ACT + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Activate" + SEVERITY WARNING; + -- AutoRefresh to Activate + ASSERT (NOW - RC_chk >= tRC) + REPORT "tRC violation during Activate" + SEVERITY WARNING; + -- Record variable for checking violation + RRD_chk := NOW; + Previous_bank := TO_BITVECTOR (Ba); + END IF; + + -- Precharge Block + IF Prech_enable = '1' THEN + IF Addr(10) = '1' THEN + Pc_b0 := '1'; + Pc_b1 := '1'; + Pc_b2 := '1'; + Pc_b3 := '1'; + Act_b0 := '0'; + Act_b1 := '0'; + Act_b2 := '0'; + Act_b3 := '0'; + RP_chk0 := NOW; + RP_chk1 := NOW; + RP_chk2 := NOW; + RP_chk3 := NOW; + -- Activate to Precharge all banks + ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS)) + REPORT "tRAS violation during Precharge all banks" + SEVERITY WARNING; + -- tWR violation check for Write + IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR + (NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN + ASSERT (FALSE) + REPORT "tWR violation during Precharge ALL banks" + SEVERITY WARNING; + END IF; + ELSIF Addr(10) = '0' THEN + IF Ba = "00" THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + -- Activate to Precharge bank 0 + ASSERT (NOW - RAS_chk0 >= tRAS) + REPORT "tRAS violation during Precharge bank 0" + SEVERITY WARNING; + ELSIF Ba = "01" THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + -- Activate to Precharge bank 1 + ASSERT (NOW - RAS_chk1 >= tRAS) + REPORT "tRAS violation during Precharge bank 1" + SEVERITY WARNING; + ELSIF Ba = "10" THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + -- Activate to Precharge bank 2 + ASSERT (NOW - RAS_chk2 >= tRAS) + REPORT "tRAS violation during Precharge bank 2" + SEVERITY WARNING; + ELSIF Ba = "11" THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + -- Activate to Precharge bank 3 + ASSERT (NOW - RAS_chk3 >= tRAS) + REPORT "tRAS violation during Precharge bank 3" + SEVERITY WARNING; + END IF; + -- tWR violation check for Write + ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + -- Terminate a Write Immediately (if same bank or all banks) + IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN + Data_in_enable := '0'; + END IF; + -- Precharge Command Pipeline for READ + IF CAS_latency_3 = '1' THEN + Command(2) := PRECH; + Bank_precharge(2) := TO_BITVECTOR (Ba); + A10_precharge(2) := TO_BIT(Addr(10)); + ELSIF CAS_latency_2 = '1' THEN + Command(1) := PRECH; + Bank_precharge(1) := TO_BITVECTOR (Ba); + A10_precharge(1) := TO_BIT(Addr(10)); + END IF; + END IF; + + -- Burst Terminate + IF Burst_term = '1' THEN + -- Terminate a Write immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + -- Terminate a Read depend on CAS Latency + IF CAS_latency_3 = '1' THEN + Command(2) := BST; + ELSIF CAS_latency_2 = '1' THEN + Command(1) := BST; + END IF; + END IF; + + -- Read, Write, Column Latch + IF Read_enable = '1' OR Write_enable = '1' THEN + -- Check to see if bank is open (ACT) for Read or Write + IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN + ASSERT (FALSE) + REPORT "Cannot Read or Write - Bank is not Activated" + SEVERITY WARNING; + END IF; + -- Activate to Read or Write + IF Ba = "00" THEN + ASSERT (NOW - RCD_chk0 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 0" + SEVERITY WARNING; + ELSIF Ba = "01" THEN + ASSERT (NOW - RCD_chk1 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 1" + SEVERITY WARNING; + ELSIF Ba = "10" THEN + ASSERT (NOW - RCD_chk2 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 2" + SEVERITY WARNING; + ELSIF Ba = "11" THEN + ASSERT (NOW - RCD_chk3 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 3" + SEVERITY WARNING; + END IF; + + -- Read Command + IF Read_enable = '1' THEN + -- CAS Latency Pipeline + IF Cas_latency_3 = '1' THEN + IF Addr(10) = '1' THEN + Command(2) := READ_A; + ELSE + Command(2) := READ; + END IF; + Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0)); + Bank_addr (2) := TO_BITVECTOR (Ba); + ELSIF Cas_latency_2 = '1' THEN + IF Addr(10) = '1' THEN + Command(1) := READ_A; + ELSE + Command(1) := READ; + END IF; + Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0)); + Bank_addr (1) := TO_BITVECTOR (Ba); + END IF; + + -- Read intterupt a Write (terminate Write immediately) + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Write Command + ELSIF Write_enable = '1' THEN + IF Addr(10) = '1' THEN + Command(0) := WRITE_A; + ELSE + Command(0) := WRITE; + END IF; + Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0)); + Bank_addr (0) := TO_BITVECTOR (Ba); + + -- Write intterupt a Write (terminate Write immediately) + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Write interrupt a Read (terminate Read immediately) + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + + -- Interrupt a Write with Auto Precharge + IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1'; + END IF; + + -- Interrupt a Read with Auto Precharge + IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1'; + END IF; + + -- Read or Write with Auto Precharge + IF Addr(10) = '1' THEN + Auto_precharge (TO_INTEGER(Ba)) := '1'; + Count_precharge (TO_INTEGER(Ba)) := 0; + RW_Interrupt_Bank := TO_BitVector(Ba); + IF Read_enable = '1' THEN + Read_precharge (TO_INTEGER(Ba)) := '1'; + ELSIF Write_enable = '1' THEN + Write_precharge (TO_INTEGER(Ba)) := '1'; + END IF; + END IF; + END IF; + + -- Read with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. BL/2 cycles after command + -- and 2. Meet tRAS requirement + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR + (RW_interrupt_read(0) = '1')) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + Auto_precharge(0) := '0'; + Read_precharge(0) := '0'; + RW_interrupt_read(0) := '0'; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR + (RW_interrupt_read(1) = '1')) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + Auto_precharge(1) := '0'; + Read_precharge(1) := '0'; + RW_interrupt_read(1) := '0'; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR + (RW_interrupt_read(2) = '1')) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + Auto_precharge(2) := '0'; + Read_precharge(2) := '0'; + RW_interrupt_read(2) := '0'; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR + (RW_interrupt_read(3) = '1')) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + Auto_precharge(3) := '0'; + Read_precharge(3) := '0'; + RW_interrupt_read(3) := '0'; + END IF; + END IF; + + -- Internal Precharge or Bst + IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks + IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + + IF Data_out_enable = '0' THEN + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH; + END IF; + + -- Detect Read or Write Command + IF Command(0) = READ OR Command(0) = READ_A THEN + Bank := Bank_addr (0); + Col := Col_addr (0); + Col_brst := Col_addr (0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '0'; + Data_out_enable := '1'; + ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN + Bank := Bank_addr(0); + Col := Col_addr(0); + Col_brst := Col_addr(0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '1'; + Data_out_enable := '0'; + END IF; + + -- DQ (Driver / Receiver) + Row_index := TO_INTEGER (Row); + Col_index := TO_INTEGER (Col); + IF Data_in_enable = '1' THEN + IF Dqm /= "11" THEN + Init_mem (Bank, Row_index); + IF Bank = "00" THEN + Dq_temp := Bank0 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0)); + ELSIF Bank = "01" THEN + Dq_temp := Bank1 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0)); + ELSIF Bank = "10" THEN + Dq_temp := Bank2 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0)); + ELSIF Bank = "11" THEN + Dq_temp := Bank3 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0)); + END IF; + WR_chkp(TO_INTEGER(Bank)) := NOW; + WR_counter(TO_INTEGER(Bank)) := 0; + END IF; + Burst_decode; + ELSIF Data_out_enable = '1' THEN + IF Dqm_reg0 /= "11" THEN + Init_mem (Bank, Row_index); + IF Bank = "00" THEN + Dq_temp := Bank0 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + ELSIF Bank = "01" THEN + Dq_temp := Bank1 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + ELSIF Bank = "10" THEN + Dq_temp := Bank2 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + ELSIF Bank = "11" THEN + Dq_temp := Bank3 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + END IF; + ELSE + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ; + END IF; + Burst_decode; + END IF; + ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --' + Operation <= LOAD_FILE; + load := '0'; +-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..." +-- SEVERITY NOTE; + WHILE NOT endfile(file_load) LOOP + readline(file_load, l); + read(l, ch); + if (ch /= 'S') or (ch /= 's') then + hexread(l, rectype); + hexread(l, reclen); + recaddr := (others => '0'); + case rectype is + when "0001" => + hexread(l, recaddr(15 downto 0)); + when "0010" => + hexread(l, recaddr(23 downto 0)); + when "0011" => + hexread(l, recaddr); + recaddr(31 downto 24) := (others => '0'); + when others => next; + end case; + if true then + hexread(l, recdata); + Bank_Load := recaddr(25 downto 24); + Rows_Load := recaddr(23 downto 11); + Cols_Load := recaddr(10 downto 2); + Init_Mem (Bank_Load, To_Integer(Rows_Load)); + + IF Bank_Load = "00" THEN + for i in 0 to 3 loop + Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15)); + end loop; + ELSIF Bank_Load = "01" THEN + for i in 0 to 3 loop + Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15)); + end loop; + ELSIF Bank_Load = "10" THEN + for i in 0 to 3 loop + Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15)); + end loop; + ELSIF Bank_Load = "11" THEN + for i in 0 to 3 loop + Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15)); + end loop; + END IF; + + END IF; + END IF; + END LOOP; + ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --' + Operation <= DUMP_FILE; + ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..." + SEVERITY NOTE; + WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --' + WRITELINE (file_dump, l); + WRITE (l, string'("# BA ROWS COLS DQ")); --' + WRITELINE (file_dump, l); + WRITE (l, string'("# -- ------------- --------- ----------------")); --' + WRITELINE (file_dump, l); + -- Dumping Bank 0 + FOR i IN 0 TO 2**addr_bits -1 LOOP + -- Check if ROW is NULL + IF Bank0 (i) /= NULL THEN + For j IN 0 TO 2**col_bits - 1 LOOP + -- Check if COL is NULL + NEXT WHEN Bank0 (i) (j) (data_bits) = '0'; + WRITE (l, string'("00"), right, 4); --' + WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1); + WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1); + WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1); + WRITELINE (file_dump, l); + END LOOP; + END IF; + END LOOP; + -- Dumping Bank 1 + FOR i IN 0 TO 2**addr_bits -1 LOOP + -- Check if ROW is NULL + IF Bank1 (i) /= NULL THEN + For j IN 0 TO 2**col_bits - 1 LOOP + -- Check if COL is NULL + NEXT WHEN Bank1 (i) (j) (data_bits) = '0'; + WRITE (l, string'("01"), right, 4); --' + WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1); + WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1); + WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1); + WRITELINE (file_dump, l); + END LOOP; + END IF; + END LOOP; + -- Dumping Bank 2 + FOR i IN 0 TO 2**addr_bits -1 LOOP + -- Check if ROW is NULL + IF Bank2 (i) /= NULL THEN + For j IN 0 TO 2**col_bits - 1 LOOP + -- Check if COL is NULL + NEXT WHEN Bank2 (i) (j) (data_bits) = '0'; + WRITE (l, string'("10"), right, 4); --' + WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1); + WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1); + WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1); + WRITELINE (file_dump, l); + END LOOP; + END IF; + END LOOP; + -- Dumping Bank 3 + FOR i IN 0 TO 2**addr_bits -1 LOOP + -- Check if ROW is NULL + IF Bank3 (i) /= NULL THEN + For j IN 0 TO 2**col_bits - 1 LOOP + -- Check if COL is NULL + NEXT WHEN Bank3 (i) (j) (data_bits) = '0'; + WRITE (l, string'("11"), right, 4); --' + WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1); + WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1); + WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1); + WRITELINE (file_dump, l); + END LOOP; + END IF; + END LOOP; + END IF; + + -- Write with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. tWR cycles after command + -- and 2. Meet tRAS requirement + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR + (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN + Auto_precharge(0) := '0'; + Write_precharge(0) := '0'; + RW_interrupt_write(0) := '0'; + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR + (RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN + Auto_precharge(1) := '0'; + Write_precharge(1) := '0'; + RW_interrupt_write(1) := '0'; + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR + (RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN + Auto_precharge(2) := '0'; + Write_precharge(2) := '0'; + RW_interrupt_write(2) := '0'; + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR + (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN + Auto_precharge(3) := '0'; + Write_precharge(3) := '0'; + RW_interrupt_write(3) := '0'; + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + END IF; + END IF; + + -- Checking internal wires (Optional for debug purpose) + Pre_chk (0) <= Pc_b0; + Pre_chk (1) <= Pc_b1; + Pre_chk (2) <= Pc_b2; + Pre_chk (3) <= Pc_b3; + Act_chk (0) <= Act_b0; + Act_chk (1) <= Act_b1; + Act_chk (2) <= Act_b2; + Act_chk (3) <= Act_b3; + Dq_in_chk <= Data_in_enable; + Dq_out_chk <= Data_out_enable; + Bank_chk <= Bank; + Row_chk <= Row; + Col_chk <= Col; + END PROCESS; + + + -- Clock timing checks +-- Clock_check : PROCESS +-- VARIABLE Clk_low, Clk_high : TIME := 0 ns; +-- BEGIN +-- WAIT ON Clk; +-- IF (Clk = '1' AND NOW >= 10 ns) THEN +-- ASSERT (NOW - Clk_low >= tCL) +-- REPORT "tCL violation" +-- SEVERITY WARNING; +-- ASSERT (NOW - Clk_high >= tCK) +-- REPORT "tCK violation" +-- SEVERITY WARNING; +-- Clk_high := NOW; +-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN +-- ASSERT (NOW - Clk_high >= tCH) +-- REPORT "tCH violation" +-- SEVERITY WARNING; +-- Clk_low := NOW; +-- END IF; +-- END PROCESS; + + -- Setup timing checks + Setup_check : PROCESS + BEGIN + wait; + WAIT ON Clk; + IF Clk = '1' THEN + ASSERT(Cke'LAST_EVENT >= tCKS) --' + REPORT "CKE Setup time violation -- tCKS" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tCMS) --' + REPORT "CS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tCMS) --' + REPORT "CAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tCMS) --' + REPORT "RAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tCMS) --' + REPORT "WE# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT >= tCMS) --' + REPORT "Dqm Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tAS) --' + REPORT "ADDR Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tAS) --' + REPORT "BA Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Dq'LAST_EVENT >= tDS) --' + REPORT "Dq Setup time violation -- tDS" + SEVERITY WARNING; + END IF; + END PROCESS; + + -- Hold timing checks + Hold_check : PROCESS + BEGIN + wait; + WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH); + IF Clk'DELAYED (tCKH) = '1' THEN --' + ASSERT(Cke'LAST_EVENT > tCKH) --' + REPORT "CKE Hold time violation -- tCKH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tCMH) = '1' THEN --' + ASSERT(Cs_n'LAST_EVENT > tCMH) --' + REPORT "CS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT > tCMH) --' + REPORT "CAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT > tCMH) --' + REPORT "RAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT > tCMH) --' + REPORT "WE# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT > tCMH) --' + REPORT "Dqm Hold time violation -- tCMH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tAH) = '1' THEN --' + ASSERT(Addr'LAST_EVENT > tAH) --' + REPORT "ADDR Hold time violation -- tAH" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT > tAH) --' + REPORT "BA Hold time violation -- tAH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tDH) = '1' THEN --' + ASSERT(Dq'LAST_EVENT > tDH) --' + REPORT "Dq Hold time violation -- tDH" + SEVERITY WARNING; + END IF; + END PROCESS; + +END ARCHITECTURE sim; + diff --git a/Libs/Memory_test/hds/.hdlsidedata/_Flash_behav.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_Flash_behav.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_Flash_behav.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_bram_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_bram_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_bram_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_fifo_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_fifo_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_fifo_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_flashController_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_flashController_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_flashController_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_flash_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_flash_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_flash_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg.vhd._fpf new file mode 100644 index 0000000..5732f99 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_93 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg_body.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg_body.vhd._fpf new file mode 100644 index 0000000..5732f99 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg_body.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_93 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_sdramController_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_sdramController_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_sdramController_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_sdram_mt48lc16m16a2_sim.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_sdram_mt48lc16m16a2_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_sdram_mt48lc16m16a2_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/_bram_tb._epf b/Libs/Memory_test/hds/_bram_tb._epf new file mode 100644 index 0000000..174551f --- /dev/null +++ b/Libs/Memory_test/hds/_bram_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom bram_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_bram_tester._epf b/Libs/Memory_test/hds/_bram_tester._epf new file mode 100644 index 0000000..559360f --- /dev/null +++ b/Libs/Memory_test/hds/_bram_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom bram_tester_test.vhd diff --git a/Libs/Memory_test/hds/_fifo_tb._epf b/Libs/Memory_test/hds/_fifo_tb._epf new file mode 100644 index 0000000..1b086f1 --- /dev/null +++ b/Libs/Memory_test/hds/_fifo_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom fifo_tb/struct.bd +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_flash_28f128j3a._epf b/Libs/Memory_test/hds/_flash_28f128j3a._epf new file mode 100644 index 0000000..ef7aef2 --- /dev/null +++ b/Libs/Memory_test/hds/_flash_28f128j3a._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom Flash_behav.vhd +DEFAULT_ARCHITECTURE atom behav diff --git a/Libs/Memory_test/hds/_flash_tb._epf b/Libs/Memory_test/hds/_flash_tb._epf new file mode 100644 index 0000000..99c6d2b --- /dev/null +++ b/Libs/Memory_test/hds/_flash_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom flash_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_flash_tester._epf b/Libs/Memory_test/hds/_flash_tester._epf new file mode 100644 index 0000000..a7aa7e2 --- /dev/null +++ b/Libs/Memory_test/hds/_flash_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom flash_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Memory_test/hds/_flashcontroller_tb._epf b/Libs/Memory_test/hds/_flashcontroller_tb._epf new file mode 100644 index 0000000..3f59750 --- /dev/null +++ b/Libs/Memory_test/hds/_flashcontroller_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom flash@controller_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_flashcontroller_tester._epf b/Libs/Memory_test/hds/_flashcontroller_tester._epf new file mode 100644 index 0000000..d81ef79 --- /dev/null +++ b/Libs/Memory_test/hds/_flashcontroller_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom flashController_tester_test.vhd diff --git a/Libs/Memory_test/hds/_sdramcontroller_tb._epf b/Libs/Memory_test/hds/_sdramcontroller_tb._epf new file mode 100644 index 0000000..318858b --- /dev/null +++ b/Libs/Memory_test/hds/_sdramcontroller_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom sdram@controller_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_sdramcontroller_tester._epf b/Libs/Memory_test/hds/_sdramcontroller_tester._epf new file mode 100644 index 0000000..cd1908b --- /dev/null +++ b/Libs/Memory_test/hds/_sdramcontroller_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom sdramController_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Memory_test/hds/bram_tb/struct.bd b/Libs/Memory_test/hds/bram_tb/struct.bd new file mode 100644 index 0000000..cc5de3c --- /dev/null +++ b/Libs/Memory_test/hds/bram_tb/struct.bd @@ -0,0 +1,3661 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I1" +duLibraryName "memory_test" +duName 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a/Libs/Memory_test/hds/fifo_tb/struct.bd.info/msimSimulationReplay.sh b/Libs/Memory_test/hds/fifo_tb/struct.bd.info/msimSimulationReplay.sh new file mode 100644 index 0000000..c211a82 --- /dev/null +++ b/Libs/Memory_test/hds/fifo_tb/struct.bd.info/msimSimulationReplay.sh @@ -0,0 +1,3 @@ +# Script to replay the last simulation run +cd $HDS_PROJECT_DIR\..\Memory_test\work +"C:/eda/mentor/questasim64_10.1b/win64/vsim" -f hds_args.tmp diff --git a/Libs/Memory_test/hds/fifo_tb/symbol.sb b/Libs/Memory_test/hds/fifo_tb/symbol.sb new file mode 100644 index 0000000..33e507e --- /dev/null +++ b/Libs/Memory_test/hds/fifo_tb/symbol.sb @@ -0,0 +1,1256 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2001,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 107,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 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\"U:\\ELN_board\\Simulation\\sdram.srec\" ( string ) +tAC = 6 ns ( time ) +tHZ = 7 ns ( time ) +tOH = 2.7 ns ( time ) +tMRD = 2 ( integer ) +tRAS = 44 ns ( time ) +tRC = 66 ns ( time ) +tRCD = 20 ns ( time ) +tRP = 20 ns ( time ) +tRRD = 15 ns ( time ) +tWRa = 7.5 ns ( time ) +tWRp = 15 ns ( time ) +tAH = 0.8 ns ( time ) +tAS = 1.5 ns ( time ) +tCH = 2.5 ns ( time ) +tCL = 2.5 ns ( time ) +tCK = 10 ns ( time ) +tDH = 0.8 ns ( time ) +tDS = 1.5 ns ( time ) +tCKH = 0.8 ns ( time ) +tCKS = 1.5 ns ( time ) +tCMH = 0.8 ns ( time ) +tCMS = 1.5 ns ( time ) " +) +header "" +) +elements [ +(GiElement +name "addr_bits" +type "integer" +value "rowAddressBitNb" +) +(GiElement +name "data_bits" +type "integer" +value "dataBitNb" +) +(GiElement +name "col_bits" +type "integer" +value "colAddressBitNb" +) +(GiElement +name "index" +type "integer" +value "0" +) +(GiElement +name "fname" +type "string" +value "\"U:\\ELN_board\\Simulation\\sdram.srec\"" +) +(GiElement +name "tAC" +type "time" +value "6 ns" +) +(GiElement +name "tHZ" +type "time" +value "7 ns" +) +(GiElement +name "tOH" +type "time" +value "2.7 ns" +) +(GiElement +name "tMRD" +type "integer" +value "2" +) +(GiElement +name "tRAS" +type "time" +value "44 ns" +) +(GiElement +name "tRC" +type "time" +value "66 ns" +) +(GiElement +name "tRCD" +type "time" +value "20 ns" +) +(GiElement +name "tRP" +type "time" +value "20 ns" +) +(GiElement +name "tRRD" +type "time" +value "15 ns" +) +(GiElement +name "tWRa" +type "time" +value "7.5 ns" +) +(GiElement +name "tWRp" +type "time" +value "15 ns" +) +(GiElement +name "tAH" +type "time" +value "0.8 ns" +) +(GiElement +name "tAS" +type "time" +value "1.5 ns" +) +(GiElement +name "tCH" +type "time" +value "2.5 ns" +) +(GiElement +name "tCL" +type "time" +value "2.5 ns" +) +(GiElement +name "tCK" +type "time" +value "10 ns" +) +(GiElement +name "tDH" +type "time" +value "0.8 ns" +) +(GiElement +name "tDS" +type "time" +value "1.5 ns" +) +(GiElement +name "tCKH" +type "time" +value "0.8 ns" +) +(GiElement +name "tCKS" +type "time" +value "1.5 ns" +) +(GiElement +name "tCMH" +type "time" +value "0.8 ns" +) +(GiElement +name "tCMS" +type "time" +value "1.5 ns" +) +] +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*43 (Net +uid 5992,0 +decl (Decl +n "sdClk" +t "std_ulogic" +o 20 +suid 68,0 +) +declText (MLText +uid 5993,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdClk : std_ulogic" +) +) +*44 (Net +uid 5998,0 +decl (Decl +n "sdCke" +t "std_ulogic" +o 19 +suid 69,0 +) +declText (MLText +uid 5999,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdCke : std_ulogic" +) +) +*45 (Net +uid 6004,0 +decl (Decl +n "sdDqm" +t "std_ulogic_vector" +b "( 1 DOWNTO 0 )" +o 22 +suid 70,0 +) +declText (MLText +uid 6005,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,126000,1100" +st "SIGNAL sdDqm : std_ulogic_vector( 1 DOWNTO 0 )" +) +) +*46 (Net +uid 6010,0 +decl (Decl +n "memWr_n" +t "std_ulogic" +o 9 +suid 71,0 +) +declText (MLText +uid 6011,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL memWr_n : std_ulogic" +) +) +*47 (Net +uid 6016,0 +decl (Decl +n "sdCas_n" +t "std_ulogic" +o 18 +suid 72,0 +) +declText (MLText +uid 6017,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdCas_n : std_ulogic" +) +) +*48 (Net +uid 6022,0 +decl (Decl +n "sdRas_n" +t "std_ulogic" +o 23 +suid 73,0 +) +declText (MLText +uid 6023,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdRas_n : std_ulogic" +) +) +*49 (Net +uid 6028,0 +decl (Decl +n "sdCs_n" +t "std_ulogic" +o 21 +suid 74,0 +) +declText (MLText +uid 6029,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdCs_n : std_ulogic" +) +) +*50 (Net +uid 6048,0 +decl (Decl +n "DQ" +t "std_logic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 1 +suid 75,0 +) +declText (MLText +uid 6049,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,129500,1100" +st "SIGNAL DQ : std_logic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*51 (HdlText +uid 6058,0 +optionalChildren [ +*52 (EmbeddedText +uid 6063,0 +commentText (CommentText +uid 6064,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6065,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "73000,31000,89000,39000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6066,0 +va (VaSet +font "courier,9,0" +) +xt "73200,31200,89200,35700" +st " +memDataIn <= std_ulogic_vector(DQ); +DQ <= std_logic_vector(memDataOut) when memWr_n = '0' + else (others => 'Z'); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 8000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 6059,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "73000,30000,89000,40000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6060,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*53 (Text +uid 6061,0 +va (VaSet +) +xt "73400,40000,74600,41000" +st "eb1" +blo "73400,40800" +tm "HdlTextNameMgr" +) +*54 (Text +uid 6062,0 +va (VaSet +) +xt "73400,41000,73800,42000" +st "1" +blo "73400,41800" +tm "HdlTextNumberMgr" +) +] +) +) +*55 (HdlText +uid 6138,0 +optionalChildren [ +*56 (EmbeddedText +uid 6143,0 +commentText (CommentText +uid 6144,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6145,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "128000,62000,170000,86000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6146,0 +va (VaSet +font "courier,9,0" +) +xt "128200,62200,168200,79300" +st " +commandBus <= (sdCs_n, sdRas_n, sdCas_n, memWr_n, sdDqm(1), sdDqm(0)); + + ----------------------------------------------------------------------------- + -- debug information + commandDecode: process(commandBus) + begin + case commandBus is + when inhibit => commandString <= \"inhibit \"; + when nop => commandString <= \"nop \"; + when active => commandString <= \"active \"; + when read => commandString <= \"read \"; + when write => commandString <= \"write \"; + when burstTerminate => commandString <= \"burstTerminate \"; + when precharge => commandString <= \"precharge \"; + when autoRefresh => commandString <= \"autoRefresh \"; + when loadModeReg => commandString <= \"loadModeReg \"; + when others => commandString <= \"XXXXXXXXXXXXXXXX\"; + end case; + end process commandDecode; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 24000 +visibleWidth 42000 +) +) +) +] +shape (Rectangle +uid 6139,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "128000,61000,170000,87000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6140,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*57 (Text +uid 6141,0 +va (VaSet +) +xt "128200,87000,129800,88000" +st "eb2" +blo "128200,87800" +tm "HdlTextNameMgr" +) +*58 (Text +uid 6142,0 +va (VaSet +) +xt "128200,88000,129000,89000" +st "2" +blo "128200,88800" +tm "HdlTextNumberMgr" +) +] +) +) +*59 (Net +uid 6195,0 +decl (Decl +n "commandBus" +t "commandBusType" +o 3 +suid 76,0 +) +declText (MLText +uid 6196,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,117500,1100" +st "SIGNAL commandBus : commandBusType" +) +) +*60 (Net +uid 6207,0 +decl (Decl +n "commandString" +t "string" +b "(1 TO 16)" +o 4 +suid 78,0 +) +declText (MLText +uid 6208,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,118000,1100" +st "SIGNAL commandString : string(1 TO 16)" +) +) +*61 (SaComponent +uid 6647,0 +optionalChildren [ +*62 (CptPort +uid 6563,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6564,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,53625,25000,54375" +) +tg (CPTG +uid 6565,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6566,0 +va (VaSet +) +xt "26000,53500,28100,54500" +st "clock" +blo "26000,54300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 20,0 +) +) +) +*63 (CptPort +uid 6567,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6568,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,39625,25000,40375" +) +tg (CPTG +uid 6569,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6570,0 +va (VaSet +) +xt "26000,39500,31400,40500" +st "ramDataValid" +blo "26000,40300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ramDataValid" +t "std_ulogic" +o 14 +suid 21,0 +) +) +) +*64 (CptPort +uid 6571,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6572,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,29625,25000,30375" +) +tg (CPTG +uid 6573,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6574,0 +va (VaSet +) +xt "26000,29500,29300,30500" +st "ramAddr" +blo "26000,30300" +) +) +thePort (LogicalPort +decl (Decl +n "ramAddr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 3 +suid 22,0 +) +) +) +*65 (CptPort +uid 6575,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6576,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,29625,41750,30375" +) +tg (CPTG +uid 6577,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6578,0 +va (VaSet +) +xt "34800,29500,40000,30500" +st "memAddress" +ju 2 +blo "40000,30300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memAddress" +t "std_ulogic_vector" +b "( chipAddressBitNb-1 DOWNTO 0 )" +o 9 +suid 23,0 +) +) +) +*66 (CptPort +uid 6579,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6580,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,33625,25000,34375" +) +tg (CPTG +uid 6581,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6582,0 +va (VaSet +) +xt "26000,33500,30900,34500" +st "ramDataOut" +blo "26000,34300" +) +) +thePort (LogicalPort +decl (Decl +n "ramDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 24,0 +) +) +) +*67 (CptPort +uid 6583,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6584,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,33625,41750,34375" +) +tg (CPTG +uid 6585,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6586,0 +va (VaSet +) +xt "35800,33500,40000,34500" +st "memDataIn" +ju 2 +blo "40000,34300" +) +) +thePort (LogicalPort +decl (Decl +n "memDataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 2 +suid 25,0 +) +) +) +*68 (CptPort +uid 6587,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6588,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,35625,41750,36375" +) +tg (CPTG +uid 6589,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6590,0 +va (VaSet +) +xt "34800,35500,40000,36500" +st "memDataOut" +ju 2 +blo "40000,36300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 11 +suid 26,0 +) +) +) +*69 (CptPort +uid 6591,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6592,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,43625,41750,44375" +) +tg (CPTG +uid 6593,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6594,0 +va (VaSet +) +xt "36200,43500,40000,44500" +st "memWr_n" +ju 2 +blo "40000,44300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memWr_n" +t "std_ulogic" +o 12 +suid 27,0 +) +) +) +*70 (CptPort +uid 6595,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6596,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,51625,25000,52375" +) +tg (CPTG +uid 6597,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6598,0 +va (VaSet +) +xt "26000,51500,28600,52500" +st "ramEn" +blo "26000,52300" +) +) +thePort (LogicalPort +decl (Decl +n "ramEn" +t "std_ulogic" +o 5 +suid 28,0 +) +) +) +*71 (CptPort +uid 6599,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6600,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,35625,25000,36375" +) +tg (CPTG +uid 6601,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6602,0 +va (VaSet +) +xt "26000,35500,28700,36500" +st "ramRd" +blo "26000,36300" +) +) +thePort (LogicalPort +decl (Decl +n "ramRd" +t "std_ulogic" +o 6 +suid 29,0 +) +) +) +*72 (CptPort +uid 6603,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6604,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,37625,25000,38375" +) +tg (CPTG +uid 6605,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6606,0 +va (VaSet +) +xt "26000,37500,28700,38500" +st "ramWr" +blo "26000,38300" +) +) +thePort (LogicalPort +decl (Decl +n "ramWr" +t "std_ulogic" +o 7 +suid 30,0 +) +) +) +*73 (CptPort +uid 6607,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6608,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,55625,25000,56375" +) +tg (CPTG +uid 6609,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6610,0 +va (VaSet +) +xt "26000,55500,28100,56500" +st "reset" +blo "26000,56300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 8 +suid 31,0 +) +) +) +*74 (CptPort +uid 6611,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6612,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,41625,41750,42375" +) +tg (CPTG +uid 6613,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6614,0 +va (VaSet +) +xt "36600,41500,40000,42500" +st "sdCas_n" +ju 2 +blo "40000,42300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCas_n" +t "std_ulogic" +o 15 +suid 32,0 +) +) +) +*75 (CptPort +uid 6615,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6616,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,47625,41750,48375" +) +tg (CPTG +uid 6617,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6618,0 +va (VaSet +) +xt "37500,47500,40000,48500" +st "sdCke" +ju 2 +blo "40000,48300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCke" +t "std_ulogic" +o 16 +suid 33,0 +) +) +) +*76 (CptPort +uid 6619,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6620,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,49625,41750,50375" +) +tg (CPTG +uid 6621,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6622,0 +va (VaSet +) +xt "37700,49500,40000,50500" +st "sdClk" +ju 2 +blo "40000,50300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdClk" +t "std_ulogic" +o 17 +suid 34,0 +) +) +) +*77 (CptPort +uid 6623,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6624,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,37625,41750,38375" +) +tg (CPTG +uid 6625,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6626,0 +va (VaSet +) +xt "37000,37500,40000,38500" +st "sdCs_n" +ju 2 +blo "40000,38300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCs_n" +t "std_ulogic" +o 18 +suid 35,0 +) +) +) +*78 (CptPort +uid 6627,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6628,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,45625,41750,46375" +) +tg (CPTG +uid 6629,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6630,0 +va (VaSet +) +xt "37100,45500,40000,46500" +st "sdDqm" +ju 2 +blo "40000,46300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdDqm" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 19 +suid 36,0 +) +) +) +*79 (CptPort +uid 6631,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6632,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,39625,41750,40375" +) +tg (CPTG +uid 6633,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6634,0 +va (VaSet +) +xt "36600,39500,40000,40500" +st "sdRas_n" +ju 2 +blo "40000,40300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdRas_n" +t "std_ulogic" +o 20 +suid 38,0 +) +) +) +*80 (CptPort +uid 6635,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 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"43750,43600" +tm "WireNameMgr" +) +) +on &46 +) +*104 (Wire +uid 6018,0 +shape (OrthoPolyLine +uid 6019,0 +va (VaSet +vasetType 3 +) +xt "41750,42000,56250,42000" +pts [ +"41750,42000" +"56250,42000" +] +) +start &74 +end &32 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 6020,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6021,0 +va (VaSet +font "courier,12,0" +) +xt "43750,40600,50050,42000" +st "sdCas_n" +blo "43750,41800" +tm "WireNameMgr" +) +) +on &47 +) +*105 (Wire +uid 6024,0 +shape (OrthoPolyLine +uid 6025,0 +va (VaSet +vasetType 3 +) +xt "41750,40000,56250,40000" +pts [ +"41750,40000" +"56250,40000" +] +) +start &79 +end &38 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 6026,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6027,0 +va (VaSet +font "courier,12,0" +) +xt "43750,38600,48650,39900" +st "sdRas_n" +blo "43750,39600" +tm "WireNameMgr" +) +) +on &48 +) +*106 (Wire +uid 6030,0 +shape (OrthoPolyLine +uid 6031,0 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+) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "-6000,13200,-6000,13200" +tm "SyDeclarativeTextMgr" +) +) +lastUid 661,0 +activeModelName "Symbol" +) diff --git a/Libs/Sequential/hdl/DFFE_pre_sim.vhd b/Libs/Sequential/hdl/DFFE_pre_sim.vhd new file mode 100644 index 0000000..07bbccd --- /dev/null +++ b/Libs/Sequential/hdl/DFFE_pre_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF DFFE_pre IS +BEGIN + + process(clk, pre) + begin + if pre = '1' then + q <= '1' after delay; + elsif rising_edge(clk) then + if e = '1' then + q <= d after delay; + end if; + end if; + end process; + +END ARCHITECTURE sim; + diff --git a/Libs/Sequential/hdl/DFFE_sim.vhd b/Libs/Sequential/hdl/DFFE_sim.vhd new file mode 100644 index 0000000..41a917c --- /dev/null +++ b/Libs/Sequential/hdl/DFFE_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF DFFE IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0' after delay; + elsif rising_edge(clk) then + if e = '1' then + q <= d after delay; + end if; + end if; + end process; + +END ARCHITECTURE sim; + diff --git a/Libs/Sequential/hdl/DFFE_sim1.vhd b/Libs/Sequential/hdl/DFFE_sim1.vhd new file mode 100644 index 0000000..07bbccd --- /dev/null +++ b/Libs/Sequential/hdl/DFFE_sim1.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF DFFE_pre IS +BEGIN + + process(clk, pre) + begin + if pre = '1' then + q <= '1' after delay; + elsif rising_edge(clk) then + if e = '1' then + q <= d after delay; + end if; + end if; + end process; + +END ARCHITECTURE sim; + diff --git a/Libs/Sequential/hdl/DFF_pre_sim.vhd b/Libs/Sequential/hdl/DFF_pre_sim.vhd new file mode 100644 index 0000000..70a09a0 --- /dev/null +++ b/Libs/Sequential/hdl/DFF_pre_sim.vhd @@ -0,0 +1,13 @@ +ARCHITECTURE sim OF DFF_pre IS +BEGIN + + process(clk, pre) + begin + if pre = '1' then + q <= '1' after delay; + elsif rising_edge(clk) then + q <= d after delay; + end if; + end process; + +END sim; diff --git a/Libs/Sequential/hdl/DFF_sim.vhd b/Libs/Sequential/hdl/DFF_sim.vhd new file mode 100644 index 0000000..340b4fa --- /dev/null +++ b/Libs/Sequential/hdl/DFF_sim.vhd @@ -0,0 +1,13 @@ +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0' after delay; + elsif rising_edge(clk) then + q <= d after delay; + end if; + end process; + +END sim; diff --git a/Libs/Sequential/hdl/DFF_sim1.vhd b/Libs/Sequential/hdl/DFF_sim1.vhd new file mode 100644 index 0000000..a17f2f1 --- /dev/null +++ b/Libs/Sequential/hdl/DFF_sim1.vhd @@ -0,0 +1,18 @@ +ARCHITECTURE sim OF TFF IS + + signal q_int: std_ulogic; + +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q_int <= '0' after delay; + elsif rising_edge(clk) then + q_int <= t xor q_int after delay; + end if; + end process; + + q <= q_int; + +END sim; diff --git a/Libs/Sequential/hdl/DFF_sim11.vhd b/Libs/Sequential/hdl/DFF_sim11.vhd new file mode 100644 index 0000000..fcd88e6 --- /dev/null +++ b/Libs/Sequential/hdl/DFF_sim11.vhd @@ -0,0 +1,18 @@ +ARCHITECTURE sim OF TFF_pre IS + + signal q_int: std_ulogic; + +BEGIN + + process(clk, pre) + begin + if pre = '1' then + q_int <= '1' after delay; + elsif rising_edge(clk) then + q_int <= t xor q_int after delay; + end if; + end process; + + q <= q_int; + +END sim; diff --git a/Libs/Sequential/hdl/DFF_sim2.vhd b/Libs/Sequential/hdl/DFF_sim2.vhd new file mode 100644 index 0000000..70a09a0 --- /dev/null +++ b/Libs/Sequential/hdl/DFF_sim2.vhd @@ -0,0 +1,13 @@ +ARCHITECTURE sim OF DFF_pre IS +BEGIN + + process(clk, pre) + begin + if pre = '1' then + q <= '1' after delay; + elsif rising_edge(clk) then + q <= d after delay; + end if; + end process; + +END sim; diff --git a/Libs/Sequential/hdl/TFF_pre_sim.vhd b/Libs/Sequential/hdl/TFF_pre_sim.vhd new file mode 100644 index 0000000..fcd88e6 --- /dev/null +++ b/Libs/Sequential/hdl/TFF_pre_sim.vhd @@ -0,0 +1,18 @@ +ARCHITECTURE sim OF TFF_pre IS + + signal q_int: std_ulogic; + +BEGIN + + process(clk, pre) + begin + if pre = '1' then + q_int <= '1' after delay; + elsif rising_edge(clk) then + q_int <= t xor q_int after delay; + end if; + end process; + + q <= q_int; + +END sim; diff --git a/Libs/Sequential/hdl/TFF_sim.vhd b/Libs/Sequential/hdl/TFF_sim.vhd new file mode 100644 index 0000000..a17f2f1 --- /dev/null +++ b/Libs/Sequential/hdl/TFF_sim.vhd @@ -0,0 +1,18 @@ +ARCHITECTURE sim OF TFF IS + + signal q_int: std_ulogic; + +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q_int <= '0' after delay; + elsif rising_edge(clk) then + q_int <= t xor q_int after delay; + end if; + end process; + + q <= q_int; + +END sim; diff --git a/Libs/Sequential/hdl/accumulator_RTL.vhd b/Libs/Sequential/hdl/accumulator_RTL.vhd new file mode 100644 index 0000000..44d3ffe --- /dev/null +++ b/Libs/Sequential/hdl/accumulator_RTL.vhd @@ -0,0 +1,46 @@ +-------------------------------------------------------------------------------- +-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch) +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-------------------------------------------------------------------------------- +-- Accumulator +-- Accumulator with the step as signal and a synchronous clear signal. +-- +-- Created on 2013-03-03 +-- +-- Version: 1.0 +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-------------------------------------------------------------------------------- +-- +ARCHITECTURE RTL OF accumulator IS + signal sum_s : unsigned(bitNb-1 downto 0); +begin + + process (clock, reset) + begin + if reset = '1' then + sum_s <= (OTHERS => '0'); + elsif rising_edge(clock) then + if enable = '1' then + sum_s <= unsigned(step) + sum_s; + end if; + if clear = '1' then + sum_s <= (OTHERS => '0'); + end if; + end if; + end process; + + acc <= sum_s; + +END ARCHITECTURE RTL; + diff --git a/Libs/Sequential/hdl/counterEnableResetSync_rtl.vhd b/Libs/Sequential/hdl/counterEnableResetSync_rtl.vhd new file mode 100644 index 0000000..460fe82 --- /dev/null +++ b/Libs/Sequential/hdl/counterEnableResetSync_rtl.vhd @@ -0,0 +1,46 @@ +-------------------------------------------------------------------------------- +-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch) +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-------------------------------------------------------------------------------- +-- Counter +-- Simple counter with a generic width of nbBits. +-- +-- Created on 2013-08-10 +-- +-- Version: 1.0 +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-------------------------------------------------------------------------------- +-- +ARCHITECTURE rtl OF counterEnableResetSync IS + + signal sCountOut: unsigned(countOut'range); + +BEGIN + + countEndlessly: process(reset, clock) + begin + if reset = '1' then + sCountOut <= (others => '0'); + elsif rising_edge(clock) then + if resetSync = '1' then + sCountOut <= (others => '0'); + elsif enable = '1' then + sCountOut <= sCountOut + 1; + end if; + end if; + end process countEndlessly; + + countOut <= sCountOut after delay; + +END ARCHITECTURE RTL; diff --git a/Libs/Sequential/hdl/counterEnable_rtl.vhd b/Libs/Sequential/hdl/counterEnable_rtl.vhd new file mode 100644 index 0000000..1841030 --- /dev/null +++ b/Libs/Sequential/hdl/counterEnable_rtl.vhd @@ -0,0 +1,44 @@ +-------------------------------------------------------------------------------- +-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch) +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-------------------------------------------------------------------------------- +-- Counter +-- Simple counter with a generic width of nbBits. +-- +-- Created on 2013-08-10 +-- +-- Version: 1.0 +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-------------------------------------------------------------------------------- +-- +ARCHITECTURE rtl OF counterEnable IS + + signal sCountOut: unsigned(countOut'range); + +BEGIN + + countEndlessly: process(reset, clock) + begin + if reset = '1' then + sCountOut <= (others => '0'); + elsif rising_edge(clock) then + if enable = '1' then + sCountOut <= sCountOut + 1; + end if; + end if; + end process countEndlessly; + + countOut <= sCountOut after delay; + +END ARCHITECTURE RTL; diff --git a/Libs/Sequential/hdl/counterRestart_RTL.vhd b/Libs/Sequential/hdl/counterRestart_RTL.vhd new file mode 100644 index 0000000..a9950b9 --- /dev/null +++ b/Libs/Sequential/hdl/counterRestart_RTL.vhd @@ -0,0 +1,22 @@ +ARCHITECTURE RTL OF counterRestart IS + + signal count: unsigned(countOut'range); + +BEGIN + + countWithRestart: process(reset, clock) + begin + if reset = '1' then + count <= (others => '0'); + elsif rising_edge(clock) then + if restart = '1' then + count <= (others => '0'); + else + count <= count+1; + end if; + end if; + end process countWithRestart; + + countOut <= count after delay; + +END ARCHITECTURE RTL; diff --git a/Libs/Sequential/hdl/counterUpDownEnable_RTL.vhd b/Libs/Sequential/hdl/counterUpDownEnable_RTL.vhd new file mode 100644 index 0000000..7decb38 --- /dev/null +++ b/Libs/Sequential/hdl/counterUpDownEnable_RTL.vhd @@ -0,0 +1,24 @@ +ARCHITECTURE RTL OF counterUpDownEnable IS + + signal sCountOut: unsigned(countOut'range); + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + sCountOut <= (others => '0'); + elsif rising_edge(clock) then + if enable = '1' then + if up = '1' then + sCountOut <= sCountOut + 1; + elsif down = '1' then + sCountOut <= sCountOut - 1; + end if; + end if; + end if; + end process count; + + countOut <= sCountOut after delay; + +END ARCHITECTURE RTL; diff --git a/Libs/Sequential/hdl/counterUpDown_RTL.vhd b/Libs/Sequential/hdl/counterUpDown_RTL.vhd new file mode 100644 index 0000000..a141be4 --- /dev/null +++ b/Libs/Sequential/hdl/counterUpDown_RTL.vhd @@ -0,0 +1,22 @@ +ARCHITECTURE RTL OF counterUpDown IS + + signal sCountOut: unsigned(countOut'range); + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + sCountOut <= (others => '0'); + elsif rising_edge(clock) then + if up = '1' then + sCountOut <= sCountOut + 1; + elsif down = '1' then + sCountOut <= sCountOut - 1; + end if; + end if; + end process count; + + countOut <= sCountOut after delay; + +END ARCHITECTURE RTL; diff --git a/Libs/Sequential/hdl/counter_rtl.vhd b/Libs/Sequential/hdl/counter_rtl.vhd new file mode 100644 index 0000000..d20f51d --- /dev/null +++ b/Libs/Sequential/hdl/counter_rtl.vhd @@ -0,0 +1,18 @@ +ARCHITECTURE RTL OF counter IS + + signal count: unsigned(countOut'range); + +BEGIN + + countEndlessly: process(reset, clock) + begin + if reset = '1' then + count <= (others => '0'); + elsif rising_edge(clock) then + count <= count+1; + end if; + end process countEndlessly; + + countOut <= count after delay; + +END ARCHITECTURE RTL; diff --git a/Libs/Sequential/hdl/edgeDetector_arch.vhd b/Libs/Sequential/hdl/edgeDetector_arch.vhd new file mode 100644 index 0000000..69958e7 --- /dev/null +++ b/Libs/Sequential/hdl/edgeDetector_arch.vhd @@ -0,0 +1,50 @@ +-------------------------------------------------------------------------------- +-- Copyright 2014 HES-SO Valais Wallis (www.hevs.ch) +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-------------------------------------------------------------------------------- +-- EdgeDetector +-- Detect rising and falling edges of a signal. +-- +-- Created on 2014-04-02 +-- +-- Version: 1.0 +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-------------------------------------------------------------------------------- +ARCHITECTURE arch OF edgeDetector IS + + SIGNAL signal_s : std_ulogic; + SIGNAL rising_detected_s : std_ulogic; + SIGNAL falling_detected_s : std_ulogic; + +BEGIN + + -- sync + reg : PROCESS (reset,clock) + BEGIN + IF reset = '1' THEN + signal_s <= '0'; + ELSIF rising_edge(clock) THEN + signal_s <= input; + END IF; + END PROCESS reg ; + + -- edge detection + rising_detected_s <= input AND NOT signal_s; + falling_detected_s <= NOT input AND signal_s; + + -- output + rising_detected <= rising_detected_s; + falling_detected <= falling_detected_s; + +END ARCHITECTURE arch; diff --git a/Libs/Sequential/hdl/freqDividerEnable_RTL.vhd b/Libs/Sequential/hdl/freqDividerEnable_RTL.vhd new file mode 100644 index 0000000..93ac7f6 --- /dev/null +++ b/Libs/Sequential/hdl/freqDividerEnable_RTL.vhd @@ -0,0 +1,28 @@ +LIBRARY Common; + USE Common.CommonLib.all; + +ARCHITECTURE RTL OF freqDividerEnable IS + + signal count: unsigned(requiredBitNb(divideValue)-1 downto 0); + +BEGIN + + countEndlessly: process(reset, clock) + begin + if reset = '1' then + count <= (others => '0'); + elsif rising_edge(clock) then + if enIn = '1' then + if count = 0 then + count <= to_unsigned(divideValue-1, count'length); + else + count <= count-1 ; + end if; + end if; + end if; + end process countEndlessly; + + enOut <= '1' after delay when count = 0 + else '0' after delay; + +END ARCHITECTURE RTL; diff --git a/Libs/Sequential/hdl/freqDivider_RTL.vhd b/Libs/Sequential/hdl/freqDivider_RTL.vhd new file mode 100644 index 0000000..6462dce --- /dev/null +++ b/Libs/Sequential/hdl/freqDivider_RTL.vhd @@ -0,0 +1,26 @@ +LIBRARY Common; + USE Common.CommonLib.all; + +ARCHITECTURE RTL OF freqDivider IS + + signal count: unsigned(requiredBitNb(divideValue)-1 downto 0); + +BEGIN + + countEndlessly: process(reset, clock) + begin + if reset = '1' then + count <= (others => '0'); + elsif rising_edge(clock) then + if count = 0 then + count <= to_unsigned(divideValue-1, count'length); + else + count <= count-1 ; + end if; + end if; + end process countEndlessly; + + enable <= '1' after delay when count = 0 + else '0' after delay; + +END ARCHITECTURE RTL; diff --git a/Libs/Sequential/hdl/registerLogicVector_sim.vhd b/Libs/Sequential/hdl/registerLogicVector_sim.vhd new file mode 100644 index 0000000..11cfb55 --- /dev/null +++ b/Libs/Sequential/hdl/registerLogicVector_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF registerLogicVector IS +BEGIN + + registerData: process(reset, clock) + begin + if reset = '1' then + dataOut <= (others => '0') after delay; + elsif rising_edge(clock) then + if enable = '1' then + dataOut <= dataIn after delay; + end if; + end if; + end process registerData; + +END ARCHITECTURE sim; + diff --git a/Libs/Sequential/hdl/registerSigned_sim.vhd b/Libs/Sequential/hdl/registerSigned_sim.vhd new file mode 100644 index 0000000..4010de2 --- /dev/null +++ b/Libs/Sequential/hdl/registerSigned_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF registerSigned IS +BEGIN + + registerData: process(reset, clock) + begin + if reset = '1' then + dataOut <= (others => '0') after delay; + elsif rising_edge(clock) then + if enable = '1' then + dataOut <= dataIn after delay; + end if; + end if; + end process registerData; + +END ARCHITECTURE sim; + diff --git a/Libs/Sequential/hdl/registerULogicVectorTo_RTL.vhd b/Libs/Sequential/hdl/registerULogicVectorTo_RTL.vhd new file mode 100644 index 0000000..458385d --- /dev/null +++ b/Libs/Sequential/hdl/registerULogicVectorTo_RTL.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF registerULogicVectorTo IS +BEGIN + + registerData: process(reset, clock) + begin + if reset = '1' then + dataOut <= (others => '0') after delay; + elsif rising_edge(clock) then + if enable = '1' then + dataOut <= dataIn after delay; + end if; + end if; + end process registerData; + +END ARCHITECTURE sim; + diff --git a/Libs/Sequential/hdl/registerULogicVector_sim.vhd b/Libs/Sequential/hdl/registerULogicVector_sim.vhd new file mode 100644 index 0000000..88c99d0 --- /dev/null +++ b/Libs/Sequential/hdl/registerULogicVector_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF registerULogicVector IS +BEGIN + + registerData: process(reset, clock) + begin + if reset = '1' then + dataOut <= (others => '0') after delay; + elsif rising_edge(clock) then + if enable = '1' then + dataOut <= dataIn after delay; + end if; + end if; + end process registerData; + +END ARCHITECTURE sim; + diff --git a/Libs/Sequential/hdl/registerULogicVector_sim1.vhd b/Libs/Sequential/hdl/registerULogicVector_sim1.vhd new file mode 100644 index 0000000..11cfb55 --- /dev/null +++ b/Libs/Sequential/hdl/registerULogicVector_sim1.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF registerLogicVector IS +BEGIN + + registerData: process(reset, clock) + begin + if reset = '1' then + dataOut <= (others => '0') after delay; + elsif rising_edge(clock) then + if enable = '1' then + dataOut <= dataIn after delay; + end if; + end if; + end process registerData; + +END ARCHITECTURE sim; + diff --git a/Libs/Sequential/hdl/registerUnsigned_sim.vhd b/Libs/Sequential/hdl/registerUnsigned_sim.vhd new file mode 100644 index 0000000..0fe6357 --- /dev/null +++ b/Libs/Sequential/hdl/registerUnsigned_sim.vhd @@ -0,0 +1,16 @@ +ARCHITECTURE sim OF registerUnsigned IS +BEGIN + + registerData: process(reset, clock) + begin + if reset = '1' then + dataOut <= (others => '0') after delay; + elsif rising_edge(clock) then + if enable = '1' then + dataOut <= dataIn after delay; + end if; + end if; + end process registerData; + +END ARCHITECTURE sim; + diff --git a/Libs/Sequential/hds/.hdlsidedata/_DFFE_pre_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_DFFE_pre_sim.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_DFFE_pre_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_DFFE_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_DFFE_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_DFFE_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_DFFE_sim1.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_DFFE_sim1.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_DFFE_sim1.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_DFF_pre_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_DFF_pre_sim.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_DFF_pre_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_DFF_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_DFF_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_DFF_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_DFF_sim1.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_DFF_sim1.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_DFF_sim1.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_DFF_sim11.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_DFF_sim11.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_DFF_sim11.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_DFF_sim2.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_DFF_sim2.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_DFF_sim2.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_SRAM_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_SRAM_sim.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_SRAM_sim.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Sequential/hds/.hdlsidedata/_TFF_pre_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_TFF_pre_sim.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_TFF_pre_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_TFF_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_TFF_sim.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_TFF_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_accumulator_RTL.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_accumulator_RTL.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_accumulator_RTL.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Sequential/hds/.hdlsidedata/_accumulator_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_accumulator_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_accumulator_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterEnableResetSync_rtl.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterEnableResetSync_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterEnableResetSync_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterEnable_rtl.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterEnable_rtl.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterEnable_rtl.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterRestart_RTL.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterRestart_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterRestart_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterUpDownEnable_RTL.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterUpDownEnable_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterUpDownEnable_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterUpDown_RTL.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterUpDown_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterUpDown_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterUpDown_arch.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterUpDown_arch.vhd._fpf new file mode 100644 index 0000000..19d6635 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterUpDown_arch.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2002 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counter_arch.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_counter_arch.vhd._fpf new file mode 100644 index 0000000..19d6635 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counter_arch.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2002 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counter_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_counter_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counter_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counter_rtl.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_counter_rtl.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counter_rtl.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterenable_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterenable_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterenable_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterenableresetsync_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterenableresetsync_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterenableresetsync_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterrestart_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterrestart_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterrestart_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterupdown_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterupdown_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterupdown_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterupdownenable_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterupdownenable_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterupdownenable_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_counterupdownenable_struct.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_counterupdownenable_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_counterupdownenable_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_dff_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_dff_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_dff_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_dff_pre_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_dff_pre_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_dff_pre_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_dffe_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_dffe_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_dffe_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_dffe_pre_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_dffe_pre_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_dffe_pre_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_edgeDetector_RTL.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_edgeDetector_RTL.vhd._fpf new file mode 100644 index 0000000..19d6635 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_edgeDetector_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2002 diff --git a/Libs/Sequential/hds/.hdlsidedata/_edgeDetector_arch.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_edgeDetector_arch.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_edgeDetector_arch.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Sequential/hds/.hdlsidedata/_edgedetector_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_edgedetector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_edgedetector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_freqDividerEnable_RTL.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_freqDividerEnable_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_freqDividerEnable_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_freqDivider_RTL.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_freqDivider_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_freqDivider_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_freqdivider_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_freqdivider_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_freqdivider_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_freqdividerenable_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_freqdividerenable_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_freqdividerenable_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerLogicVector_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerLogicVector_sim.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerLogicVector_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerSigned_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerSigned_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerSigned_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerULogicVectorTo_RTL.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerULogicVectorTo_RTL.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerULogicVectorTo_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerULogicVector_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerULogicVector_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerULogicVector_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerULogicVector_sim1.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerULogicVector_sim1.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerULogicVector_sim1.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerUnsigned_sim.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerUnsigned_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerUnsigned_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerfile_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerfile_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerfile_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerfile_struct.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerfile_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerfile_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerlogicvector_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerlogicvector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerlogicvector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registersigned_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_registersigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registersigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerulogicvector_entity.vhd._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerulogicvector_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerulogicvector_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerulogicvector_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerulogicvector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerulogicvector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerulogicvectorto_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerulogicvectorto_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerulogicvectorto_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_registerunsigned_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_registerunsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_registerunsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_reglatch_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_reglatch_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_reglatch_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_sram_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_sram_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_sram_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_sram_struct.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_sram_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_sram_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_tff_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_tff_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_tff_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Sequential/hds/.hdlsidedata/_tff_pre_entity.vhg._fpf b/Libs/Sequential/hds/.hdlsidedata/_tff_pre_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Sequential/hds/.hdlsidedata/_tff_pre_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff 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+) +portLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,8000,2700,9000" +st "Ports:" +blo "0,8800" +) +externalLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,13500,2500,14400" +st "User:" +blo "0,14200" +) +internalLabel (Text +uid 2,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,15100,5800,16100" +st "Internal User:" +blo "0,15900" +) +externalText (MLText +uid 3,0 +va (VaSet +font "courier,8,0" +) +xt "2000,14400,2000,14400" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 4,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "2000,16800,2000,16800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 329,0 +activeModelName "Symbol" +) diff --git a/Prefs/hds.hdp b/Prefs/hds.hdp new file mode 100644 index 0000000..a48c39c --- /dev/null +++ b/Prefs/hds.hdp @@ -0,0 +1,50 @@ +[Concat] +Board = $HDS_PROJECT_DIR/../Board/concat +[ModelSim] +Board = $SCRATCH_DIR/Board/work +Common = $SCRATCH_DIR/Common/work +Cursor = $SCRATCH_DIR/Cursor/work +Cursor_test = $SCRATCH_DIR/Cursor_test/work +gates = $SCRATCH_DIR/gates/work +io = $SCRATCH_DIR/IO/work +LCD = $SCRATCH_DIR/LCD/work +LCD_test = $SCRATCH_DIR/LCD_test/work +Memory = $SCRATCH_DIR/Memory/work +Memory_test = $SCRATCH_DIR/Memory_test/work +sequential = $SCRATCH_DIR/sequential/work +[hdl] +Board = $HDS_PROJECT_DIR/../Board/hdl +Common = $HEI_LIBS_DIR/Common/hdl +Cursor = $HDS_PROJECT_DIR/../Cursor/hdl +Cursor_test = $HDS_PROJECT_DIR/../Cursor_test/hdl +gates = $HEI_LIBS_DIR/Gates/hdl +ieee = $HDS_HOME/hdl_libs/ieee/hdl +io = $HEI_LIBS_DIR/IO/hdl +LCD = $HEI_LIBS_DIR/Lcd/hdl +LCD_test = $HEI_LIBS_DIR/Lcd_test/hdl +Memory = $HEI_LIBS_DIR/Memory/hdl +Memory_test = $HEI_LIBS_DIR/Memory_test/hdl +sequential = $HEI_LIBS_DIR/Sequential/hdl +std = $HDS_HOME/hdl_libs/std/hdl +[hds] +Board = $HDS_PROJECT_DIR/../Board/hds +Common = $HEI_LIBS_DIR/Common/hds +Cursor = $HDS_PROJECT_DIR/../Cursor/hds +Cursor_test = $HDS_PROJECT_DIR/../Cursor_test/hds +gates = $HEI_LIBS_DIR/Gates/hds +ieee = $HDS_HOME/hdl_libs/ieee/hds +io = $HEI_LIBS_DIR/IO/hds +LCD = $HEI_LIBS_DIR/Lcd/hds +LCD_test = $HEI_LIBS_DIR/Lcd_test/hds +Memory = $HEI_LIBS_DIR/Memory/hds +Memory_test = $HEI_LIBS_DIR/Memory_test/hds +sequential = $HEI_LIBS_DIR/Sequential/hds +std = $HDS_HOME/hdl_libs/std/hds +[hds_settings] +design_root = Cursor_test.cursor_tb(struct)cursor_tb/struct.bd +[library_type] +Board = regular +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/Prefs/hds_team/shared.hdp b/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/Prefs/hds_team/v2015.2/hds_team_prefs b/Prefs/hds_team/v2015.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/Prefs/hds_team/v2015.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/Prefs/hds_team/v2015.2/title_block.tmpl b/Prefs/hds_team/v2015.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/Prefs/hds_team/v2015.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/Prefs/hds_team/v2018.1/hds_team_prefs b/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/Prefs/hds_team/v2018.1/title_block.tmpl b/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/Prefs/hds_team/v2019.2/hds_team_prefs b/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/Prefs/hds_team/v2019.2/title_block.tmpl b/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 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+textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "Emacs (using server)" +second "emacsclient +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "XEmacs" +second "xemacs +%(l) '%(p)'" +) +(pair +first "XEmacs (using server)" +second "gnuclient +%(l) '%(p)'" +) +(pair +first "XTerm with Editor" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e \"${EDITOR:-vi}\" '%(f)'" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi +%(l) '%(f)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair 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"notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Builtin" +win32DefaultViewer "Builtin" +unixDefaultEditor "Builtin" +unixDefaultViewer "Builtin" +defaultLanguage 0 +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"TabularWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/ElN_cursor.hdp" +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +defaultUserLibRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +" +defaultVerilogPackages "" +defaultFont "courier,10,0" +tableFont "courier,10,0" +pageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +pageSizes [ +] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ +(StringtoTwoInts +name "A4 (134mm x 110mm)" +width 379 +height 313 +) +(StringtoTwoInts +name "A4 (134mm x 221mm)" +width 379 +height 626 +) +(StringtoTwoInts +name "Letter (5.5\" x 4\")" +width 396 +height 288 +) +(StringtoTwoInts +name "Letter (5.5\" x 8\")" +width 396 +height 576 +) +] +titleBlockPath "$HDS_TEAM_VER/title_block.tmpl" +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +userFileNames 1 +commentGraphicShapeVaSet (VaSet +vasetType 1 +fg "49152,49152,49152" +) +pageConnTextVaSet (VaSet +fg "0,0,50000" +font "courier,8,1" +) +teamPrefsPath "" +remoteSimPath "$HDS_TEAM_VER/remote" +mwMVL4 1 +mwVerilogUseSynthesisPragmas 0 +mwVhdlUseBusSlicesChkBox 0 +mwVerilogUseBusSlicesChkBox 0 +vmCheckInDesc "" +userVariables [ +(pair +first "task_DesignCompilerPath" +second "" +) +(pair +first "task_LeonardoPath" +second "" +) +(pair +first "task_ModelSimPath" +second "/usr/opt/Modelsim/modeltech/bin" +) +(pair +first "task_NC-SimPath" +second "" +) +(pair +first "task_PrecisionRTLPath" +second "" +) +(pair +first "task_QuestaSimPath" +second "" +) +(pair +first "task_VCSPath" +second "" +) +] +tasksOrder [ +"USER:Generate" +"USER:DesignChecker" +"USER:DesignChecker Flow" +"USER:Register Assistant" +"USER:SystemVerilog Assistant" +"USER:ModelSim Compile" +"USER:ModelSim Simulate" +"USER:QuestaSim Compile" +"USER:QuestaSim Simulate" +"USER:Precision Synthesis" +"USER:LeonardoSpectrum" +"USER:Xilinx CORE Generator" +"USER:Altera MegaWizard" +"USER:Altera SOPC Builder" +"USER:Xilinx Platform Studio" +"USER:FPGA Technology Setup" +"USER:FPGA Library Compile" +"USER:Xilinx Synthesis Tool" +"USER:Xilinx Place and Route" +"USER:Xilinx Import" +"USER:Quartus II Synthesis" +"USER:Quartus Place and Route" +"USER:Quartus Programmer" +"USER:Actel Place and Route" +"USER:Lattice Place and Route" +"USER:C/C++ Wrapper Generator" +"USER:ModelSim Flow" +"USER:QuestaSim Flow" +"USER:LeonardoSpectrum Flow" +"USER:Precision Synthesis Flow" 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+wStateShapeVaSet (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "26368,26368,26368" +lineWidth 2 +) +wStateTextVaSet (VaSet +fg "0,0,32768" +font "courier,10,1" +) +tBlockShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +tBlockLineVaSet (VaSet +vasetType 3 +) +tBlockConditionVaSet (VaSet +font "courier,8,0" +) +tBlockActionsVaSet (VaSet +font "courier,8,0" +) +tPriorityRadius 40 +tPriorityPadding 100 +tPriorityShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +tPriorityNameVaSet (VaSet +font "courier,8,0" +) +transitionShapeVaSet (VaSet +vasetType 3 +) +localDeclLabelVaSet (VaSet +font "courier,8,1" +) +localDeclValueVaSet (VaSet +font "courier,8,0" +) +processDeclLabelVaSet (VaSet +font "courier,8,1" +) +processDeclValueVaSet (VaSet +font "courier,8,0" +) +globalActionsLabelVaSet (VaSet +font "courier,8,1" +) +globalActionsValueVaSet (VaSet +font "courier,8,0" +) +stateRegBlkLabelVaSet (VaSet +font "courier,8,1" +) +stateRegBlkValueVaSet (VaSet +font "courier,8,0" +) +signalsGenStatusVaSet (VaSet +font "courier,8,1" +) +signalsGenStatusValueVaSet (VaSet +font "courier,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "courier,8,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +font "courier,8,0" +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "courier,8,1" +) +packageListFontVaSet (VaSet +font "courier,8,0" +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +font "courier,8,0" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "courier,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "26368,26368,26368" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "courier,8,1" +) +CompDirValueVaSet (VaSet +font "courier,8,0" +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "courier,8,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "courier,8,1" +) +cptPortFontVaSet (VaSet +font "courier,8,0" +) +genericInterfaceFontVaSet (VaSet +font "courier,8,0" +) +portRowVaSet (VaSet +vasetType 4 +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "std_logic_vector" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +) +] diff --git a/Prefs/hds_user-linux/v2015.2/tasks/actel_place_and_route.tsk b/Prefs/hds_user-linux/v2015.2/tasks/actel_place_and_route.tsk new file mode 100644 index 0000000..014f1ac --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/actel_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Actel Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_actel.bmp" +hasBitmap 1 +tooltip "Invokes the Actel Designer Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"ActelPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/altera_megawizard.tsk b/Prefs/hds_user-linux/v2015.2/tasks/altera_megawizard.tsk new file mode 100644 index 0000000..1b63782 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/altera_megawizard.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Altera MegaWizard" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_alteramegawizard.bmp" +hasBitmap 1 +tooltip "Creates Altera Megawizard components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"\"%(p)\" %(library)" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraMegaWizard" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/altera_sopc_builder.tsk b/Prefs/hds_user-linux/v2015.2/tasks/altera_sopc_builder.tsk new file mode 100644 index 0000000..5a394b1 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/altera_sopc_builder.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Altera SOPC Builder" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_alterasopc.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Altera SOPC Builder" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraSOPC" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/c_c_wrapper_generator.tsk b/Prefs/hds_user-linux/v2015.2/tasks/c_c_wrapper_generator.tsk new file mode 100644 index 0000000..aa121c5 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/c_c_wrapper_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "C/C++ Wrapper Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_cwrapper.bmp" +hasBitmap 1 +tooltip "Generates an HDL wrapper for a C/C++ view" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"CWrapperGen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/designchecker.tsk b/Prefs/hds_user-linux/v2015.2/tasks/designchecker.tsk new file mode 100644 index 0000000..a955548 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/designchecker.tsk @@ -0,0 +1,43 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignChecker" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Runs DesignChecker" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"forceGui" +"NO_FORCE" +"initialDir" +"" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"HdsLintPlugin" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/designchecker_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/designchecker_flow.tsk new file mode 100644 index 0000000..2d662f3 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/designchecker_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "DesignChecker Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Generate and runs DesignChecker" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "DesignChecker" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"forceGui" +"NO_FORCE" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:DesignChecker" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/fpga_library_compile.tsk b/Prefs/hds_user-linux/v2015.2/tasks/fpga_library_compile.tsk new file mode 100644 index 0000000..eedb81a --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/fpga_library_compile.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Library Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgalibcomp.bmp" +hasBitmap 1 +tooltip "Compiles Vendor Simulation Libraries" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaLibsComp" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/fpga_technology_setup.tsk b/Prefs/hds_user-linux/v2015.2/tasks/fpga_technology_setup.tsk new file mode 100644 index 0000000..f1b887c --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/fpga_technology_setup.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Technology Setup" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgatechsetup.bmp" +hasBitmap 1 +tooltip "Sets the FPGA technology" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaTechSetup" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/generate.tsk b/Prefs/hds_user-linux/v2015.2/tasks/generate.tsk new file mode 100644 index 0000000..d248a15 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/i_o_design_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/i_o_design_flow.tsk new file mode 100644 index 0000000..a191262 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/i_o_design_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "I/O Design Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Generate and runs BoardLink Pro to define pin assignments" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "I/O Design" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Runs BoardLink Pro to define pin assignments" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"BoardLinkPro" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/lattice_place_and_route.tsk b/Prefs/hds_user-linux/v2015.2/tasks/lattice_place_and_route.tsk new file mode 100644 index 0000000..d1f9f2e --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/lattice_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Lattice Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"LatticePARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/leonardospectrum.tsk b/Prefs/hds_user-linux/v2015.2/tasks/leonardospectrum.tsk new file mode 100644 index 0000000..3ab131f --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/leonardospectrum.tsk @@ -0,0 +1,101 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "LeonardoSpectrum" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Runs LeonardoSpectrum data preparation and invokes tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"$HDS_HOME/resources/tcl/plugins/dialogs/SpectrumCombinedDlg.tbc" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "LeonardoSpectrum Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Does data preparation for LeonardoSpectrum" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"SpectrumDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "LeonardoSpectrum Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Invokes the LeonardoSpectrum Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"SpectrumInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/leonardospectrum_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/leonardospectrum_flow.tsk new file mode 100644 index 0000000..fa1af05 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/leonardospectrum_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "LeonardoSpectrum Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire LeonardoSpectrum flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "LeonardoSpectrum" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:LeonardoSpectrum" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/modelsim_compile.tsk b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..6bf537f --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_compile.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/modelsim_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..9e6f746 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_flow.tsk @@ -0,0 +1,74 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "/usr/opt/Modelsim/modeltech/bin" +) +(preferedMap +preferedEnum 2 +preferedSetting "MODEL_SIM" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/modelsim_simulate.tsk b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..e11f828 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis.tsk b/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis.tsk new file mode 100644 index 0000000..e4a16ef --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis.tsk @@ -0,0 +1,101 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Runs Precision data preparation and invokes tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"$HDS_HOME/resources/tcl/plugins/dialogs/PrecisionSynthesisCombinedDlg.tbc" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Does data preparation for Precision Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"PrecisionSynthesisDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Invokes the Precision Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"PrecisionSynthesisInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis_flow.tsk new file mode 100644 index 0000000..3b1c63a --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Precision Synthesis flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Precision Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Precision Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis.tsk b/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis.tsk new file mode 100644 index 0000000..4d806ce --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus II Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Quartus II Synthesis data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus II Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus II Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus II Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis_flow.tsk new file mode 100644 index 0000000..20f9ba1 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus II Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Quartus QIS Synthesis flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Quartus II Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Quartus II Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/quartus_place_and_route.tsk b/Prefs/hds_user-linux/v2015.2/tasks/quartus_place_and_route.tsk new file mode 100644 index 0000000..1ba58ba --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/quartus_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_altera_quartus.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/quartus_programmer.tsk b/Prefs/hds_user-linux/v2015.2/tasks/quartus_programmer.tsk new file mode 100644 index 0000000..a655174 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/quartus_programmer.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Programmer" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_programmer.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Programmer tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPGMInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/questasim_compile.tsk b/Prefs/hds_user-linux/v2015.2/tasks/questasim_compile.tsk new file mode 100644 index 0000000..1cbe2b6 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/questasim_compile.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "QuestaSim Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_questasim_compile.bmp" +hasBitmap 1 +tooltip "Runs QuestaSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QuestaSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/questasim_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/questasim_flow.tsk new file mode 100644 index 0000000..3a2e9c1 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/questasim_flow.tsk @@ -0,0 +1,66 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "QuestaSim Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_questasim.bmp" +hasBitmap 1 +tooltip "Generate and run entire QuestaSim flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "QuestaSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:QuestaSim Compile" +) +(HDSTaskRef +TaskName "QuestaSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:QuestaSim Simulate" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/questasim_simulate.tsk b/Prefs/hds_user-linux/v2015.2/tasks/questasim_simulate.tsk new file mode 100644 index 0000000..9201889 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/questasim_simulate.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "QuestaSim Simulate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_questasim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the QuestaSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QuestaSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/register_assistant.tsk b/Prefs/hds_user-linux/v2015.2/tasks/register_assistant.tsk new file mode 100644 index 0000000..c2c17d0 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/register_assistant.tsk @@ -0,0 +1,45 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Register Assistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_registerassistant.bmp" +hasBitmap 1 +tooltip "Invokes Register Assistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"RegisterAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/systemverilog_assistant.tsk b/Prefs/hds_user-linux/v2015.2/tasks/systemverilog_assistant.tsk new file mode 100644 index 0000000..1b0b2e6 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/systemverilog_assistant.tsk @@ -0,0 +1,45 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "SystemVerilog Assistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SystemVerilog Assistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"SvAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_core_generator.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_core_generator.tsk new file mode 100644 index 0000000..f7da1b9 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_core_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx CORE Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxcoregen.bmp" +hasBitmap 1 +tooltip "Creates Xilinx ISE CORE Generator components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxCoregen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_import.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_import.tsk new file mode 100644 index 0000000..16050ec --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_import.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Import" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_import.bmp" +hasBitmap 1 +tooltip "Import Existing Xilinx ISE Project into HDS" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxImport" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_place_and_route.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_place_and_route.tsk new file mode 100644 index 0000000..76ae08d --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_projnav.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ISEPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_platform_studio.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_platform_studio.tsk new file mode 100644 index 0000000..20d8090 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_platform_studio.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Platform Studio" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxplatstudio.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Xilinx Platform Studio" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxPlatStudio" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool.tsk new file mode 100644 index 0000000..a2db8d3 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Xilinx ISE Synthesis Tool data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XSTDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XSTInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool_flow.tsk new file mode 100644 index 0000000..7105fe5 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Xilinx Synthesis Tool flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Xilinx Synthesis Tool" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Xilinx Synthesis Tool" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_vivado_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_vivado_flow.tsk new file mode 100644 index 0000000..25c63cc --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_vivado_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Vivado Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "Generate and runs Xilinx Vivado wizard" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Vivado" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "HDS integration with Xilinx Vivado" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxVivado" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/templates/text_files/new_document.txt b/Prefs/hds_user-linux/v2015.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_combined/combined.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_entity/entity.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user-linux/v2018.1/hds_user_prefs b/Prefs/hds_user-linux/v2018.1/hds_user_prefs new file mode 100644 index 0000000..0c35b12 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/hds_user_prefs @@ -0,0 +1,5790 @@ +version "48.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Builtin" +win32DefaultViewer "Builtin" +unixDefaultEditor "Atom" +unixDefaultViewer "Builtin" +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"TabularWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/ElN_cursor.hdp" +"/home/francois/Favorites/ElN_local/Labs/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +defaultUserLibRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +" +defaultVerilogPackages "" +defaultFont "courier,10,0" +tableFont "courier,10,0" +pageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +pageSizes [ +] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ +(StringtoTwoInts +name "A4 (134mm x 110mm)" +width 379 +height 313 +) +(StringtoTwoInts +name "A4 (134mm x 221mm)" +width 379 +height 626 +) +(StringtoTwoInts +name "Letter (5.5\" x 4\")" +width 396 +height 288 +) +(StringtoTwoInts +name "Letter (5.5\" x 8\")" +width 396 +height 576 +) +] +titleBlockPath "$HDS_TEAM_VER/title_block.tmpl" +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +userFileNames 1 +commentGraphicShapeVaSet (VaSet +vasetType 1 +fg "49152,49152,49152" +) +pageConnTextVaSet (VaSet +fg "0,0,50000" +font "courier,8,1" +) +teamPrefsPath "" +remoteSimPath "$HDS_TEAM_VER/remote" +mwMVL4 1 +mwVerilogUseSynthesisPragmas 0 +mwVhdlUseBusSlicesChkBox 0 +mwVerilogUseBusSlicesChkBox 0 +vmCheckInDesc "" +userVariables [ +(pair +first "task_DesignCompilerPath" +second "" +) +(pair +first "task_LeonardoPath" +second "" +) +(pair +first "task_ModelSimPath" +second "/usr/opt/Modelsim/modeltech/bin" +) +(pair +first "task_NC-SimPath" +second "" +) +(pair +first "task_PrecisionRTLPath" +second "" +) +(pair +first "task_QuestaSimPath" +second "" +) +(pair +first "task_VCSPath" +second "" +) +] +tasksOrder [ +"USER:Generate" +"USER:DesignChecker" +"USER:DesignChecker Flow" +"USER:Register Assistant" +"USER:ModelSim Compile" +"USER:ModelSim Simulate" +"USER:QuestaSim Compile" +"USER:QuestaSim Simulate" +"USER:Precision Synthesis" +"USER:LeonardoSpectrum" +"USER:Xilinx CORE Generator" +"USER:Altera MegaWizard" +"USER:Altera SOPC Builder" +"USER:Xilinx Platform Studio" +"USER:FPGA Technology Setup" +"USER:FPGA Library Compile" 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+DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +) +] diff --git a/Prefs/hds_user-linux/v2018.1/tasks/actel_place_and_route.tsk b/Prefs/hds_user-linux/v2018.1/tasks/actel_place_and_route.tsk new file mode 100644 index 0000000..014f1ac --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/actel_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Actel Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_actel.bmp" +hasBitmap 1 +tooltip "Invokes the Actel Designer Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"ActelPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/altera_megawizard.tsk b/Prefs/hds_user-linux/v2018.1/tasks/altera_megawizard.tsk new file mode 100644 index 0000000..1b63782 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/altera_megawizard.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Altera MegaWizard" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_alteramegawizard.bmp" +hasBitmap 1 +tooltip "Creates Altera Megawizard components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"\"%(p)\" %(library)" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraMegaWizard" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/altera_sopc_builder.tsk b/Prefs/hds_user-linux/v2018.1/tasks/altera_sopc_builder.tsk new file mode 100644 index 0000000..5a394b1 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/altera_sopc_builder.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Altera SOPC Builder" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_alterasopc.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Altera SOPC Builder" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraSOPC" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/c_c_wrapper_generator.tsk b/Prefs/hds_user-linux/v2018.1/tasks/c_c_wrapper_generator.tsk new file mode 100644 index 0000000..aa121c5 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/c_c_wrapper_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "C/C++ Wrapper Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_cwrapper.bmp" +hasBitmap 1 +tooltip "Generates an HDL wrapper for a C/C++ view" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"CWrapperGen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/designchecker.tsk b/Prefs/hds_user-linux/v2018.1/tasks/designchecker.tsk new file mode 100644 index 0000000..a955548 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/designchecker.tsk @@ -0,0 +1,43 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignChecker" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Runs DesignChecker" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"forceGui" +"NO_FORCE" +"initialDir" +"" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"HdsLintPlugin" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/designchecker_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/designchecker_flow.tsk new file mode 100644 index 0000000..2d662f3 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/designchecker_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "DesignChecker Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Generate and runs DesignChecker" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "DesignChecker" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"forceGui" +"NO_FORCE" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:DesignChecker" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/fpga_library_compile.tsk b/Prefs/hds_user-linux/v2018.1/tasks/fpga_library_compile.tsk new file mode 100644 index 0000000..eedb81a --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/fpga_library_compile.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Library Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgalibcomp.bmp" +hasBitmap 1 +tooltip "Compiles Vendor Simulation Libraries" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaLibsComp" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/fpga_technology_setup.tsk b/Prefs/hds_user-linux/v2018.1/tasks/fpga_technology_setup.tsk new file mode 100644 index 0000000..f1b887c --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/fpga_technology_setup.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Technology Setup" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgatechsetup.bmp" +hasBitmap 1 +tooltip "Sets the FPGA technology" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaTechSetup" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/generate.tsk b/Prefs/hds_user-linux/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..d248a15 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/i_o_design_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/i_o_design_flow.tsk new file mode 100644 index 0000000..a191262 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/i_o_design_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "I/O Design Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Generate and runs BoardLink Pro to define pin assignments" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "I/O Design" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Runs BoardLink Pro to define pin assignments" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"BoardLinkPro" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/lattice_place_and_route.tsk b/Prefs/hds_user-linux/v2018.1/tasks/lattice_place_and_route.tsk new file mode 100644 index 0000000..d1f9f2e --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/lattice_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Lattice Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"LatticePARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/leonardospectrum.tsk b/Prefs/hds_user-linux/v2018.1/tasks/leonardospectrum.tsk new file mode 100644 index 0000000..3ab131f --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/leonardospectrum.tsk @@ -0,0 +1,101 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "LeonardoSpectrum" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Runs LeonardoSpectrum data preparation and invokes tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"$HDS_HOME/resources/tcl/plugins/dialogs/SpectrumCombinedDlg.tbc" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "LeonardoSpectrum Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Does data preparation for LeonardoSpectrum" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"SpectrumDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "LeonardoSpectrum Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Invokes the LeonardoSpectrum Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"SpectrumInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/leonardospectrum_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/leonardospectrum_flow.tsk new file mode 100644 index 0000000..fa1af05 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/leonardospectrum_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "LeonardoSpectrum Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire LeonardoSpectrum flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "LeonardoSpectrum" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:LeonardoSpectrum" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/modelsim_compile.tsk b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..6bf537f --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/modelsim_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..9e6f746 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,74 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "/usr/opt/Modelsim/modeltech/bin" +) +(preferedMap +preferedEnum 2 +preferedSetting "MODEL_SIM" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/modelsim_simulate.tsk b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..e11f828 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis.tsk b/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis.tsk new file mode 100644 index 0000000..e4a16ef --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis.tsk @@ -0,0 +1,101 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Runs Precision data preparation and invokes tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"$HDS_HOME/resources/tcl/plugins/dialogs/PrecisionSynthesisCombinedDlg.tbc" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Does data preparation for Precision Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"PrecisionSynthesisDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Invokes the Precision Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"PrecisionSynthesisInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis_flow.tsk new file mode 100644 index 0000000..3b1c63a --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Precision Synthesis flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Precision Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Precision Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_place_and_route.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_place_and_route.tsk new file mode 100644 index 0000000..1ba58ba --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_altera_quartus.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_prime_import.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_prime_import.tsk new file mode 100644 index 0000000..232d299 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_prime_import.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Prime Import" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_altera_quartus_prime.bmp" +hasBitmap 1 +tooltip "Import IP variations from Quartus Prime" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"\"%(p)\" %(library)" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QuartusPrimeImport" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_programmer.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_programmer.tsk new file mode 100644 index 0000000..a655174 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_programmer.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Programmer" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_programmer.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Programmer tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPGMInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis.tsk new file mode 100644 index 0000000..a40412d --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Quartus Synthesis data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_flow.tsk new file mode 100644 index 0000000..0210e0e --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Quartus QIS Synthesis flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Quartus Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Quartus Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_invoke.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_invoke.tsk new file mode 100644 index 0000000..cb4a2bc --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_invoke.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_prepare_data.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_prepare_data.tsk new file mode 100644 index 0000000..007bff2 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_prepare_data.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/questasim_compile.tsk b/Prefs/hds_user-linux/v2018.1/tasks/questasim_compile.tsk new file mode 100644 index 0000000..1cbe2b6 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/questasim_compile.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "QuestaSim Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_questasim_compile.bmp" +hasBitmap 1 +tooltip "Runs QuestaSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QuestaSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/questasim_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/questasim_flow.tsk new file mode 100644 index 0000000..3a2e9c1 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/questasim_flow.tsk @@ -0,0 +1,66 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "QuestaSim Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_questasim.bmp" +hasBitmap 1 +tooltip "Generate and run entire QuestaSim flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "QuestaSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:QuestaSim Compile" +) +(HDSTaskRef +TaskName "QuestaSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:QuestaSim Simulate" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/questasim_simulate.tsk b/Prefs/hds_user-linux/v2018.1/tasks/questasim_simulate.tsk new file mode 100644 index 0000000..9201889 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/questasim_simulate.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "QuestaSim Simulate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_questasim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the QuestaSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QuestaSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/register_assistant.tsk b/Prefs/hds_user-linux/v2018.1/tasks/register_assistant.tsk new file mode 100644 index 0000000..c2c17d0 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/register_assistant.tsk @@ -0,0 +1,45 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Register Assistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_registerassistant.bmp" +hasBitmap 1 +tooltip "Invokes Register Assistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"RegisterAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/svassistant_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/svassistant_flow.tsk new file mode 100644 index 0000000..466248c --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/svassistant_flow.tsk @@ -0,0 +1,78 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "SVAssistant Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SVAssistant Flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "SVAssistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SVAssistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"SvAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_core_generator.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_core_generator.tsk new file mode 100644 index 0000000..f7da1b9 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_core_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx CORE Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxcoregen.bmp" +hasBitmap 1 +tooltip "Creates Xilinx ISE CORE Generator components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxCoregen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_import.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_import.tsk new file mode 100644 index 0000000..16050ec --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_import.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Import" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_import.bmp" +hasBitmap 1 +tooltip "Import Existing Xilinx ISE Project into HDS" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxImport" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_place_and_route.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_place_and_route.tsk new file mode 100644 index 0000000..76ae08d --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_projnav.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ISEPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_platform_studio.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_platform_studio.tsk new file mode 100644 index 0000000..20d8090 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_platform_studio.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Platform Studio" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxplatstudio.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Xilinx Platform Studio" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxPlatStudio" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool.tsk new file mode 100644 index 0000000..a2db8d3 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Xilinx ISE Synthesis Tool data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XSTDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XSTInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool_flow.tsk new file mode 100644 index 0000000..7105fe5 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Xilinx Synthesis Tool flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Xilinx Synthesis Tool" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Xilinx Synthesis Tool" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_vivado_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_vivado_flow.tsk new file mode 100644 index 0000000..25c63cc --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_vivado_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Vivado Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "Generate and runs Xilinx Vivado wizard" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Vivado" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "HDS integration with Xilinx Vivado" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxVivado" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/templates/text_files/new_document.txt b/Prefs/hds_user-linux/v2018.1/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_combined/combined.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_entity/entity.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2015.2/hds_user_prefs b/Prefs/hds_user/v2015.2/hds_user_prefs new file mode 100644 index 0000000..3ecac1e --- /dev/null +++ b/Prefs/hds_user/v2015.2/hds_user_prefs @@ -0,0 +1,6011 @@ +version "45.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap 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a/Prefs/hds_user/v2015.2/tasks/generate.tsk b/Prefs/hds_user/v2015.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/Prefs/hds_user/v2015.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/Prefs/hds_user/v2015.2/tasks/modelsim_compile.tsk b/Prefs/hds_user/v2015.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/Prefs/hds_user/v2015.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" 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+preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user/v2015.2/tasks/modelsim_simulate.tsk b/Prefs/hds_user/v2015.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..6962f42 --- /dev/null +++ b/Prefs/hds_user/v2015.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2015.2/tasks/prepare_for_synthesis.tsk b/Prefs/hds_user/v2015.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/Prefs/hds_user/v2015.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2015.2/tasks/xilinx_project_navigator.tsk b/Prefs/hds_user/v2015.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/Prefs/hds_user/v2015.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2015.2/templates/text_files/new_document.txt b/Prefs/hds_user/v2015.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/Prefs/hds_user/v2015.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/Prefs/hds_user/v2015.2/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user/v2015.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2015.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2015.2/templates/vhdl_combined/combined.vhd b/Prefs/hds_user/v2015.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2015.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2015.2/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user/v2015.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2015.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2015.2/templates/vhdl_entity/entity.vhd b/Prefs/hds_user/v2015.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2015.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2015.2/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user/v2015.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2015.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2015.2/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user/v2015.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2015.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2018.1/hds_user_prefs b/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..c2c84cb --- /dev/null +++ b/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6826 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name 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+(SmartTableVPData_Column +name "Time Stamp" +width 120 +alignment 0 +) +(SmartTableVPData_Column +name "Requirement References" +width -1 +alignment 0 +) +] +filterNames [ +"Architectures and Modules" +"Configurations" +"Entities" +"Files" +"Packages" +"SV Classes" +"SV Interfaces" +"SV Packages" +"SV Program Blocks" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))" +) +] +WorkTabs [ +(WorkTab +name "Cursor" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Cursor" +primaryName "cursorCircuit" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "Cursor_test" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Cursor_test" +primaryName "cursor_tb" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "Board" +showingHierarchy 0 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(VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" 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+"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..6962f42 --- /dev/null +++ b/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) 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using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2019.2/hds_user_prefs b/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..23b555e --- /dev/null +++ b/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6487 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" 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"29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/Prefs/hds_user/v2019.2/tasks/generate.tsk b/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..6962f42 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt b/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/README.md b/README.md new file mode 100644 index 0000000..607f5e9 --- /dev/null +++ b/README.md @@ -0,0 +1,93 @@ +

+
+ ELN Cursor Logo +
+ ELN Project Cursor +
+

+ +

Labor Files for ELN Semester Project Cursor Moodle Cyberlearn.

+ +# Table of contents +

+ Description • + How To Use • + Credits • + License • + Find us on +

+ +![screenshot](img/screenshot.png) + +## Description +[(Back to top)](#table-of-contents) + +Laboratory file for semesterproject chronometer for first year bachelor students. + +As it changes each year, all you have to do is search on Moodle Cyberlearn for the course number and select the one starting with the last two digits of the current year. + +Course number is 2131 for SYND + +The course full name is composed as a concatenation of year (YY), school name, course ID and course name: "YY_HES-SO-VS_2131_Electricite / Elektrotechnik ELN" + +## How To Use +[(Back to top)](#table-of-contents) + +To clone and run this application, you'll need [Git](https://git-scm.com) and [HDL Designer](https://www.mentor.com/products/fpga/hdl_design/hdl_designer_series/) as well as [Modelsim](https://www.mentor.com/products/fv/modelsim/) installed on your computer. From your command line: + +![usage instructions](img/eln_labs_deployment-students.png) + +### Launch +```bash +# Change to location for the Sourcecode on your PC for Example Base of Drive U: +U: + +# Clone this repository +git clone https://github.com/hei-synd-2131-eln/eln_cursor.git + +# Go into the repository +cd eln_cursor + +# Run the app +## Linux +./eln_cursor.bash + +## Windows +.\eln_cursor.bat +``` + +### Update Student **Fork** to the latest modification from **Master** Repo +```bash +# goto your student fork repo location +cd u:\eln_cursor\ + +# add upstream Master remote +git remote add upstream https://github.com/hei-synd-2131-eln/eln_cursor.git + +# like "git pull" which is fetch + merge) +git fetch upstream +git merge upstream/master master + +# Push the changes into your own fork repo +git push origin master +``` + +## Credits +[(Back to top)](#table-of-contents) +* COF +* PRC +* ZAS + +## License +[(Back to top)](#table-of-contents) + +:copyright: [All rights reserved](LICENSE) + +--- + +## Find us on +> [hevs.ch](https://www.hevs.ch)  ·  +> Facebook [@hessovalais](https://www.facebook.com/hessovalais)  ·  +> Twitter [@hessovalais](https://twitter.com/hessovalais)  ·  +> LinkedIn [HES-SO Valais-Wallis](https://www.linkedin.com/groups/104343/)  ·  +> Youtube [HES-SO Valais-Wallis](https://www.youtube.com/user/HESSOVS) diff --git a/Scripts/cleanGenerated.bash b/Scripts/cleanGenerated.bash new file mode 100755 index 0000000..ca088c6 --- /dev/null +++ b/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/Scripts/cleanGenerated.bat b/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/Scripts/cleanScratch.bat b/Scripts/cleanScratch.bat new file mode 100644 index 0000000..132ac91 --- /dev/null +++ b/Scripts/cleanScratch.bat @@ -0,0 +1,38 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/Scripts/hdlDesigner.bash b/Scripts/hdlDesigner.bash new file mode 100755 index 0000000..4b54b46 --- /dev/null +++ b/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/Scripts/hdlDesigner.bat b/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..ee1e3ea --- /dev/null +++ b/Scripts/hdlDesigner.bat @@ -0,0 +1,246 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo "Search Commandline Parameters" +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo "%INDENT:"=%verbose enabled" + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo "%INDENT:"=%design_name=!design_name:"=! " + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo "%INDENT:"=%design_directory=!design_directory:"=! " + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo "%INDENT:"=%prefs_directory=!prefs_directory:"=! " + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo "%INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% " + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo "%INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% " + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo "%INDENT:"=%scratch_directory=%scratch_directory:"=% " + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo "%INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% " + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo "%INDENT:"=%library_matchings=%library_matchings:"=% " + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo "Program Parameters" + echo "%INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=%" + echo "%INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=%" + echo "%INDENT:"=%HDS_LIBS is %HDS_LIBS:"=%" + echo "%INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=%" + echo "%INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=%" + echo "%INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=%" + echo "%INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=%" + echo "%INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=%" + if %REQUIRE_HDS% == 1 ( + echo "%INDENT:"=%HDS_HOME is %HDS_HOME:"=%" + ) + if %REQUIRE_MODELSIM% == 1 ( + echo "%INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=%" + ) + if %REQUIRE_ISE% == 1 ( + echo "%INDENT:"=%ISE_HOME is %ISE_HOME:"=%" + echo "%INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=%" + echo "%INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=%" + ) + if %REQUIRE_LIBERO% == 1 ( + echo "%INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=%" + echo "%INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=%" + echo "%INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=%" + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo "%ISE_BASE_DIR:"=%" + echo " -> %ISE_WORK_DIR:"=%" + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo "%LIBERO_BASE_DIR:"=%" + echo " -> %LIBERO_BASE_DIR:"=%" + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo "%SEPARATOR:"=%" +echo "-- Launching program" +echo "%INDENT:"=%Waiting until programs finished..." +echo "-- Finished... YOU CAN CLOSE THIS WINDOW NOW!" +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start /wait !HDS_HOME!\bin\hdldesigner.exe +echo "%SEPARATOR:"=%" + +:end + popd + endlocal + pause&goto:eof + +::------------------------------------------------------------------------------ +:: Helper Functions +:: +:HELP + echo. + echo %usage1:"=% + echo %usage2:"=% + echo %usage3:"=% + echo %usage4:"=% + echo %usage5:"=% + echo.&pause&goto:eof diff --git a/Scripts/searchPaths.bat b/Scripts/searchPaths.bat new file mode 100644 index 0000000..2b8258c --- /dev/null +++ b/Scripts/searchPaths.bat @@ -0,0 +1,157 @@ +::============================================================================== +:: search_paths.bat - Search for Libraries and HDL Tools +:: + +:start + @echo off + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. + +echo "Search HEI Library" +::------------------------------------------------------------------------------ +:: Search HEI library directory +:: +if !REQUIRE_LIBS! == 1 ( + if "%HEI_LIBS_DIR%" == "" ( + set HEI_LIBS_DIR=%design_directory:"=!%\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for ET labs + set HEI_LIBS_DIR=R:\ETE\Ele1_8132\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for SI labs + set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + echo "ERROR: No valid libraries found: please verify your project setup." + pause&goto:end + ) + ) + ) + ) + ) + ) + if exist !HEI_LIBS_DIR!\ ( + echo "%INDENT:"=%Found HEI_LIBS_DIR at !HEI_LIBS_DIR:"=!" + ) else ( + echo "%INDENT:"=%ERROR: No valid HEI_LIBS_DIR found: please verify your HEI_LIBS_DIR settings." + pause&goto:eof + ) +) + + +echo "Search Design Tools: HDL Designer, Modelsim, Xilinx ISE, Microsemi Libero" +::------------------------------------------------------------------------------ +:: Search HDL Designer directory +:: +if !REQUIRE_HDS! == 1 ( + if "%HDS_HOME%" == "" ( + set HDS_HOME=C:\eda\MentorGraphics\HDS + if not exist !HDS_HOME!\ ( + set HDS_HOME=C:\tools\eda\HDS + if not exist !HDS_HOME!\ ( + echo "%INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings." + pause&goto:eof + ) + ) + ) + if exist !HDS_HOME! ( + echo "%INDENT:"=%Found HDL-Designer at !HDS_HOME!" + ) else ( + echo "%INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings." + pause&goto:eof + ) + ) +) + +::------------------------------------------------------------------------------ +:: Search Modelsim directory +:: +if !REQUIRE_MODELSIM! == 1 ( + if "%MODELSIM_HOME%" == "" ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + echo "%INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings." + pause&goto:eof + ) + ) + ) + ) + ) + if exist !MODELSIM_HOME! ( + echo "%INDENT:"=%Found ModelSim at !MODELSIM_HOME:"=!" + ) else ( + echo "%INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings." + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Xilinx ISE directory +:: + +if !REQUIRE_ISE! == 1 ( + if "%ISE_HOME%" == "" ( + set ISE_HOME=C:\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + set ISE_HOME=C:\tools\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + echo "%INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings." + pause&goto:eof + ) + ) + ) + if exist !ISE_HOME! ( + echo "%INDENT:"=%Found ISE at !ISE_HOME:"=!" + ) else ( + echo "%INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings." + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Microsemi Libero directory +:: +if %REQUIRE_LIBERO% == 1 ( + if "%LIBERO_HOME%" == "" ( + set LIBERO_HOME=C:\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + set LIBERO_HOME=C:\tools\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + echo "%INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings." + pause&goto:eof + ) + ) + ) + if exist !LIBERO_HOME! ( + echo "%INDENT:"=%Found Libero at !LIBERO_HOME:"=!" + ) else ( + echo "%INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings." + pause + goto:eof + ) +) + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + goto:eof \ No newline at end of file diff --git a/Scripts/start_libero.pl b/Scripts/start_libero.pl new file mode 100644 index 0000000..3e11301 --- /dev/null +++ b/Scripts/start_libero.pl @@ -0,0 +1,37 @@ +#!/usr/bin/perl +# filename: start_libero.pl +# created by: Corthay Francois & Zahno Silvan +# +#------------------------------------------------------------------------------- +# +# Description: +# Starts Libero in the correct timezone for the Synplify License +# Help Parameter : +# Parameter : start_libero.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : zas 08.2019 -- Initial release +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; + +#------------------------------------------------------------------------------- +# Launch Libero +# + +if ($verbose == 1) { + print "\n"; + print "launching $designerExe\n"; + print $indent, "project file spec: $liberoFileSpec\n"; + print "$separator\n"; +} + +system("$designerExe $liberoFileSpec"); \ No newline at end of file diff --git a/Scripts/trimLibs.pl b/Scripts/trimLibs.pl new file mode 100644 index 0000000..81500ed --- /dev/null +++ b/Scripts/trimLibs.pl @@ -0,0 +1,161 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [Franois Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ------------------------------------------------------------------------------ +# Changelog: +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/Scripts/update_ise.pl b/Scripts/update_ise.pl new file mode 100644 index 0000000..1ce5756 --- /dev/null +++ b/Scripts/update_ise.pl @@ -0,0 +1,91 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# update_ise +# replace ucf and vhd filelocation and name in the Xilinx xise project file +# Help Parameter : +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ +# Parameter : update_libero.pl <^PDC File Spec> +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : cof 12.2013 -- Initial release +# V0.2 : zas 08.2019 -- Changed actel to libero +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$pdcFileSpec = $ARGV[2]; + + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * liberoFileSpec: $liberoFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * pdcFileSpec: $pdcFileSpec\n"; +} + + + +#------------------------------------------------------------------------------- +# Project variables +# +$liberoWorkFileSpec = $liberoFileSpec . '.tmp'; + # source directory +my $sourceDir = "$ENV{CONCAT_DIR}"; +my $projectDir = "$ENV{LIBERO_WORK_DIR}"; + +#------------------------------------------------------------------------------- +# Update paths in the project file +# + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $liberoFileSpec\n"; + print $indent, "temporary file spec: $liberoWorkFileSpec\n"; +} +my $line; + +open(LiberoFile, $liberoFileSpec) || die "couldn't open $HDLFileSpec!"; +open(workFile, ">$liberoWorkFileSpec"); +while (chop($line = )) { + # replace source path + if ($line =~ m/DEFAULT_IMPORT_LOC/i) { + $line =~ s/".*"/"$sourceDir"/; + } + # replace project path + if ($line =~ m/ProjectLocation/i) { + $line =~ s/".*"/"$projectDir"/; + } + # replace VHDL file spec + if ($line =~ m/VALUE\s".*,hdl"/i) { + $line =~ s/".*"/"$vhdlFileSpec,hdl"/; + } + # replace PDC file spec + if ($line =~ m/VALUE\s".*\.pdc,pdc"/i) { + $line =~ s/".*"/"$pdcFileSpec,pdc"/; + } + + print workFile ("$line\n"); +} + +close(workFile); +close(LiberoFile); + + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($liberoFileSpec); +rename($liberoWorkFileSpec, $liberoFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#------------------------------------------------------------------------------- +# Launch Libero +# + +#if ($verbose == 1) { +# print "\n"; +# print "launching $designerExe\n"; +# print $indent, "project file spec: $liberoFileSpec\n"; +# print "$separator\n"; +#} + +#system("$designerExe $liberoFileSpec"); diff --git a/Simulation/cursor.do b/Simulation/cursor.do new file mode 100644 index 0000000..de78b85 --- /dev/null +++ b/Simulation/cursor.do @@ -0,0 +1,43 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group {reset and clock} /cursor_tb/reset +add wave -noupdate -group {reset and clock} /cursor_tb/clock +add wave -noupdate -group {reset and clock} /cursor_tb/testMode +add wave -noupdate -expand -group {Buttons and sensors} /cursor_tb/restart +add wave -noupdate -expand -group {Buttons and sensors} /cursor_tb/go1 +add wave -noupdate -expand -group {Buttons and sensors} /cursor_tb/go2 +add wave -noupdate -expand -group {Buttons and sensors} /cursor_tb/sensor1 +add wave -noupdate -expand -group {Buttons and sensors} /cursor_tb/sensor2 +add wave -noupdate -group Encoder /cursor_tb/encoderA +add wave -noupdate -group Encoder /cursor_tb/encoderB +add wave -noupdate -group Encoder /cursor_tb/encoderI +add wave -noupdate -expand -group Internals /cursor_tb/I_DUT/I_ctrl/current_state +add wave -noupdate -expand -group Internals -radix unsigned /cursor_tb/I_DUT/selectPosition +add wave -noupdate -expand -group Internals /cursor_tb/I_DUT/zeroSpeed +add wave -noupdate -expand -group Internals /cursor_tb/I_DUT/fullSpeed +add wave -noupdate -expand -group Internals /cursor_tb/I_DUT/rampEnable +add wave -noupdate -expand -group Internals /cursor_tb/I_DUT/endReached +add wave -noupdate -expand -group Internals -format Analog-Step -height 50 -max 255.0 -radix unsigned /cursor_tb/I_DUT/amplitude +add wave -noupdate -expand -group Internals -format Analog-Step -height 50 -max 14000.0 -radix unsigned /cursor_tb/I_DUT/position +add wave -noupdate -expand -group {Motor control} /cursor_tb/motorOn +add wave -noupdate -expand -group {Motor control} /cursor_tb/side1 +add wave -noupdate -expand -group {Motor control} /cursor_tb/side2 +add wave -noupdate /cursor_tb/I_DUT/testOut +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {18011924 ns} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 240 +configure wave -valuecolwidth 71 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ms +update +WaveRestoreZoom {0 ns} {21 ms} diff --git a/Simulation/divider.do b/Simulation/divider.do new file mode 100644 index 0000000..426d4da --- /dev/null +++ b/Simulation/divider.do @@ -0,0 +1,21 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /divider_tb/reset +add wave -noupdate -format Logic /divider_tb/clock +add wave -noupdate -format Logic /divider_tb/testmode +add wave -noupdate -format Logic /divider_tb/enlow +add wave -noupdate -format Logic /divider_tb/enpwm +add wave -noupdate -format Logic /divider_tb/start +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {0 ps} +WaveRestoreZoom {0 ps} {5250 us} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +run 10 ms diff --git a/Simulation/lcdFont.txt b/Simulation/lcdFont.txt new file mode 100644 index 0000000..2ab4422 --- /dev/null +++ b/Simulation/lcdFont.txt @@ -0,0 +1,128 @@ +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 +111000111011000000010000000000001110001111100011 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+010010000101010001010100010101000010000000000000 +000001000011111101000100010000000010000000000000 +001111000100000001000000001000000111110000000000 +000111000010000001000000001000000001110000000000 +001111000100000000110000010000000011110000000000 +010001000010100000010000001010000100010000000000 +000011000101000001010000010100000011110000000000 +010001000110010001010100010011000100010000000000 +000000000000100000110110010000010000000000000000 +000000000000000001111111000000000000000000000000 +000000000100000100110110000010000000000000000000 +000010000000100000101010000111000000100000000000 +000010000001110000101010000010000000100000000000 diff --git a/Simulation/positionCounter.do b/Simulation/positionCounter.do new file mode 100644 index 0000000..179e166 --- /dev/null +++ b/Simulation/positionCounter.do @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /positioncounter_tb/reset +add wave -noupdate -format Logic /positioncounter_tb/clock +add wave -noupdate -divider Controls +add wave -noupdate -format Logic /positioncounter_tb/clear +add wave -noupdate -divider Encoder +add wave -noupdate -format Logic /positioncounter_tb/i1/direction +add wave -noupdate -format Analog-Step -height 40 -radix unsigned -scale 0.20000000000000001 /positioncounter_tb/i1/stepcount +add wave -noupdate -format Logic /positioncounter_tb/encodera +add wave -noupdate -format Logic /positioncounter_tb/encoderb +add wave -noupdate -format Logic /positioncounter_tb/encoderi +add wave -noupdate -divider {Position counter} +add wave -noupdate -format Logic /positioncounter_tb/i0/risinga +add wave -noupdate -format Logic /positioncounter_tb/i0/fallinga +add wave -noupdate -format Logic /positioncounter_tb/i0/risingb +add wave -noupdate -format Logic /positioncounter_tb/i0/fallingb +add wave -noupdate -format Analog-Step -height 50 -radix unsigned -scale 0.10000000000000001 /positioncounter_tb/position +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {52123100 ps} +WaveRestoreZoom {0 ps} {210 us} +configure wave -namecolwidth 198 +configure wave -valuecolwidth 52 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +run 200 us \ No newline at end of file diff --git a/Simulation/pulseWidthModulator.do b/Simulation/pulseWidthModulator.do new file mode 100644 index 0000000..5f22850 --- /dev/null +++ b/Simulation/pulseWidthModulator.do @@ -0,0 +1,21 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /pulsewidthmodulator_tb/reset +add wave -noupdate -format Logic /pulsewidthmodulator_tb/clock +add wave -noupdate -format Literal -radix hexadecimal /pulsewidthmodulator_tb/amplitude +add wave -noupdate -format Logic /pulsewidthmodulator_tb/en +add wave -noupdate -format Analog-Step -height 40 -radix unsigned -scale 0.10000000000000001 /pulsewidthmodulator_tb/i0/counter +add wave -noupdate -format Logic /pulsewidthmodulator_tb/pwm +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {0 ps} +WaveRestoreZoom {0 ps} {2100 us} +configure wave -namecolwidth 200 +configure wave -valuecolwidth 50 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +run 1 ms diff --git a/Simulation/rampCounter.do b/Simulation/rampCounter.do new file mode 100644 index 0000000..3bf22bd --- /dev/null +++ b/Simulation/rampCounter.do @@ -0,0 +1,20 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /rampcounter_tb/reset +add wave -noupdate -format Logic /rampcounter_tb/clock +add wave -noupdate -format Logic /rampcounter_tb/en +add wave -noupdate -format Logic /rampcounter_tb/updown +add wave -noupdate -format Logic /rampcounter_tb/start +add wave -noupdate -format Analog-Step -height 40 -radix unsigned -scale 0.10000000000000001 /rampcounter_tb/ramp +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {76751300 ps} +WaveRestoreZoom {0 ps} {210 us} +configure wave -namecolwidth 195 +configure wave -valuecolwidth 55 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +run 200 us \ No newline at end of file diff --git a/doc/Board/cursor-chariot-assembly.pdf b/doc/Board/cursor-chariot-assembly.pdf new file mode 100644 index 0000000..4f71a59 --- /dev/null +++ b/doc/Board/cursor-chariot-assembly.pdf @@ -0,0 +1,11693 @@ +%PDF-1.4 % +6 0 obj <> endobj +xref +6 3035 +0000000016 00000 n +0000065083 00000 n +0000065159 00000 n +0000065350 00000 n +0000095503 00000 n +0000095549 00000 n +0000095596 00000 n +0000095642 00000 n +0000095688 00000 n +0000095735 00000 n +0000095781 00000 n +0000095828 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a/doc/evaluation-bewertung-cursor.pdf b/doc/evaluation-bewertung-cursor.pdf new file mode 100644 index 0000000..25ff065 Binary files /dev/null and b/doc/evaluation-bewertung-cursor.pdf differ diff --git a/doc/lcd-explanations.pdf b/doc/lcd-explanations.pdf new file mode 100644 index 0000000..3feecaa Binary files /dev/null and b/doc/lcd-explanations.pdf differ diff --git a/eln_cursor.bash b/eln_cursor.bash new file mode 100644 index 0000000..d170c47 --- /dev/null +++ b/eln_cursor.bash @@ -0,0 +1,32 @@ +#!/bin/bash +#=============================================================================== +# eln_labs.bash +# Starts HDL designer based on the generic hdlDesigner.bash +# + +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +hdl_script_name="$design_directory/../Scripts/hdlDesigner.bash" +export HEI_LIBS_DIR=/media/hei-students/SYND/Ele_2131/ELN/Labs/Libraries + +verbose=1 +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + + +#------------------------------------------------------------------------------- +# Main script +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Launching HDL Designer" + echo "${INDENT}Design name is $design_name" + echo "${INDENT}Start directory is $design_directory" + echo "${INDENT}HDL designer script is $hdl_script_name" +fi + +#------------------------------------------------------------------------------- +# Launch application +# +$hdl_script_name -v -d $design_directory -n $design_name diff --git a/eln_cursor.bat b/eln_cursor.bat new file mode 100644 index 0000000..e6f8d78 --- /dev/null +++ b/eln_cursor.bat @@ -0,0 +1,76 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=1 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 +set REQUIRE_ISE=1 +set REQUIRE_LIBERO=0 + +:: Set project name +set design_name=eln_cursor + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo.&goto:eof diff --git a/img/ELN_cursor.gif b/img/ELN_cursor.gif new file mode 100644 index 0000000..cfc15c6 Binary files /dev/null and b/img/ELN_cursor.gif differ diff --git a/img/ELN_cursor.png b/img/ELN_cursor.png new file mode 100644 index 0000000..a84a7cb Binary files /dev/null and b/img/ELN_cursor.png differ diff --git a/img/ELN_cursor.svg b/img/ELN_cursor.svg new file mode 100644 index 0000000..09d3cd8 --- /dev/null +++ b/img/ELN_cursor.svg @@ -0,0 +1,119 @@ + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + diff --git a/img/eln_labs_deployment-students.png b/img/eln_labs_deployment-students.png new file mode 100644 index 0000000..2f5a843 Binary files /dev/null and b/img/eln_labs_deployment-students.png differ diff --git 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