DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
itemName "ALL"
)
]
instances [
(Instance
name "rx1ToTx2"
duLibraryName "memory"
duName "fifoBridgeRxToTx"
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "fifoDepth"
type "positive"
value "fifoDepth"
)
(GiElement
name "firstWordFallThrough"
type "boolean"
value "firstWordFallThrough"
e "first byte written into the FIFO immediately appears on the output"
)
]
mwi 0
uid 1201,0
)
(Instance
name "rx2ToTx1"
duLibraryName "memory"
duName "fifoBridgeRxToTx"
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "fifoDepth"
type "positive"
value "fifoDepth"
)
(GiElement
name "firstWordFallThrough"
type "boolean"
value "firstWordFallThrough"
e "first byte written into the FIFO immediately appears on the output"
)
]
mwi 0
uid 1242,0
)
]
libraryRefs [
"ieee"
]
)
version "31.1"
appVersion "2018.1 (Build 12)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hdl"
)
(vvPair
variable "HDSDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
)
(vvPair
variable "SideDataDesignDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge/struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge/struct.bd.user"
)
(vvPair
variable "SourceDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge"
)
(vvPair
variable "d_logical"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifoBridge"
)
(vvPair
variable "date"
value "08/28/19"
)
(vvPair
variable "day"
value "Wed"
)
(vvPair
variable "day_long"
value "Wednesday"
)
(vvPair
variable "dd"
value "28"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "fifoBridge"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "francois"
)
(vvPair
variable "graphical_source_date"
value "08/28/19"
)
(vvPair
variable "graphical_source_group"
value "francois"
)
(vvPair
variable "graphical_source_host"
value "Aphelia"
)
(vvPair
variable "graphical_source_time"
value "13:45:16"
)
(vvPair
variable "group"
value "francois"
)
(vvPair
variable "host"
value "Aphelia"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "Memory"
)
(vvPair
variable "library_downstream_Concatenation"
value "U:/ELN_Board/Synthesis"
)
(vvPair
variable "library_downstream_Generic_1_file"
value "U:\\ELN_Board\\Synthesis"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/../Demo/designcheck"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Libs/Memory/work"
)
(vvPair
variable "library_downstream_SpyGlass"
value "U:\\ELN_Board\\Synthesis"
)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "fifoBridge"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge/struct.bd"
)
(vvPair
variable "p_logical"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifoBridge/struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$SCRATCH_DIR\\BoardTester\\Board\\ise"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME/modeltech/bin"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "13:45:16"
)
(vvPair
variable "unit"
value "fifoBridge"
)
(vvPair
variable "user"
value "francois"
)
(vvPair
variable "version"
value "2018.1 (Build 12)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2019"
)
(vvPair
variable "yy"
value "19"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 209,0
optionalChildren [
*1 (PortIoIn
uid 9,0
shape (CompositeShape
uid 10,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 11,0
sl 0
ro 270
xt "28000,20625,29500,21375"
)
(Line
uid 12,0
sl 0
ro 270
xt "29500,21000,30000,21000"
pts [
"29500,21000"
"30000,21000"
]
)
]
)
tg (WTG
uid 13,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "23500,20300,27000,21600"
st "clock"
ju 2
blo "27000,21300"
tm "WireNameMgr"
)
)
)
*2 (Net
uid 21,0
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
declText (MLText
uid 22,0
va (VaSet
font "courier,8,0"
)
xt "-1000,7200,10000,8100"
st "clock    : std_ulogic"
)
)
*3 (PortIoIn
uid 23,0
shape (CompositeShape
uid 24,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 25,0
sl 0
ro 270
xt "28000,22625,29500,23375"
)
(Line
uid 26,0
sl 0
ro 270
xt "29500,23000,30000,23000"
pts [
"29500,23000"
"30000,23000"
]
)
]
)
tg (WTG
uid 27,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 28,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "23500,22300,27000,23600"
st "reset"
ju 2
blo "27000,23300"
tm "WireNameMgr"
)
)
)
*4 (Net
uid 35,0
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
declText (MLText
uid 36,0
va (VaSet
font "courier,8,0"
)
xt "-1000,8100,10000,9000"
st "reset    : std_ulogic"
)
)
*5 (Grouping
uid 177,0
optionalChildren [
*6 (CommentText
uid 179,0
shape (Rectangle
uid 180,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "57000,65000,74000,66000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 181,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,65000,73400,66000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*7 (CommentText
uid 182,0
shape (Rectangle
uid 183,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "74000,61000,78000,62000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 184,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "74200,61000,77800,62000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*8 (CommentText
uid 185,0
shape (Rectangle
uid 186,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "57000,63000,74000,64000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 187,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,63000,73400,64000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*9 (CommentText
uid 188,0
shape (Rectangle
uid 189,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,63000,57000,64000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 190,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,63000,56800,64000"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*10 (CommentText
uid 191,0
shape (Rectangle
uid 192,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "74000,62000,94000,66000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 193,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "74200,62200,87400,63200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
)
*11 (CommentText
uid 194,0
shape (Rectangle
uid 195,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "78000,61000,94000,62000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 196,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "78200,61000,93800,62000"
st "
<enter project name here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
)
*12 (CommentText
uid 197,0
shape (Rectangle
uid 198,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,61000,74000,63000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 199,0
va (VaSet
fg "32768,0,0"
)
xt "59000,61500,68000,62500"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
)
*13 (CommentText
uid 200,0
shape (Rectangle
uid 201,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,64000,57000,65000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 202,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,64000,56200,65000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*14 (CommentText
uid 203,0
shape (Rectangle
uid 204,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,65000,57000,66000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 205,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,65000,56800,66000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*15 (CommentText
uid 206,0
shape (Rectangle
uid 207,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "57000,64000,74000,65000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 208,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,64000,72200,65000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
uid 178,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "53000,61000,94000,66000"
)
oxt "14000,66000,55000,71000"
)
*16 (PortIoOut
uid 774,0
shape (CompositeShape
uid 775,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 776,0
sl 0
ro 270
xt "62500,40625,64000,41375"
)
(Line
uid 777,0
sl 0
ro 270
xt "62000,41000,62500,41000"
pts [
"62000,41000"
"62500,41000"
]
)
]
)
tg (WTG
uid 778,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 779,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "65000,40500,68500,41800"
st "txWr1"
blo "65000,41500"
tm "WireNameMgr"
)
)
)
*17 (Net
uid 786,0
decl (Decl
n "txWr1"
t "std_ulogic"
o 13
suid 13,0
)
declText (MLText
uid 787,0
va (VaSet
font "courier,8,0"
)
xt "-1000,18000,10000,18900"
st "txWr1    : std_ulogic"
)
)
*18 (PortIoIn
uid 788,0
shape (CompositeShape
uid 789,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 790,0
sl 0
ro 270
xt "28000,12625,29500,13375"
)
(Line
uid 791,0
sl 0
ro 270
xt "29500,13000,30000,13000"
pts [
"29500,13000"
"30000,13000"
]
)
]
)
tg (WTG
uid 792,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 793,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "3900,12500,27000,13800"
st "rxData1 : (dataBitNb-1 DOWNTO 0)"
ju 2
blo "27000,13500"
tm "WireNameMgr"
)
)
)
*19 (Net
uid 800,0
decl (Decl
n "rxData1"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 3
suid 14,0
)
declText (MLText
uid 801,0
va (VaSet
font "courier,8,0"
)
xt "-1000,9000,24500,9900"
st "rxData1  : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*20 (PortIoOut
uid 802,0
shape (CompositeShape
uid 803,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 804,0
sl 0
ro 90
xt "28000,16625,29500,17375"
)
(Line
uid 805,0
sl 0
ro 90
xt "29500,17000,30000,17000"
pts [
"30000,17000"
"29500,17000"
]
)
]
)
tg (WTG
uid 806,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 807,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "23500,16300,27000,17600"
st "rxRd1"
ju 2
blo "27000,17300"
tm "WireNameMgr"
)
)
)
*21 (Net
uid 814,0
decl (Decl
n "rxRd1"
t "std_ulogic"
o 9
suid 15,0
)
declText (MLText
uid 815,0
va (VaSet
font "courier,8,0"
)
xt "-1000,14400,10000,15300"
st "rxRd1    : std_ulogic"
)
)
*22 (PortIoIn
uid 816,0
shape (CompositeShape
uid 817,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 818,0
sl 0
ro 90
xt "62500,38625,64000,39375"
)
(Line
uid 819,0
sl 0
ro 90
xt "62000,39000,62500,39000"
pts [
"62500,39000"
"62000,39000"
]
)
]
)
tg (WTG
uid 820,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 821,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "65000,38300,69900,39600"
st "txFull1"
blo "65000,39300"
tm "WireNameMgr"
)
)
)
*23 (Net
uid 828,0
decl (Decl
n "txFull1"
t "std_ulogic"
o 7
suid 16,0
)
declText (MLText
uid 829,0
va (VaSet
font "courier,8,0"
)
xt "-1000,12600,10000,13500"
st "txFull1  : std_ulogic"
)
)
*24 (PortIoIn
uid 830,0
shape (CompositeShape
uid 831,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 832,0
sl 0
ro 270
xt "28000,14625,29500,15375"
)
(Line
uid 833,0
sl 0
ro 270
xt "29500,15000,30000,15000"
pts [
"29500,15000"
"30000,15000"
]
)
]
)
tg (WTG
uid 834,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 835,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "21400,14500,27000,15800"
st "rxEmpty1"
ju 2
blo "27000,15500"
tm "WireNameMgr"
)
)
)
*25 (Net
uid 842,0
decl (Decl
n "rxEmpty1"
t "std_ulogic"
o 5
suid 17,0
)
declText (MLText
uid 843,0
va (VaSet
font "courier,8,0"
)
xt "-1000,10800,10000,11700"
st "rxEmpty1 : std_ulogic"
)
)
*26 (PortIoOut
uid 844,0
shape (CompositeShape
uid 845,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 846,0
sl 0
ro 270
xt "62500,36625,64000,37375"
)
(Line
uid 847,0
sl 0
ro 270
xt "62000,37000,62500,37000"
pts [
"62000,37000"
"62500,37000"
]
)
]
)
tg (WTG
uid 848,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 849,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "65000,36500,88100,37800"
st "txData1 : (dataBitNb-1 DOWNTO 0)"
blo "65000,37500"
tm "WireNameMgr"
)
)
)
*27 (Net
uid 856,0
decl (Decl
n "txData1"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 11
suid 18,0
)
declText (MLText
uid 857,0
va (VaSet
font "courier,8,0"
)
xt "-1000,16200,24500,17100"
st "txData1  : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*28 (PortIoOut
uid 858,0
shape (CompositeShape
uid 859,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 860,0
sl 0
ro 90
xt "28000,40625,29500,41375"
)
(Line
uid 861,0
sl 0
ro 90
xt "29500,41000,30000,41000"
pts [
"30000,41000"
"29500,41000"
]
)
]
)
tg (WTG
uid 862,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 863,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "23500,40300,27000,41600"
st "rxRd2"
ju 2
blo "27000,41300"
tm "WireNameMgr"
)
)
)
*29 (Net
uid 870,0
decl (Decl
n "rxRd2"
t "std_ulogic"
o 10
suid 19,0
)
declText (MLText
uid 871,0
va (VaSet
font "courier,8,0"
)
xt "-1000,15300,10000,16200"
st "rxRd2    : std_ulogic"
)
)
*30 (PortIoIn
uid 872,0
shape (CompositeShape
uid 873,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 874,0
sl 0
ro 270
xt "28000,36625,29500,37375"
)
(Line
uid 875,0
sl 0
ro 270
xt "29500,37000,30000,37000"
pts [
"29500,37000"
"30000,37000"
]
)
]
)
tg (WTG
uid 876,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 877,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "3900,36500,27000,37800"
st "rxData2 : (dataBitNb-1 DOWNTO 0)"
ju 2
blo "27000,37500"
tm "WireNameMgr"
)
)
)
*31 (Net
uid 884,0
decl (Decl
n "rxData2"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 20,0
)
declText (MLText
uid 885,0
va (VaSet
font "courier,8,0"
)
xt "-1000,9900,24500,10800"
st "rxData2  : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*32 (PortIoOut
uid 886,0
shape (CompositeShape
uid 887,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 888,0
sl 0
ro 270
xt "62500,12625,64000,13375"
)
(Line
uid 889,0
sl 0
ro 270
xt "62000,13000,62500,13000"
pts [
"62000,13000"
"62500,13000"
]
)
]
)
tg (WTG
uid 890,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 891,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "65000,12500,88100,13800"
st "txData2 : (dataBitNb-1 DOWNTO 0)"
blo "65000,13500"
tm "WireNameMgr"
)
)
)
*33 (Net
uid 898,0
decl (Decl
n "txData2"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 12
suid 21,0
)
declText (MLText
uid 899,0
va (VaSet
font "courier,8,0"
)
xt "-1000,17100,24500,18000"
st "txData2  : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*34 (PortIoIn
uid 900,0
shape (CompositeShape
uid 901,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 902,0
sl 0
ro 90
xt "62500,14625,64000,15375"
)
(Line
uid 903,0
sl 0
ro 90
xt "62000,15000,62500,15000"
pts [
"62500,15000"
"62000,15000"
]
)
]
)
tg (WTG
uid 904,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 905,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "65000,14300,69900,15600"
st "txFull2"
blo "65000,15300"
tm "WireNameMgr"
)
)
)
*35 (Net
uid 912,0
decl (Decl
n "txFull2"
t "std_ulogic"
o 8
suid 22,0
)
declText (MLText
uid 913,0
va (VaSet
font "courier,8,0"
)
xt "-1000,13500,10000,14400"
st "txFull2  : std_ulogic"
)
)
*36 (PortIoIn
uid 914,0
shape (CompositeShape
uid 915,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 916,0
sl 0
ro 270
xt "28000,38625,29500,39375"
)
(Line
uid 917,0
sl 0
ro 270
xt "29500,39000,30000,39000"
pts [
"29500,39000"
"30000,39000"
]
)
]
)
tg (WTG
uid 918,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 919,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "21400,38500,27000,39800"
st "rxEmpty2"
ju 2
blo "27000,39500"
tm "WireNameMgr"
)
)
)
*37 (Net
uid 926,0
decl (Decl
n "rxEmpty2"
t "std_ulogic"
o 6
suid 23,0
)
declText (MLText
uid 927,0
va (VaSet
font "courier,8,0"
)
xt "-1000,11700,10000,12600"
st "rxEmpty2 : std_ulogic"
)
)
*38 (PortIoOut
uid 928,0
shape (CompositeShape
uid 929,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 930,0
sl 0
ro 270
xt "62500,16625,64000,17375"
)
(Line
uid 931,0
sl 0
ro 270
xt "62000,17000,62500,17000"
pts [
"62000,17000"
"62500,17000"
]
)
]
)
tg (WTG
uid 932,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 933,0
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "65000,16500,68500,17800"
st "txWr2"
blo "65000,17500"
tm "WireNameMgr"
)
)
)
*39 (Net
uid 940,0
decl (Decl
n "txWr2"
t "std_ulogic"
o 14
suid 24,0
)
declText (MLText
uid 941,0
va (VaSet
font "courier,8,0"
)
xt "-1000,18900,10000,19800"
st "txWr2    : std_ulogic"
)
)
*40 (SaComponent
uid 1201,0
optionalChildren [
*41 (CptPort
uid 1169,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1170,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,20625,38000,21375"
)
tg (CPTG
uid 1171,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1172,0
va (VaSet
font "courier,9,0"
)
xt "39000,20400,41500,21300"
st "clock"
blo "39000,21100"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*42 (CptPort
uid 1173,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1174,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,22625,38000,23375"
)
tg (CPTG
uid 1175,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1176,0
va (VaSet
font "courier,9,0"
)
xt "39000,22400,41500,23300"
st "reset"
blo "39000,23100"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*43 (CptPort
uid 1177,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1178,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "54000,12625,54750,13375"
)
tg (CPTG
uid 1179,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1180,0
va (VaSet
font "courier,9,0"
)
xt "50500,12400,53000,13300"
st "data2"
ju 2
blo "53000,13100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data2"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 3
suid 3,0
)
)
)
*44 (CptPort
uid 1181,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1182,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "54000,14625,54750,15375"
)
tg (CPTG
uid 1183,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1184,0
va (VaSet
font "courier,9,0"
)
xt "50500,14400,53000,15300"
st "full2"
ju 2
blo "53000,15100"
)
)
thePort (LogicalPort
decl (Decl
n "full2"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*45 (CptPort
uid 1185,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1186,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "54000,16625,54750,17375"
)
tg (CPTG
uid 1187,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1188,0
va (VaSet
font "courier,9,0"
)
xt "51500,16400,53000,17300"
st "wr2"
ju 2
blo "53000,17100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wr2"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*46 (CptPort
uid 1189,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1190,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,14625,38000,15375"
)
tg (CPTG
uid 1191,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1192,0
va (VaSet
font "courier,9,0"
)
xt "39000,14400,42000,15300"
st "empty1"
blo "39000,15100"
)
)
thePort (LogicalPort
decl (Decl
n "empty1"
t "std_ulogic"
o 7
suid 6,0
)
)
)
*47 (CptPort
uid 1193,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1194,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,12625,38000,13375"
)
tg (CPTG
uid 1195,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1196,0
va (VaSet
font "courier,9,0"
)
xt "39000,12400,41500,13300"
st "data1"
blo "39000,13100"
)
)
thePort (LogicalPort
decl (Decl
n "data1"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 6
suid 7,0
)
)
)
*48 (CptPort
uid 1197,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1198,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,16625,38000,17375"
)
tg (CPTG
uid 1199,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1200,0
va (VaSet
font "courier,9,0"
)
xt "39000,16400,40500,17300"
st "rd1"
blo "39000,17100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rd1"
t "std_ulogic"
o 8
suid 8,0
)
)
)
]
shape (Rectangle
uid 1202,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "38000,9000,54000,25000"
)
oxt "35000,10000,51000,26000"
ttg (MlTextGroup
uid 1203,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*49 (Text
uid 1204,0
va (VaSet
font "courier,9,1"
)
xt "38600,24800,41600,25700"
st "memory"
blo "38600,25500"
tm "BdLibraryNameMgr"
)
*50 (Text
uid 1205,0
va (VaSet
font "courier,9,1"
)
xt "38600,26000,47100,26900"
st "fifoBridgeRxToTx"
blo "38600,26700"
tm "CptNameMgr"
)
*51 (Text
uid 1206,0
va (VaSet
font "courier,9,1"
)
xt "38600,27200,42600,28100"
st "rx1ToTx2"
blo "38600,27900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1207,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1208,0
text (MLText
uid 1209,0
va (VaSet
font "courier,8,0"
)
xt "38000,28400,103000,31100"
st "dataBitNb = dataBitNb    ( positive )  
fifoDepth = fifoDepth    ( positive )  
firstWordFallThrough = firstWordFallThrough    ( boolean  ) --first byte written into the FIFO immediately appears on the output "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "fifoDepth"
type "positive"
value "fifoDepth"
)
(GiElement
name "firstWordFallThrough"
type "boolean"
value "firstWordFallThrough"
e "first byte written into the FIFO immediately appears on the output"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*52 (SaComponent
uid 1242,0
optionalChildren [
*53 (CptPort
uid 1210,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1211,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,44625,38000,45375"
)
tg (CPTG
uid 1212,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1213,0
va (VaSet
font "courier,9,0"
)
xt "39000,44400,41500,45300"
st "clock"
blo "39000,45100"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*54 (CptPort
uid 1214,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1215,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,46625,38000,47375"
)
tg (CPTG
uid 1216,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1217,0
va (VaSet
font "courier,9,0"
)
xt "39000,46400,41500,47300"
st "reset"
blo "39000,47100"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*55 (CptPort
uid 1218,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1219,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "54000,36625,54750,37375"
)
tg (CPTG
uid 1220,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1221,0
va (VaSet
font "courier,9,0"
)
xt "50500,36400,53000,37300"
st "data2"
ju 2
blo "53000,37100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data2"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 3
suid 3,0
)
)
)
*56 (CptPort
uid 1222,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1223,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "54000,38625,54750,39375"
)
tg (CPTG
uid 1224,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1225,0
va (VaSet
font "courier,9,0"
)
xt "50500,38400,53000,39300"
st "full2"
ju 2
blo "53000,39100"
)
)
thePort (LogicalPort
decl (Decl
n "full2"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*57 (CptPort
uid 1226,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1227,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "54000,40625,54750,41375"
)
tg (CPTG
uid 1228,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1229,0
va (VaSet
font "courier,9,0"
)
xt "51500,40400,53000,41300"
st "wr2"
ju 2
blo "53000,41100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wr2"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*58 (CptPort
uid 1230,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1231,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,38625,38000,39375"
)
tg (CPTG
uid 1232,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1233,0
va (VaSet
font "courier,9,0"
)
xt "39000,38400,42000,39300"
st "empty1"
blo "39000,39100"
)
)
thePort (LogicalPort
decl (Decl
n "empty1"
t "std_ulogic"
o 7
suid 6,0
)
)
)
*59 (CptPort
uid 1234,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1235,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,36625,38000,37375"
)
tg (CPTG
uid 1236,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1237,0
va (VaSet
font "courier,9,0"
)
xt "39000,36400,41500,37300"
st "data1"
blo "39000,37100"
)
)
thePort (LogicalPort
decl (Decl
n "data1"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 6
suid 7,0
)
)
)
*60 (CptPort
uid 1238,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1239,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37250,40625,38000,41375"
)
tg (CPTG
uid 1240,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1241,0
va (VaSet
font "courier,9,0"
)
xt "39000,40400,40500,41300"
st "rd1"
blo "39000,41100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rd1"
t "std_ulogic"
o 8
suid 8,0
)
)
)
]
shape (Rectangle
uid 1243,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "38000,33000,54000,49000"
)
oxt "35000,10000,51000,26000"
ttg (MlTextGroup
uid 1244,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*61 (Text
uid 1245,0
va (VaSet
font "courier,9,1"
)
xt "38600,48800,41600,49700"
st "memory"
blo "38600,49500"
tm "BdLibraryNameMgr"
)
*62 (Text
uid 1246,0
va (VaSet
font "courier,9,1"
)
xt "38600,49700,47100,50600"
st "fifoBridgeRxToTx"
blo "38600,50400"
tm "CptNameMgr"
)
*63 (Text
uid 1247,0
va (VaSet
font "courier,9,1"
)
xt "38600,50600,42600,51500"
st "rx2ToTx1"
blo "38600,51300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1248,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1249,0
text (MLText
uid 1250,0
va (VaSet
font "courier,8,0"
)
xt "38000,52400,103000,55100"
st "dataBitNb = dataBitNb    ( positive )  
fifoDepth = fifoDepth    ( positive )  
firstWordFallThrough = firstWordFallThrough    ( boolean  ) --first byte written into the FIFO immediately appears on the output "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "fifoDepth"
type "positive"
value "fifoDepth"
)
(GiElement
name "firstWordFallThrough"
type "boolean"
value "firstWordFallThrough"
e "first byte written into the FIFO immediately appears on the output"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*64 (Wire
uid 15,0
shape (OrthoPolyLine
uid 16,0
va (VaSet
vasetType 3
)
xt "30000,21000,37250,21000"
pts [
"30000,21000"
"37250,21000"
]
)
start &1
end &41
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20,0
va (VaSet
font "courier,12,0"
)
xt "30000,19600,33500,20900"
st "clock"
blo "30000,20600"
tm "WireNameMgr"
)
)
on &2
)
*65 (Wire
uid 29,0
shape (OrthoPolyLine
uid 30,0
va (VaSet
vasetType 3
)
xt "30000,23000,37250,23000"
pts [
"30000,23000"
"37250,23000"
]
)
start &3
end &42
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 33,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 34,0
va (VaSet
font "courier,12,0"
)
xt "30000,21600,33500,22900"
st "reset"
blo "30000,22600"
tm "WireNameMgr"
)
)
on &4
)
*66 (Wire
uid 780,0
shape (OrthoPolyLine
uid 781,0
va (VaSet
vasetType 3
)
xt "54750,41000,62000,41000"
pts [
"54750,41000"
"62000,41000"
]
)
start &57
end &16
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 784,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 785,0
va (VaSet
font "courier,12,0"
)
xt "58000,39600,61500,40900"
st "txWr1"
blo "58000,40600"
tm "WireNameMgr"
)
)
on &17
)
*67 (Wire
uid 794,0
shape (OrthoPolyLine
uid 795,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "30000,13000,37250,13000"
pts [
"30000,13000"
"37250,13000"
]
)
start &18
end &47
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 798,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 799,0
va (VaSet
font "courier,12,0"
)
xt "30000,11600,34900,12900"
st "rxData1"
blo "30000,12600"
tm "WireNameMgr"
)
)
on &19
)
*68 (Wire
uid 808,0
shape (OrthoPolyLine
uid 809,0
va (VaSet
vasetType 3
)
xt "30000,17000,37250,17000"
pts [
"37250,17000"
"30000,17000"
]
)
start &48
end &20
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 812,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 813,0
va (VaSet
font "courier,12,0"
)
xt "30000,15600,33500,16900"
st "rxRd1"
blo "30000,16600"
tm "WireNameMgr"
)
)
on &21
)
*69 (Wire
uid 822,0
shape (OrthoPolyLine
uid 823,0
va (VaSet
vasetType 3
)
xt "54750,39000,62000,39000"
pts [
"62000,39000"
"54750,39000"
]
)
start &22
end &56
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 826,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 827,0
va (VaSet
font "courier,12,0"
)
xt "58000,37600,62900,38900"
st "txFull1"
blo "58000,38600"
tm "WireNameMgr"
)
)
on &23
)
*70 (Wire
uid 836,0
shape (OrthoPolyLine
uid 837,0
va (VaSet
vasetType 3
)
xt "30000,15000,37250,15000"
pts [
"30000,15000"
"37250,15000"
]
)
start &24
end &46
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 840,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 841,0
va (VaSet
font "courier,12,0"
)
xt "30000,13600,35600,14900"
st "rxEmpty1"
blo "30000,14600"
tm "WireNameMgr"
)
)
on &25
)
*71 (Wire
uid 850,0
shape (OrthoPolyLine
uid 851,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "54750,37000,62000,37000"
pts [
"54750,37000"
"62000,37000"
]
)
start &55
end &26
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 854,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 855,0
va (VaSet
font "courier,12,0"
)
xt "57000,35600,61900,36900"
st "txData1"
blo "57000,36600"
tm "WireNameMgr"
)
)
on &27
)
*72 (Wire
uid 864,0
shape (OrthoPolyLine
uid 865,0
va (VaSet
vasetType 3
)
xt "30000,41000,37250,41000"
pts [
"37250,41000"
"30000,41000"
]
)
start &60
end &28
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 868,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 869,0
va (VaSet
font "courier,12,0"
)
xt "30000,39600,33500,40900"
st "rxRd2"
blo "30000,40600"
tm "WireNameMgr"
)
)
on &29
)
*73 (Wire
uid 878,0
shape (OrthoPolyLine
uid 879,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "30000,37000,37250,37000"
pts [
"30000,37000"
"37250,37000"
]
)
start &30
end &59
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 882,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 883,0
va (VaSet
font "courier,12,0"
)
xt "30000,35600,34900,36900"
st "rxData2"
blo "30000,36600"
tm "WireNameMgr"
)
)
on &31
)
*74 (Wire
uid 892,0
shape (OrthoPolyLine
uid 893,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "54750,13000,62000,13000"
pts [
"54750,13000"
"62000,13000"
]
)
start &43
end &32
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 896,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 897,0
va (VaSet
font "courier,12,0"
)
xt "57000,11600,61900,12900"
st "txData2"
blo "57000,12600"
tm "WireNameMgr"
)
)
on &33
)
*75 (Wire
uid 906,0
shape (OrthoPolyLine
uid 907,0
va (VaSet
vasetType 3
)
xt "54750,15000,62000,15000"
pts [
"62000,15000"
"54750,15000"
]
)
start &34
end &44
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 910,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 911,0
va (VaSet
font "courier,12,0"
)
xt "58000,13600,62900,14900"
st "txFull2"
blo "58000,14600"
tm "WireNameMgr"
)
)
on &35
)
*76 (Wire
uid 920,0
shape (OrthoPolyLine
uid 921,0
va (VaSet
vasetType 3
)
xt "30000,39000,37250,39000"
pts [
"30000,39000"
"37250,39000"
]
)
start &36
end &58
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 924,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 925,0
va (VaSet
font "courier,12,0"
)
xt "30000,37600,35600,38900"
st "rxEmpty2"
blo "30000,38600"
tm "WireNameMgr"
)
)
on &37
)
*77 (Wire
uid 934,0
shape (OrthoPolyLine
uid 935,0
va (VaSet
vasetType 3
)
xt "54750,17000,62000,17000"
pts [
"54750,17000"
"62000,17000"
]
)
start &45
end &38
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 938,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 939,0
va (VaSet
font "courier,12,0"
)
xt "58000,15600,61500,16900"
st "txWr2"
blo "58000,16600"
tm "WireNameMgr"
)
)
on &39
)
*78 (Wire
uid 1099,0
shape (OrthoPolyLine
uid 1100,0
va (VaSet
vasetType 3
)
xt "34000,47000,37250,47000"
pts [
"34000,47000"
"37250,47000"
]
)
end &54
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1105,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1106,0
va (VaSet
font "courier,12,0"
)
xt "32000,45600,35500,46900"
st "reset"
blo "32000,46600"
tm "WireNameMgr"
)
)
on &4
)
*79 (Wire
uid 1107,0
shape (OrthoPolyLine
uid 1108,0
va (VaSet
vasetType 3
)
xt "34000,45000,37250,45000"
pts [
"34000,45000"
"37250,45000"
]
)
end &53
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1113,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1114,0
va (VaSet
font "courier,12,0"
)
xt "32000,43600,35500,44900"
st "clock"
blo "32000,44600"
tm "WireNameMgr"
)
)
on &2
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *80 (PackageList
uid 210,0
stg "VerticalLayoutStrategy"
textVec [
*81 (Text
uid 211,0
va (VaSet
font "courier,8,1"
)
xt "-3000,0,3500,900"
st "Package List"
blo "-3000,700"
)
*82 (MLText
uid 212,0
va (VaSet
)
xt "-3000,1000,15600,4000"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 213,0
stg "VerticalLayoutStrategy"
textVec [
*83 (Text
uid 214,0
va (VaSet
isHidden 1
font "courier,8,1"
)
xt "20000,0,30000,900"
st "Compiler Directives"
blo "20000,700"
)
*84 (Text
uid 215,0
va (VaSet
isHidden 1
font "courier,8,1"
)
xt "20000,1000,31500,1900"
st "Pre-module directives:"
blo "20000,1700"
)
*85 (MLText
uid 216,0
va (VaSet
isHidden 1
)
xt "20000,2000,32000,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*86 (Text
uid 217,0
va (VaSet
isHidden 1
font "courier,8,1"
)
xt "20000,4000,32000,4900"
st "Post-module directives:"
blo "20000,4700"
)
*87 (MLText
uid 218,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*88 (Text
uid 219,0
va (VaSet
isHidden 1
font "courier,8,1"
)
xt "20000,5000,31500,5900"
st "End-module directives:"
blo "20000,5700"
)
*89 (MLText
uid 220,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "367,41,1424,909"
viewArea "-4497,-1499,104998,72675"
cachedDiagramExtent "-3000,0,103000,66000"
pageSetupInfo (PageSetupInfo
ptrCmd ""
toPrinter 1
xMargin 48
yMargin 48
paperWidth 595
paperHeight 842
unixPaperWidth 595
unixPaperHeight 842
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4  (210mm x 297mm)"
unixPaperName "A4  (210mm x 297mm)"
windowsPaperName "A4"
scale 75
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "-3000,0"
lastUid 1358,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,2600,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "courier,8,0"
)
xt "450,2150,1450,3050"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "courier,10,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*90 (Text
va (VaSet
)
xt "2450,3500,5550,4500"
st "<library>"
blo "2450,4300"
tm "BdLibraryNameMgr"
)
*91 (Text
va (VaSet
)
xt "2450,4500,5150,5500"
st "<block>"
blo "2450,5300"
tm "BlkNameMgr"
)
*92 (Text
va (VaSet
)
xt "2450,5500,3050,6500"
st "I0"
blo "2450,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "2450,13500,2450,13500"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*93 (Text
va (VaSet
)
xt "1000,3500,3300,4500"
st "Library"
blo "1000,4300"
)
*94 (Text
va (VaSet
)
xt "1000,4500,7000,5500"
st "MWComponent"
blo "1000,5300"
)
*95 (Text
va (VaSet
)
xt "1000,5500,1600,6500"
st "I0"
blo "1000,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6000,1500,-6000,1500"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*96 (Text
va (VaSet
)
xt "1250,3500,3550,4500"
st "Library"
blo "1250,4300"
tm "BdLibraryNameMgr"
)
*97 (Text
va (VaSet
)
xt "1250,4500,6750,5500"
st "SaComponent"
blo "1250,5300"
tm "CptNameMgr"
)
*98 (Text
va (VaSet
)
xt "1250,5500,1850,6500"
st "I0"
blo "1250,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-5750,1500,-5750,1500"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*99 (Text
va (VaSet
)
xt "950,3500,3250,4500"
st "Library"
blo "950,4300"
)
*100 (Text
va (VaSet
)
xt "950,4500,7050,5500"
st "VhdlComponent"
blo "950,5300"
)
*101 (Text
va (VaSet
)
xt "950,5500,1550,6500"
st "I0"
blo "950,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6050,1500,-6050,1500"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-50,0,8050,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*102 (Text
va (VaSet
)
xt "450,3500,2750,4500"
st "Library"
blo "450,4300"
)
*103 (Text
va (VaSet
)
xt "450,4500,7550,5500"
st "VerilogComponent"
blo "450,5300"
)
*104 (Text
va (VaSet
)
xt "450,5500,1050,6500"
st "I0"
blo "450,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6550,1500,-6550,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*105 (Text
va (VaSet
)
xt "3400,4000,4600,5000"
st "eb1"
blo "3400,4800"
tm "HdlTextNameMgr"
)
*106 (Text
va (VaSet
)
xt "3400,5000,3800,6000"
st "1"
blo "3400,5800"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2600,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "courier,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1200,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,50000"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
xt "0,0,5400,1000"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1000,10800,2000"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,17400,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*107 (Text
va (VaSet
font "courier,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*108 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,10800,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*109 (Text
va (VaSet
font "courier,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*110 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "courier,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "courier,8,1"
)
xt "-3000,5400,3500,6300"
st "Declarations"
blo "-3000,6100"
)
portLabel (Text
uid 3,0
va (VaSet
font "courier,8,1"
)
xt "-3000,6300,0,7200"
st "Ports:"
blo "-3000,7000"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "courier,8,1"
)
xt "-3000,19800,1500,20700"
st "Pre User:"
blo "-3000,20500"
)
preUserText (MLText
uid 5,0
va (VaSet
font "courier,8,0"
)
xt "-3000,5400,-3000,5400"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "courier,8,1"
)
xt "-3000,20700,5500,21600"
st "Diagram Signals:"
blo "-3000,21400"
)
postUserLabel (Text
uid 7,0
va (VaSet
font "courier,8,1"
)
xt "-3000,21600,2500,22500"
st "Post User:"
blo "-3000,22300"
)
postUserText (MLText
uid 8,0
va (VaSet
font "courier,8,0"
)
xt "-3000,5400,-3000,5400"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 24,0
usingSuid 1
emptyRow *111 (LEmptyRow
)
uid 652,0
optionalChildren [
*112 (RefLabelRowHdr
)
*113 (TitleRowHdr
)
*114 (FilterRowHdr
)
*115 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*116 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*117 (GroupColHdr
tm "GroupColHdrMgr"
)
*118 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*119 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*120 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*121 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*122 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*123 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*124 (LeafLogPort
port (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
uid 627,0
)
*125 (LeafLogPort
port (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
)
uid 629,0
)
*126 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "txWr1"
t "std_ulogic"
o 13
suid 13,0
)
)
uid 751,0
)
*127 (LeafLogPort
port (LogicalPort
decl (Decl
n "rxData1"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 3
suid 14,0
)
)
uid 753,0
)
*128 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "rxRd1"
t "std_ulogic"
o 9
suid 15,0
)
)
uid 755,0
)
*129 (LeafLogPort
port (LogicalPort
decl (Decl
n "txFull1"
t "std_ulogic"
o 7
suid 16,0
)
)
uid 757,0
)
*130 (LeafLogPort
port (LogicalPort
decl (Decl
n "rxEmpty1"
t "std_ulogic"
o 5
suid 17,0
)
)
uid 759,0
)
*131 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "txData1"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 11
suid 18,0
)
)
uid 761,0
)
*132 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "rxRd2"
t "std_ulogic"
o 10
suid 19,0
)
)
uid 763,0
)
*133 (LeafLogPort
port (LogicalPort
decl (Decl
n "rxData2"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 20,0
)
)
uid 765,0
)
*134 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "txData2"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 12
suid 21,0
)
)
uid 767,0
)
*135 (LeafLogPort
port (LogicalPort
decl (Decl
n "txFull2"
t "std_ulogic"
o 8
suid 22,0
)
)
uid 769,0
)
*136 (LeafLogPort
port (LogicalPort
decl (Decl
n "rxEmpty2"
t "std_ulogic"
o 6
suid 23,0
)
)
uid 771,0
)
*137 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "txWr2"
t "std_ulogic"
o 14
suid 24,0
)
)
uid 773,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 665,0
optionalChildren [
*138 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *139 (MRCItem
litem &111
pos 14
dimension 20
)
uid 667,0
optionalChildren [
*140 (MRCItem
litem &112
pos 0
dimension 20
uid 668,0
)
*141 (MRCItem
litem &113
pos 1
dimension 23
uid 669,0
)
*142 (MRCItem
litem &114
pos 2
hidden 1
dimension 20
uid 670,0
)
*143 (MRCItem
litem &124
pos 0
dimension 20
uid 628,0
)
*144 (MRCItem
litem &125
pos 1
dimension 20
uid 630,0
)
*145 (MRCItem
litem &126
pos 6
dimension 20
uid 750,0
)
*146 (MRCItem
litem &127
pos 3
dimension 20
uid 752,0
)
*147 (MRCItem
litem &128
pos 5
dimension 20
uid 754,0
)
*148 (MRCItem
litem &129
pos 4
dimension 20
uid 756,0
)
*149 (MRCItem
litem &130
pos 2
dimension 20
uid 758,0
)
*150 (MRCItem
litem &131
pos 7
dimension 20
uid 760,0
)
*151 (MRCItem
litem &132
pos 8
dimension 20
uid 762,0
)
*152 (MRCItem
litem &133
pos 9
dimension 20
uid 764,0
)
*153 (MRCItem
litem &134
pos 10
dimension 20
uid 766,0
)
*154 (MRCItem
litem &135
pos 11
dimension 20
uid 768,0
)
*155 (MRCItem
litem &136
pos 12
dimension 20
uid 770,0
)
*156 (MRCItem
litem &137
pos 13
dimension 20
uid 772,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
)
uid 671,0
optionalChildren [
*157 (MRCItem
litem &115
pos 0
dimension 20
uid 672,0
)
*158 (MRCItem
litem &117
pos 1
dimension 50
uid 673,0
)
*159 (MRCItem
litem &118
pos 2
dimension 100
uid 674,0
)
*160 (MRCItem
litem &119
pos 3
dimension 50
uid 675,0
)
*161 (MRCItem
litem &120
pos 4
dimension 100
uid 676,0
)
*162 (MRCItem
litem &121
pos 5
dimension 100
uid 677,0
)
*163 (MRCItem
litem &122
pos 6
dimension 50
uid 678,0
)
*164 (MRCItem
litem &123
pos 7
dimension 80
uid 679,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 666,0
vaOverrides [
]
)
]
)
uid 651,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *165 (LEmptyRow
)
uid 681,0
optionalChildren [
*166 (RefLabelRowHdr
)
*167 (TitleRowHdr
)
*168 (FilterRowHdr
)
*169 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*170 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*171 (GroupColHdr
tm "GroupColHdrMgr"
)
*172 (NameColHdr
tm "GenericNameColHdrMgr"
)
*173 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*174 (InitColHdr
tm "GenericValueColHdrMgr"
)
*175 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*176 (EolColHdr
tm "GenericEolColHdrMgr"
)
*177 (LogGeneric
generic (GiElement
name "dataBitNb"
type "positive"
value "8"
)
uid 716,0
)
*178 (LogGeneric
generic (GiElement
name "fifoDepth"
type "positive"
value "8"
)
uid 718,0
)
*179 (LogGeneric
generic (GiElement
name "firstWordFallThrough"
type "boolean"
value "false"
e "first byte written into the FIFO immediately appears on the output"
)
uid 1428,0
)
]
)
pdm (PhysicalDM
uid 693,0
optionalChildren [
*180 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *181 (MRCItem
litem &165
pos 2
dimension 20
)
uid 695,0
optionalChildren [
*182 (MRCItem
litem &166
pos 0
dimension 20
uid 696,0
)
*183 (MRCItem
litem &167
pos 1
dimension 23
uid 697,0
)
*184 (MRCItem
litem &168
pos 2
hidden 1
dimension 20
uid 698,0
)
*185 (MRCItem
litem &177
pos 0
dimension 20
uid 715,0
)
*186 (MRCItem
litem &178
pos 1
dimension 20
uid 717,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
)
uid 699,0
optionalChildren [
*187 (MRCItem
litem &169
pos 0
dimension 20
uid 700,0
)
*188 (MRCItem
litem &171
pos 1
dimension 50
uid 701,0
)
*189 (MRCItem
litem &172
pos 2
dimension 100
uid 702,0
)
*190 (MRCItem
litem &173
pos 3
dimension 100
uid 703,0
)
*191 (MRCItem
litem &174
pos 4
dimension 50
uid 704,0
)
*192 (MRCItem
litem &175
pos 5
dimension 50
uid 705,0
)
*193 (MRCItem
litem &176
pos 6
dimension 80
uid 706,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 694,0
vaOverrides [
]
)
]
)
uid 680,0
type 1
)
activeModelName "BlockDiag"
)