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blo "33910,88500"
tm "BdLibraryNameMgr"
)
*22 (Text
uid 1665,0
va (VaSet
isHidden 1
)
xt "33910,88700,38710,89700"
st "inverter"
blo "33910,89500"
tm "CptNameMgr"
)
*23 (Text
uid 1666,0
va (VaSet
)
xt "33910,88700,35110,89700"
st "I1"
blo "33910,89500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1667,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1668,0
text (MLText
uid 1669,0
va (VaSet
isHidden 1
)
xt "33000,95400,46400,96600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*24 (Net
uid 2135,0
decl (Decl
n "testMode"
t "std_uLogic"
o 12
suid 4,0
)
declText (MLText
uid 2136,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,46000,11900,47000"
st "testMode      : std_uLogic"
)
)
*25 (PortIoIn
uid 2167,0
shape (CompositeShape
uid 2168,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2169,0
sl 0
ro 270
xt "26000,47625,27500,48375"
)
(Line
uid 2170,0
sl 0
ro 270
xt "27500,48000,28000,48000"
pts [
"27500,48000"
"28000,48000"
]
)
]
)
tg (WTG
uid 2171,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2172,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "20200,47300,25000,48700"
st "go2_n"
ju 2
blo "25000,48500"
tm "WireNameMgr"
)
s (Text
uid 2173,0
va (VaSet
)
xt "20200,48700,20200,48700"
ju 2
blo "20200,48700"
tm "SignalTypeMgr"
)
)
)
*26 (PortIoIn
uid 2174,0
shape (CompositeShape
uid 2175,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2176,0
sl 0
ro 270
xt "26000,59625,27500,60375"
)
(Line
uid 2177,0
sl 0
ro 270
xt "27500,60000,28000,60000"
pts [
"27500,60000"
"28000,60000"
]
)
]
)
tg (WTG
uid 2178,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2179,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "17600,59300,25000,60700"
st "button4_n"
ju 2
blo "25000,60500"
tm "WireNameMgr"
)
s (Text
uid 2180,0
va (VaSet
)
xt "17600,60700,17600,60700"
ju 2
blo "17600,60700"
tm "SignalTypeMgr"
)
)
)
*27 (PortIoIn
uid 2181,0
shape (CompositeShape
uid 2182,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2183,0
sl 0
ro 270
xt "26000,23625,27500,24375"
)
(Line
uid 2184,0
sl 0
ro 270
xt "27500,24000,28000,24000"
pts [
"27500,24000"
"28000,24000"
]
)
]
)
tg (WTG
uid 2185,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2186,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "18300,23300,25000,24700"
st "restart_n"
ju 2
blo "25000,24500"
tm "WireNameMgr"
)
s (Text
uid 2187,0
va (VaSet
)
xt "18300,24700,18300,24700"
ju 2
blo "18300,24700"
tm "SignalTypeMgr"
)
)
)
*28 (PortIoIn
uid 2188,0
shape (CompositeShape
uid 2189,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2190,0
sl 0
ro 270
xt "26000,75625,27500,76375"
)
(Line
uid 2191,0
sl 0
ro 270
xt "27500,76000,28000,76000"
pts [
"27500,76000"
"28000,76000"
]
)
]
)
tg (WTG
uid 2192,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2193,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "18300,75300,25000,76700"
st "testMode"
ju 2
blo "25000,76500"
tm "WireNameMgr"
)
s (Text
uid 2194,0
va (VaSet
)
xt "18300,76700,18300,76700"
ju 2
blo "18300,76700"
tm "SignalTypeMgr"
)
)
)
*29 (SaComponent
uid 2212,0
optionalChildren [
*30 (CptPort
uid 2195,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2196,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,47625,41000,48375"
)
tg (CPTG
uid 2197,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2198,0
va (VaSet
)
xt "42000,47300,42600,48300"
st "D"
blo "42000,48100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*31 (CptPort
uid 2199,0
optionalChildren [
*32 (FFT
pts [
"41750,52000"
"41000,52375"
"41000,51625"
]
uid 2203,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,51625,41750,52375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2200,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,51625,41000,52375"
)
tg (CPTG
uid 2201,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2202,0
va (VaSet
)
xt "42000,51400,43800,52400"
st "CLK"
blo "42000,52200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*33 (CptPort
uid 2204,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2205,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "43625,54000,44375,54750"
)
tg (CPTG
uid 2206,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2207,0
va (VaSet
)
xt "43000,52600,44800,53600"
st "CLR"
blo "43000,53400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*34 (CptPort
uid 2208,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2209,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "47000,47625,47750,48375"
)
tg (CPTG
uid 2210,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2211,0
va (VaSet
)
xt "45400,47300,46000,48300"
st "Q"
ju 2
blo "46000,48100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 2213,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,46000,47000,54000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2214,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*35 (Text
uid 2215,0
va (VaSet
)
xt "44600,53700,51200,54700"
st "sequential"
blo "44600,54500"
tm "BdLibraryNameMgr"
)
*36 (Text
uid 2216,0
va (VaSet
)
xt "44600,54700,46400,55700"
st "DFF"
blo "44600,55500"
tm "CptNameMgr"
)
*37 (Text
uid 2217,0
va (VaSet
)
xt "44600,55700,45800,56700"
st "I2"
blo "44600,56500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2218,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2219,0
text (MLText
uid 2220,0
va (VaSet
isHidden 1
)
xt "48000,53400,61400,54600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*38 (SaComponent
uid 2262,0
optionalChildren [
*39 (CptPort
uid 2271,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2272,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,59625,41000,60375"
)
tg (CPTG
uid 2273,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2274,0
va (VaSet
)
xt "42000,59300,42600,60300"
st "D"
blo "42000,60100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*40 (CptPort
uid 2275,0
optionalChildren [
*41 (FFT
pts [
"41750,64000"
"41000,64375"
"41000,63625"
]
uid 2279,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,63625,41750,64375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2276,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,63625,41000,64375"
)
tg (CPTG
uid 2277,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2278,0
va (VaSet
)
xt "42000,63400,43800,64400"
st "CLK"
blo "42000,64200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*42 (CptPort
uid 2280,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2281,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "43625,66000,44375,66750"
)
tg (CPTG
uid 2282,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2283,0
va (VaSet
)
xt "43000,64600,44800,65600"
st "CLR"
blo "43000,65400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*43 (CptPort
uid 2284,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2285,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "47000,59625,47750,60375"
)
tg (CPTG
uid 2286,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2287,0
va (VaSet
)
xt "45400,59300,46000,60300"
st "Q"
ju 2
blo "46000,60100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 2263,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,58000,47000,66000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2264,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*44 (Text
uid 2265,0
va (VaSet
)
xt "44600,65700,51200,66700"
st "sequential"
blo "44600,66500"
tm "BdLibraryNameMgr"
)
*45 (Text
uid 2266,0
va (VaSet
)
xt "44600,66700,46400,67700"
st "DFF"
blo "44600,67500"
tm "CptNameMgr"
)
*46 (Text
uid 2267,0
va (VaSet
)
xt "44600,67700,45800,68700"
st "I3"
blo "44600,68500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2268,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2269,0
text (MLText
uid 2270,0
va (VaSet
isHidden 1
)
xt "48000,65400,61400,66600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*47 (SaComponent
uid 2306,0
optionalChildren [
*48 (CptPort
uid 2315,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2316,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,23625,41000,24375"
)
tg (CPTG
uid 2317,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2318,0
va (VaSet
)
xt "42000,23300,42600,24300"
st "D"
blo "42000,24100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*49 (CptPort
uid 2319,0
optionalChildren [
*50 (FFT
pts [
"41750,28000"
"41000,28375"
"41000,27625"
]
uid 2323,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,27625,41750,28375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2320,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,27625,41000,28375"
)
tg (CPTG
uid 2321,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2322,0
va (VaSet
)
xt "42000,27400,43800,28400"
st "CLK"
blo "42000,28200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*51 (CptPort
uid 2324,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2325,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "43625,30000,44375,30750"
)
tg (CPTG
uid 2326,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2327,0
va (VaSet
)
xt "43000,28600,44800,29600"
st "CLR"
blo "43000,29400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*52 (CptPort
uid 2328,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2329,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "47000,23625,47750,24375"
)
tg (CPTG
uid 2330,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2331,0
va (VaSet
)
xt "45400,23300,46000,24300"
st "Q"
ju 2
blo "46000,24100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 2307,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,22000,47000,30000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2308,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*53 (Text
uid 2309,0
va (VaSet
)
xt "44600,29700,51200,30700"
st "sequential"
blo "44600,30500"
tm "BdLibraryNameMgr"
)
*54 (Text
uid 2310,0
va (VaSet
)
xt "44600,30700,46400,31700"
st "DFF"
blo "44600,31500"
tm "CptNameMgr"
)
*55 (Text
uid 2311,0
va (VaSet
)
xt "44600,31700,45800,32700"
st "I4"
blo "44600,32500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2312,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2313,0
text (MLText
uid 2314,0
va (VaSet
isHidden 1
)
xt "48000,29400,61400,30600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*56 (PortIoIn
uid 2354,0
shape (CompositeShape
uid 2355,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2356,0
sl 0
ro 90
xt "120500,63625,122000,64375"
)
(Line
uid 2357,0
sl 0
ro 90
xt "120000,64000,120500,64000"
pts [
"120500,64000"
"120000,64000"
]
)
]
)
tg (WTG
uid 2358,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2359,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,63300,130500,64700"
st "sensor2_n"
blo "123000,64500"
tm "WireNameMgr"
)
s (Text
uid 2360,0
va (VaSet
)
xt "123000,64700,123000,64700"
blo "123000,64700"
tm "SignalTypeMgr"
)
)
)
*57 (SaComponent
uid 2361,0
optionalChildren [
*58 (CptPort
uid 2370,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2371,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,63625,103750,64375"
)
tg (CPTG
uid 2372,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2373,0
va (VaSet
)
xt "101400,63300,102000,64300"
st "D"
ju 2
blo "102000,64100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*59 (CptPort
uid 2374,0
optionalChildren [
*60 (FFT
pts [
"102250,68000"
"103000,67625"
"103000,68375"
]
uid 2378,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "102250,67625,103000,68375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2375,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,67625,103750,68375"
)
tg (CPTG
uid 2376,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2377,0
va (VaSet
)
xt "100200,67400,102000,68400"
st "CLK"
ju 2
blo "102000,68200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*61 (CptPort
uid 2379,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2380,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "99625,70000,100375,70750"
)
tg (CPTG
uid 2381,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2382,0
va (VaSet
)
xt "98600,68600,100400,69600"
st "CLR"
blo "98600,69400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*62 (CptPort
uid 2383,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2384,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "96250,63625,97000,64375"
)
tg (CPTG
uid 2385,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2386,0
va (VaSet
)
xt "98000,63300,98600,64300"
st "Q"
blo "98000,64100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 2362,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,62000,103000,70000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2363,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*63 (Text
uid 2364,0
va (VaSet
)
xt "95600,69700,102200,70700"
st "sequential"
blo "95600,70500"
tm "BdLibraryNameMgr"
)
*64 (Text
uid 2365,0
va (VaSet
)
xt "95600,70700,97400,71700"
st "DFF"
blo "95600,71500"
tm "CptNameMgr"
)
*65 (Text
uid 2366,0
va (VaSet
)
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t "std_uLogic"
o 2
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xt "45400,81300,46000,82300"
st "Q"
ju 2
blo "46000,82100"
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thePort (LogicalPort
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decl (Decl
n "Q"
t "std_uLogic"
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]
shape (Rectangle
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xt "41000,80000,47000,88000"
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va (VaSet
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st "sequential"
blo "44600,88500"
tm "BdLibraryNameMgr"
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va (VaSet
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st "DFF"
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va (VaSet
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xt "44600,89700,45800,90700"
st "I6"
blo "44600,90500"
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ps "EdgeToEdgeStrategy"
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text (MLText
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xt "48000,87400,61400,88600"
st "delay = 1 ns    ( time ) "
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header ""
)
elements [
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type "time"
value "1 ns"
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)
portVis (PortSigDisplay
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sT 1
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archFileType "UNKNOWN"
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*77 (Net
uid 2521,0
decl (Decl
n "resetSynch"
t "std_ulogic"
o 37
suid 5,0
)
declText (MLText
uid 2522,0
va (VaSet
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commentText (CommentText
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oxt "0,0,18000,5000"
text (MLText
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va (VaSet
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xt "29200,81200,37400,82400"
st "
logic1 <= '1';
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tm "HdlTextMgr"
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shape (Rectangle
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va (VaSet
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fg "65535,65535,32768"
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xt "28000,80000,36000,84000"
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oxt "0,0,8000,10000"
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tm "HdlTextNameMgr"
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va (VaSet
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xt "28400,85000,29000,86000"
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shape (Triangle
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ro 90
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fg "0,65535,0"
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tg (CPTG
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va (VaSet
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xt "50000,81500,51800,82500"
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xt "50000,82500,50000,82500"
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o 1
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xt "55000,81625,55750,82375"
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ps "OnEdgeStrategy"
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ro 90
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fg "0,65535,0"
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tg (CPTG
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xt "54750,82500,54750,82500"
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decl (Decl
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shape (Buf
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va (VaSet
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fg "0,65535,0"
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xt "50000,79000,55000,85000"
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xt "180750,64500,180750,64500"
ju 2
blo "180750,64500"
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ro 270
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tg (CPTG
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xt "170100,63500,172500,64500"
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s (Text
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xt "170100,64500,170100,64500"
blo "170100,64500"
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)
thePort (LogicalPort
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va (VaSet
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xt "109000,67400,122400,68600"
st "delay = 1 ns    ( time ) "
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header ""
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elements [
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value "1 ns"
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portVis (PortSigDisplay
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*98 (PortIoOut
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shape (CompositeShape
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ro 270
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(Line
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ro 270
xt "120000,32000,120500,32000"
pts [
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tg (WTG
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ps "PortIoTextPlaceStrategy"
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st "LED1"
blo "123000,32500"
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blo "123000,32700"
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o 18
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declText (MLText
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va (VaSet
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xt "-12000,79000,-600,80000"
st "LED1          : std_uLogic"
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*100 (PortIoOut
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shape (CompositeShape
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va (VaSet
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fg "0,0,32768"
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optionalChildren [
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uid 2690,0
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ro 270
xt "120500,33625,122000,34375"
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(Line
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sl 0
ro 270
xt "120000,34000,120500,34000"
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tg (WTG
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ps "PortIoTextPlaceStrategy"
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va (VaSet
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blo "123000,34700"
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declText (MLText
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xt "-12000,79000,-800,80000"
st "LED2          : std_ulogic"
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decl (Decl
n "testOut"
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b "(1 TO testLineNb)"
o 46
suid 10,0
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declText (MLText
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xt "-12000,79000,13300,80000"
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oxt "0,0,18000,5000"
text (MLText
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va (VaSet
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xt "92200,29200,108500,35200"
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tm "HdlTextMgr"
wrapOption 3
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shape (Rectangle
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xt "92000,28000,112000,40000"
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tm "HdlTextNameMgr"
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st "2"
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tm "HdlTextNumberMgr"
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xt "32250,47625,33000,48375"
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tg (CPTG
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xt "33000,47500,34800,48500"
st "in1"
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s (Text
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xt "33000,48500,33000,48500"
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thePort (LogicalPort
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ps "OnEdgeStrategy"
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xt "38750,47625,39500,48375"
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tg (CPTG
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xt "35350,47500,37750,48500"
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xt "37750,48500,37750,48500"
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thePort (LogicalPort
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xt "33000,45000,38000,51000"
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tg (CPTG
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ro 90
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ps "OnEdgeStrategy"
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tg (CPTG
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xt "47000,35625,47750,36375"
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tg (CPTG
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decl (Decl
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xt "41000,34000,47000,42000"
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va (VaSet
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xt "48000,41400,61400,42600"
st "delay = 1 ns    ( time ) "
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header ""
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portVis (PortSigDisplay
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decl (Decl
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declText (MLText
uid 3309,0
va (VaSet
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xt "-12000,79000,2300,80000"
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uid 3310,0
decl (Decl
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xt "-12000,79000,-500,80000"
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xt "-12000,79000,3200,80000"
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uid 3324,0
decl (Decl
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xt "-12000,79000,0,80000"
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decl (Decl
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uid 3328,0
decl (Decl
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o 42
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uid 3329,0
va (VaSet
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xt "-12000,79000,3700,80000"
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xt "103000,51625,103750,52375"
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tg (CPTG
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va (VaSet
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uid 3343,0
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uid 3347,0
ro 270
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xt "102250,55625,103000,56375"
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ps "OnEdgeStrategy"
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ro 270
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xt "103000,55625,103750,56375"
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tg (CPTG
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va (VaSet
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xt "100200,55400,102000,56400"
st "CLK"
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blo "102000,56200"
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ps "OnEdgeStrategy"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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xt "98600,56600,100400,57600"
st "CLR"
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decl (Decl
n "CLR"
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o 2
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ps "OnEdgeStrategy"
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ro 270
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xt "96250,51625,97000,52375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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xt "98000,51300,98600,52300"
st "Q"
blo "98000,52100"
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decl (Decl
n "Q"
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xt "97000,50000,103000,58000"
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xt "95600,57700,102200,58700"
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blo "95600,58500"
tm "BdLibraryNameMgr"
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xt "95600,58700,97400,59700"
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xt "95600,59700,97400,60700"
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xt "104000,57400,117400,58600"
st "delay = 1 ns    ( time ) "
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header ""
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portVis (PortSigDisplay
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archFileType "UNKNOWN"
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*160 (SaComponent
uid 3356,0
optionalChildren [
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uid 3365,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3366,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "114000,51625,114750,52375"
)
tg (CPTG
uid 3367,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3368,0
va (VaSet
isHidden 1
)
xt "178950,51500,180750,52500"
st "in1"
ju 2
blo "180750,52300"
)
s (Text
uid 3369,0
va (VaSet
isHidden 1
)
xt "180750,52500,180750,52500"
ju 2
blo "180750,52500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*162 (CptPort
uid 3370,0
optionalChildren [
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uid 3375,0
va (VaSet
fg "0,65535,0"
)
xt "108250,51625,109000,52375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 3371,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "107500,51625,108250,52375"
)
tg (CPTG
uid 3372,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3373,0
va (VaSet
isHidden 1
)
xt "170100,51500,172500,52500"
st "out1"
blo "170100,52300"
)
s (Text
uid 3374,0
va (VaSet
isHidden 1
)
xt "170100,52500,170100,52500"
blo "170100,52500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 3357,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,49000,114000,55000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 3358,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 3359,0
va (VaSet
isHidden 1
)
xt "109910,47700,112910,48700"
st "gates"
blo "109910,48500"
tm "BdLibraryNameMgr"
)
*165 (Text
uid 3360,0
va (VaSet
isHidden 1
)
xt "109910,48700,114710,49700"
st "inverter"
blo "109910,49500"
tm "CptNameMgr"
)
*166 (Text
uid 3361,0
va (VaSet
)
xt "109910,48700,111710,49700"
st "I15"
blo "109910,49500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3362,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3363,0
text (MLText
uid 3364,0
va (VaSet
isHidden 1
)
xt "109000,55400,122400,56600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*167 (PortIoIn
uid 3376,0
shape (CompositeShape
uid 3377,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3378,0
sl 0
ro 90
xt "120500,51625,122000,52375"
)
(Line
uid 3379,0
sl 0
ro 90
xt "120000,52000,120500,52000"
pts [
"120500,52000"
"120000,52000"
]
)
]
)
tg (WTG
uid 3380,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3381,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,51300,130500,52700"
st "sensor1_n"
blo "123000,52500"
tm "WireNameMgr"
)
s (Text
uid 3382,0
va (VaSet
)
xt "123000,52700,123000,52700"
blo "123000,52700"
tm "SignalTypeMgr"
)
)
)
*168 (Net
uid 3410,0
decl (Decl
n "sensor2Synch"
t "std_uLogic"
o 44
suid 17,0
)
declText (MLText
uid 3411,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,3700,80000"
st "SIGNAL sensor2Synch  : std_uLogic"
)
)
*169 (Net
uid 3412,0
decl (Decl
n "sensor2"
t "std_uLogic"
o 43
suid 18,0
)
declText (MLText
uid 3413,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,2800,80000"
st "SIGNAL sensor2       : std_uLogic"
)
)
*170 (Net
uid 3414,0
decl (Decl
n "sensor2_n"
t "std_uLogic"
o 11
suid 19,0
)
declText (MLText
uid 3415,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,0,80000"
st "sensor2_n     : std_uLogic"
)
)
*171 (Net
uid 3527,0
decl (Decl
n "motorOn"
t "std_uLogic"
o 21
suid 20,0
)
declText (MLText
uid 3528,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,0,80000"
st "motorOn       : std_uLogic"
)
)
*172 (PortIoOut
uid 3535,0
shape (CompositeShape
uid 3536,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3537,0
sl 0
ro 270
xt "120500,43625,122000,44375"
)
(Line
uid 3538,0
sl 0
ro 270
xt "120000,44000,120500,44000"
pts [
"120000,44000"
"120500,44000"
]
)
]
)
tg (WTG
uid 3539,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3540,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,43300,129300,44700"
st "motorOn"
blo "123000,44500"
tm "WireNameMgr"
)
s (Text
uid 3541,0
va (VaSet
font "Verdana,12,0"
)
xt "123000,44700,123000,44700"
blo "123000,44700"
tm "SignalTypeMgr"
)
)
)
*173 (PortIoOut
uid 3736,0
shape (CompositeShape
uid 3737,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3738,0
sl 0
ro 270
xt "120500,35625,122000,36375"
)
(Line
uid 3739,0
sl 0
ro 270
xt "120000,36000,120500,36000"
pts [
"120000,36000"
"120500,36000"
]
)
]
)
tg (WTG
uid 3740,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3741,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,35300,134100,36700"
st "LEDs : (1 TO 8)"
blo "123000,36500"
tm "WireNameMgr"
)
s (Text
uid 3742,0
va (VaSet
font "Verdana,12,0"
)
xt "123000,36700,123000,36700"
blo "123000,36700"
tm "SignalTypeMgr"
)
)
)
*174 (Net
uid 3920,0
decl (Decl
n "side1"
t "std_uLogic"
o 22
suid 22,0
)
declText (MLText
uid 3921,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,-800,80000"
st "side1         : std_uLogic"
)
)
*175 (Net
uid 3922,0
decl (Decl
n "side2"
t "std_uLogic"
o 23
suid 23,0
)
declText (MLText
uid 3923,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,-800,80000"
st "side2         : std_uLogic"
)
)
*176 (Net
uid 4071,0
decl (Decl
n "setPoint"
t "std_uLogic"
o 45
suid 25,0
)
declText (MLText
uid 4072,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-38400,79600"
st "SIGNAL setPoint      : std_uLogic"
)
)
*177 (Net
uid 4075,0
decl (Decl
n "go2Synch"
t "std_uLogic"
o 34
suid 27,0
)
declText (MLText
uid 4076,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-37700,79600"
st "SIGNAL go2Synch      : std_uLogic"
)
)
*178 (Net
uid 4077,0
decl (Decl
n "go2"
t "std_uLogic"
o 33
suid 28,0
)
declText (MLText
uid 4078,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-38600,79600"
st "SIGNAL go2           : std_uLogic"
)
)
*179 (Net
uid 4079,0
decl (Decl
n "go2_n"
t "std_uLogic"
o 7
suid 29,0
)
declText (MLText
uid 4080,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-41400,79600"
st "go2_n         : std_uLogic"
)
)
*180 (Net
uid 4081,0
decl (Decl
n "go1Synch"
t "std_uLogic"
o 32
suid 30,0
)
declText (MLText
uid 4082,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-37700,79600"
st "SIGNAL go1Synch      : std_uLogic"
)
)
*181 (Net
uid 4083,0
decl (Decl
n "go1"
t "std_uLogic"
o 31
suid 31,0
)
declText (MLText
uid 4084,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-38600,79600"
st "SIGNAL go1           : std_uLogic"
)
)
*182 (Net
uid 4085,0
decl (Decl
n "go1_n"
t "std_uLogic"
o 6
suid 32,0
)
declText (MLText
uid 4086,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-41400,79600"
st "go1_n         : std_uLogic"
)
)
*183 (SaComponent
uid 4087,0
optionalChildren [
*184 (CptPort
uid 4096,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4097,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,87625,103750,88375"
)
tg (CPTG
uid 4098,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4099,0
va (VaSet
)
xt "101400,87300,102000,88300"
st "D"
ju 2
blo "102000,88100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*185 (CptPort
uid 4100,0
optionalChildren [
*186 (FFT
pts [
"102250,92000"
"103000,91625"
"103000,92375"
]
uid 4104,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "102250,91625,103000,92375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 4101,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,91625,103750,92375"
)
tg (CPTG
uid 4102,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4103,0
va (VaSet
)
xt "100200,91400,102000,92400"
st "CLK"
ju 2
blo "102000,92200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*187 (CptPort
uid 4105,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4106,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "99625,94000,100375,94750"
)
tg (CPTG
uid 4107,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4108,0
va (VaSet
)
xt "98600,92600,100400,93600"
st "CLR"
blo "98600,93400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*188 (CptPort
uid 4109,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4110,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "96250,87625,97000,88375"
)
tg (CPTG
uid 4111,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4112,0
va (VaSet
)
xt "98000,87300,98600,88300"
st "Q"
blo "98000,88100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 4088,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,86000,103000,94000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 4089,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*189 (Text
uid 4090,0
va (VaSet
)
xt "95600,93700,102200,94700"
st "sequential"
blo "95600,94500"
tm "BdLibraryNameMgr"
)
*190 (Text
uid 4091,0
va (VaSet
)
xt "95600,94700,97400,95700"
st "DFF"
blo "95600,95500"
tm "CptNameMgr"
)
*191 (Text
uid 4092,0
va (VaSet
)
xt "95600,95700,97400,96700"
st "I16"
blo "95600,96500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4093,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4094,0
text (MLText
uid 4095,0
va (VaSet
isHidden 1
)
xt "104000,93400,117400,94600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*192 (SaComponent
uid 4113,0
optionalChildren [
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uid 4122,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4123,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,75625,103750,76375"
)
tg (CPTG
uid 4124,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4125,0
va (VaSet
)
xt "101400,75300,102000,76300"
st "D"
ju 2
blo "102000,76100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*194 (CptPort
uid 4126,0
optionalChildren [
*195 (FFT
pts [
"102250,80000"
"103000,79625"
"103000,80375"
]
uid 4130,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "102250,79625,103000,80375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 4127,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,79625,103750,80375"
)
tg (CPTG
uid 4128,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4129,0
va (VaSet
)
xt "100200,79400,102000,80400"
st "CLK"
ju 2
blo "102000,80200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*196 (CptPort
uid 4131,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4132,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "99625,82000,100375,82750"
)
tg (CPTG
uid 4133,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4134,0
va (VaSet
)
xt "98600,80600,100400,81600"
st "CLR"
blo "98600,81400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*197 (CptPort
uid 4135,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4136,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "96250,75625,97000,76375"
)
tg (CPTG
uid 4137,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4138,0
va (VaSet
)
xt "98000,75300,98600,76300"
st "Q"
blo "98000,76100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 4114,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,74000,103000,82000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 4115,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*198 (Text
uid 4116,0
va (VaSet
)
xt "95600,81700,102200,82700"
st "sequential"
blo "95600,82500"
tm "BdLibraryNameMgr"
)
*199 (Text
uid 4117,0
va (VaSet
)
xt "95600,82700,97400,83700"
st "DFF"
blo "95600,83500"
tm "CptNameMgr"
)
*200 (Text
uid 4118,0
va (VaSet
)
xt "95600,83700,97400,84700"
st "I17"
blo "95600,84500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4119,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4120,0
text (MLText
uid 4121,0
va (VaSet
isHidden 1
)
xt "104000,81400,117400,82600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*201 (SaComponent
uid 4139,0
optionalChildren [
*202 (CptPort
uid 4148,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4149,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "114000,87625,114750,88375"
)
tg (CPTG
uid 4150,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4151,0
va (VaSet
isHidden 1
)
xt "178950,87500,180750,88500"
st "in1"
ju 2
blo "180750,88300"
)
s (Text
uid 4152,0
va (VaSet
isHidden 1
)
xt "180750,88500,180750,88500"
ju 2
blo "180750,88500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*203 (CptPort
uid 4153,0
optionalChildren [
*204 (Circle
uid 4158,0
va (VaSet
fg "0,65535,0"
)
xt "108250,87625,109000,88375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 4154,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "107500,87625,108250,88375"
)
tg (CPTG
uid 4155,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4156,0
va (VaSet
isHidden 1
)
xt "170100,87500,172500,88500"
st "out1"
blo "170100,88300"
)
s (Text
uid 4157,0
va (VaSet
isHidden 1
)
xt "170100,88500,170100,88500"
blo "170100,88500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 4140,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,85000,114000,91000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 4141,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*205 (Text
uid 4142,0
va (VaSet
isHidden 1
)
xt "109910,83700,112910,84700"
st "gates"
blo "109910,84500"
tm "BdLibraryNameMgr"
)
*206 (Text
uid 4143,0
va (VaSet
isHidden 1
)
xt "109910,84700,114710,85700"
st "inverter"
blo "109910,85500"
tm "CptNameMgr"
)
*207 (Text
uid 4144,0
va (VaSet
)
xt "109910,84700,111710,85700"
st "I18"
blo "109910,85500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4145,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4146,0
text (MLText
uid 4147,0
va (VaSet
isHidden 1
)
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xt "59500,72000,60000,72000"
pts [
"60000,72000"
"59500,72000"
]
)
]
)
tg (WTG
uid 4954,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4955,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "49000,71300,57000,72700"
st "LCD_RST_n"
ju 2
blo "57000,72500"
tm "WireNameMgr"
)
s (Text
uid 4956,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,72700,49000,72700"
ju 2
blo "49000,72700"
tm "SignalTypeMgr"
)
)
)
*250 (Net
uid 5038,0
decl (Decl
n "LCD_CS1_n"
t "std_ulogic"
o 14
suid 49,0
)
declText (MLText
uid 5039,0
va (VaSet
isHidden 1
)
xt "0,74600,15700,75800"
st "LCD_CS1_n     : std_ulogic"
)
)
*251 (Net
uid 5040,0
decl (Decl
n "LCD_SCL"
t "std_ulogic"
o 16
suid 50,0
)
declText (MLText
uid 5041,0
va (VaSet
isHidden 1
)
xt "0,74600,15000,75800"
st "LCD_SCL       : std_ulogic"
)
)
*252 (Net
uid 5042,0
decl (Decl
n "LCD_SI"
t "std_ulogic"
o 17
suid 51,0
)
declText (MLText
uid 5043,0
va (VaSet
isHidden 1
)
xt "0,74600,14400,75800"
st "LCD_SI        : std_ulogic"
)
)
*253 (Net
uid 5044,0
decl (Decl
n "LCD_A0"
t "std_ulogic"
o 13
suid 52,0
)
declText (MLText
uid 5045,0
va (VaSet
isHidden 1
)
xt "0,74600,14700,75800"
st "LCD_A0        : std_ulogic"
)
)
*254 (Net
uid 5046,0
decl (Decl
n "LCD_RST_n"
t "std_ulogic"
o 15
suid 53,0
)
declText (MLText
uid 5047,0
va (VaSet
isHidden 1
)
xt "0,74600,15600,75800"
st "LCD_RST_n     : std_ulogic"
)
)
*255 (Net
uid 5716,0
decl (Decl
n "LEDs"
t "std_uLogic_vector"
b "(1 TO 8)"
o 20
suid 55,0
)
declText (MLText
uid 5717,0
va (VaSet
isHidden 1
)
xt "0,0,22900,1200"
st "LEDs          : std_uLogic_vector(1 TO 8)"
)
)
*256 (SaComponent
uid 6730,0
optionalChildren [
*257 (CptPort
uid 6646,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6647,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,77625,68000,78375"
)
tg (CPTG
uid 6648,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6649,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,77300,72800,78700"
st "clock"
blo "69000,78500"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_uLogic"
o 2
suid 1,0
)
)
)
*258 (CptPort
uid 6650,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6651,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,79625,68000,80375"
)
tg (CPTG
uid 6652,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6653,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,79300,73100,80700"
st "reset"
blo "69000,80500"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_uLogic"
o 8
suid 2,0
)
)
)
*259 (CptPort
uid 6654,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6655,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,55625,84750,56375"
)
tg (CPTG
uid 6656,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6657,0
va (VaSet
font "Verdana,12,0"
)
xt "78800,55400,83000,56800"
st "side1"
ju 2
blo "83000,56600"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "side1"
t "std_uLogic"
o 19
suid 3,0
)
)
)
*260 (CptPort
uid 6658,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6659,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,53625,68000,54375"
)
tg (CPTG
uid 6660,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6661,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,53300,74100,54700"
st "restart"
blo "69000,54500"
)
)
thePort (LogicalPort
decl (Decl
n "restart"
t "std_uLogic"
o 9
suid 4,0
)
)
)
*261 (CptPort
uid 6662,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6663,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,57625,68000,58375"
)
tg (CPTG
uid 6664,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6665,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,57300,72200,58700"
st "go2"
blo "69000,58500"
)
)
thePort (LogicalPort
decl (Decl
n "go2"
t "std_uLogic"
o 7
suid 5,0
)
)
)
*262 (CptPort
uid 6666,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6667,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,61625,84750,62375"
)
tg (CPTG
uid 6668,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6669,0
va (VaSet
font "Verdana,12,0"
)
xt "77100,61400,83000,62800"
st "sensor1"
ju 2
blo "83000,62600"
)
)
thePort (LogicalPort
decl (Decl
n "sensor1"
t "std_uLogic"
o 10
suid 6,0
)
)
)
*263 (CptPort
uid 6670,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6671,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,75625,68000,76375"
)
tg (CPTG
uid 6672,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6673,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,75300,75700,76700"
st "testMode"
blo "69000,76500"
)
)
thePort (LogicalPort
decl (Decl
n "testMode"
t "std_uLogic"
o 12
suid 7,0
)
)
)
*264 (CptPort
uid 6674,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6675,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,55625,68000,56375"
)
tg (CPTG
uid 6676,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6677,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,55300,72200,56700"
st "go1"
blo "69000,56500"
)
)
thePort (LogicalPort
decl (Decl
n "go1"
t "std_uLogic"
o 6
suid 9,0
)
)
)
*265 (CptPort
uid 6678,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6679,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,57625,84750,58375"
)
tg (CPTG
uid 6680,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6681,0
va (VaSet
font "Verdana,12,0"
)
xt "78800,57400,83000,58800"
st "side2"
ju 2
blo "83000,58600"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "side2"
t "std_uLogic"
o 20
suid 10,0
)
)
)
*266 (CptPort
uid 6682,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6683,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,63625,84750,64375"
)
tg (CPTG
uid 6684,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6685,0
va (VaSet
font "Verdana,12,0"
)
xt "77100,63300,83000,64700"
st "sensor2"
ju 2
blo "83000,64500"
)
)
thePort (LogicalPort
decl (Decl
n "sensor2"
t "std_uLogic"
o 11
suid 11,0
)
)
)
*267 (CptPort
uid 6686,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6687,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,53625,84750,54375"
)
tg (CPTG
uid 6688,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6689,0
va (VaSet
font "Verdana,12,0"
)
xt "76700,53400,83000,54800"
st "motorOn"
ju 2
blo "83000,54600"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "motorOn"
t "std_uLogic"
o 18
suid 12,0
)
)
)
*268 (CptPort
uid 6690,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6691,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,67625,84750,68375"
)
tg (CPTG
uid 6692,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6693,0
va (VaSet
font "Verdana,12,0"
)
xt "76300,67400,83000,68800"
st "encoderA"
ju 2
blo "83000,68600"
)
)
thePort (LogicalPort
decl (Decl
n "encoderA"
t "std_uLogic"
o 3
suid 13,0
)
)
)
*269 (CptPort
uid 6694,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6695,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,69625,84750,70375"
)
tg (CPTG
uid 6696,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6697,0
va (VaSet
font "Verdana,12,0"
)
xt "76300,69400,83000,70800"
st "encoderB"
ju 2
blo "83000,70600"
)
)
thePort (LogicalPort
decl (Decl
n "encoderB"
t "std_uLogic"
o 4
suid 14,0
)
)
)
*270 (CptPort
uid 6698,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6699,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,71625,84750,72375"
)
tg (CPTG
uid 6700,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6701,0
va (VaSet
font "Verdana,12,0"
)
xt "76600,71400,83000,72800"
st "encoderI"
ju 2
blo "83000,72600"
)
)
thePort (LogicalPort
decl (Decl
n "encoderI"
t "std_uLogic"
o 5
suid 15,0
)
)
)
*271 (CptPort
uid 6702,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6703,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,59625,68000,60375"
)
tg (CPTG
uid 6704,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6705,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,59300,74800,60700"
st "button4"
blo "69000,60500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "button4"
t "std_ulogic"
o 1
suid 16,0
)
)
)
*272 (CptPort
uid 6706,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6707,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,63625,68000,64375"
)
tg (CPTG
uid 6708,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6709,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,63300,73900,64700"
st "CS1_n"
blo "69000,64500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CS1_n"
t "std_ulogic"
o 14
suid 2017,0
)
)
)
*273 (CptPort
uid 6710,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6711,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,65625,68000,66375"
)
tg (CPTG
uid 6712,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6713,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,65300,72200,66700"
st "SCL"
blo "69000,66500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SCL"
t "std_ulogic"
o 16
suid 2018,0
)
)
)
*274 (CptPort
uid 6714,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6715,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,67625,68000,68375"
)
tg (CPTG
uid 6716,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6717,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,67300,71100,68700"
st "SI"
blo "69000,68500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SI"
t "std_ulogic"
o 17
suid 2019,0
)
)
)
*275 (CptPort
uid 6718,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6719,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,69625,68000,70375"
)
tg (CPTG
uid 6720,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6721,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,69300,71400,70700"
st "A0"
blo "69000,70500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "A0"
t "std_ulogic"
o 13
suid 2020,0
)
)
)
*276 (CptPort
uid 6722,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6723,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,71625,68000,72375"
)
tg (CPTG
uid 6724,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6725,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,71300,73700,72700"
st "RST_n"
blo "69000,72500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RST_n"
t "std_ulogic"
o 15
suid 2021,0
)
)
)
*277 (CptPort
uid 6726,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6727,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "75625,49250,76375,50000"
)
tg (CPTG
uid 6728,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6729,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "75300,51000,76700,56600"
st "testOut"
ju 2
blo "76500,51000"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_uLogic_vector"
b "(1 to 16)"
o 21
suid 2022,0
)
)
)
]
shape (Rectangle
uid 6731,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "68000,50000,84000,82000"
)
oxt "40000,2000,56000,34000"
ttg (MlTextGroup
uid 6732,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*278 (Text
uid 6733,0
va (VaSet
font "Verdana,8,1"
)
xt "68100,81700,71800,82700"
st "Cursor"
blo "68100,82500"
tm "BdLibraryNameMgr"
)
*279 (Text
uid 6734,0
va (VaSet
font "Verdana,8,1"
)
xt "68100,82700,75400,83700"
st "cursorCircuit"
blo "68100,83500"
tm "CptNameMgr"
)
*280 (Text
uid 6735,0
va (VaSet
font "Verdana,8,1"
)
xt "68100,83700,69700,84700"
st "I0"
blo "68100,84500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 6736,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 6737,0
text (MLText
uid 6738,0
va (VaSet
font "Courier New,8,0"
)
xt "68000,85200,95500,90000"
st "position0       = position0          ( positive )  
position1       = position1          ( positive )  
position2       = position2          ( positive )  
slopeShiftBitNb = slopeShiftBitNb    ( positive )  
pwmBitNb        = pwmBitNb           ( positive )  
testLineNb      = testLineNb         ( positive )  "
)
header ""
)
elements [
(GiElement
name "position0"
type "positive"
value "position0"
)
(GiElement
name "position1"
type "positive"
value "position1"
)
(GiElement
name "position2"
type "positive"
value "position2"
)
(GiElement
name "slopeShiftBitNb"
type "positive"
value "slopeShiftBitNb"
)
(GiElement
name "pwmBitNb"
type "positive"
value "pwmBitNb"
)
(GiElement
name "testLineNb"
type "positive"
value "testLineNb"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*281 (Wire
uid 1317,0
shape (OrthoPolyLine
uid 1318,0
va (VaSet
vasetType 3
)
xt "28000,92000,33000,92000"
pts [
"33000,92000"
"28000,92000"
]
)
start &18
end &14
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1321,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1322,0
va (VaSet
font "Verdana,12,0"
)
xt "27000,90600,32700,92000"
st "reset_n"
blo "27000,91800"
tm "WireNameMgr"
)
)
on &15
)
*282 (Wire
uid 1327,0
shape (OrthoPolyLine
uid 1328,0
va (VaSet
vasetType 3
)
xt "28000,78000,67250,78000"
pts [
"67250,78000"
"28000,78000"
]
)
start &257
end &13
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1331,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1332,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,76600,31800,78000"
st "clock"
blo "28000,77800"
tm "WireNameMgr"
)
)
on &1
)
*283 (Wire
uid 1625,0
shape (OrthoPolyLine
uid 1626,0
va (VaSet
vasetType 3
)
xt "55750,80000,67250,82000"
pts [
"67250,80000"
"59000,80000"
"59000,82000"
"55750,82000"
]
)
start &258
end &85
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1629,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1630,0
va (VaSet
font "Verdana,12,0"
)
xt "60000,78600,68600,80000"
st "resetSynch"
blo "60000,79800"
tm "WireNameMgr"
)
)
on &77
)
*284 (Wire
uid 2137,0
shape (OrthoPolyLine
uid 2138,0
va (VaSet
vasetType 3
)
xt "28000,76000,67250,76000"
pts [
"67250,76000"
"28000,76000"
]
)
start &263
end &28
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2141,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2142,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,74600,34700,76000"
st "testMode"
blo "28000,75800"
tm "WireNameMgr"
)
)
on &24
)
*285 (Wire
uid 2145,0
shape (OrthoPolyLine
uid 2146,0
va (VaSet
vasetType 3
)
xt "28000,24000,33000,24000"
pts [
"33000,24000"
"28000,24000"
]
)
start &115
end &27
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2149,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2150,0
va (VaSet
font "Verdana,12,0"
)
xt "27000,22600,33700,24000"
st "restart_n"
blo "27000,23800"
tm "WireNameMgr"
)
)
on &146
)
*286 (Wire
uid 2153,0
shape (OrthoPolyLine
uid 2154,0
va (VaSet
vasetType 3
)
xt "28000,60000,33000,60000"
pts [
"33000,60000"
"28000,60000"
]
)
start &122
end &26
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2157,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2158,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,58600,35400,60000"
st "button4_n"
blo "28000,59800"
tm "WireNameMgr"
)
)
on &243
)
*287 (Wire
uid 2161,0
shape (OrthoPolyLine
uid 2162,0
va (VaSet
vasetType 3
)
xt "28000,48000,33000,48000"
pts [
"33000,48000"
"28000,48000"
]
)
start &108
end &25
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2165,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2166,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,46600,31500,47900"
st "go2_n"
blo "28000,47600"
tm "WireNameMgr"
)
)
on &179
)
*288 (Wire
uid 2238,0
shape (OrthoPolyLine
uid 2239,0
va (VaSet
vasetType 3
)
xt "36000,52000,41000,52000"
pts [
"41000,52000"
"36000,52000"
]
)
start &31
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2244,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2245,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,50600,39800,52000"
st "clock"
blo "36000,51800"
tm "WireNameMgr"
)
)
on &1
)
*289 (Wire
uid 2246,0
shape (OrthoPolyLine
uid 2247,0
va (VaSet
vasetType 3
)
xt "36000,54000,44000,56000"
pts [
"44000,54000"
"44000,56000"
"36000,56000"
]
)
start &33
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2252,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2253,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,54600,44600,56000"
st "resetSynch"
blo "36000,55800"
tm "WireNameMgr"
)
)
on &77
)
*290 (Wire
uid 2256,0
shape (OrthoPolyLine
uid 2257,0
va (VaSet
vasetType 3
)
xt "47000,48000,67250,58000"
pts [
"47000,48000"
"58000,48000"
"58000,58000"
"67250,58000"
]
)
start &34
end &261
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2258,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2259,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,46600,55900,48000"
st "go2Synch"
blo "49000,47800"
tm "WireNameMgr"
)
)
on &177
)
*291 (Wire
uid 2288,0
shape (OrthoPolyLine
uid 2289,0
va (VaSet
vasetType 3
)
xt "36000,66000,44000,68000"
pts [
"44000,66000"
"44000,68000"
"36000,68000"
]
)
start &42
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2292,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2293,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,66600,44600,68000"
st "resetSynch"
blo "36000,67800"
tm "WireNameMgr"
)
)
on &77
)
*292 (Wire
uid 2294,0
shape (OrthoPolyLine
uid 2295,0
va (VaSet
vasetType 3
)
xt "36000,64000,41000,64000"
pts [
"41000,64000"
"36000,64000"
]
)
start &40
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2298,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2299,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,62600,39800,64000"
st "clock"
blo "36000,63800"
tm "WireNameMgr"
)
)
on &1
)
*293 (Wire
uid 2302,0
shape (OrthoPolyLine
uid 2303,0
va (VaSet
vasetType 3
)
xt "47000,60000,67250,60000"
pts [
"47000,60000"
"67250,60000"
]
)
start &43
end &271
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2304,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2305,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,58600,59300,60000"
st "button4Synch"
blo "49000,59800"
tm "WireNameMgr"
)
)
on &244
)
*294 (Wire
uid 2332,0
shape (OrthoPolyLine
uid 2333,0
va (VaSet
vasetType 3
)
xt "36000,30000,44000,32000"
pts [
"44000,30000"
"44000,32000"
"36000,32000"
]
)
start &51
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2336,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2337,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,30600,44600,32000"
st "resetSynch"
blo "36000,31800"
tm "WireNameMgr"
)
)
on &77
)
*295 (Wire
uid 2338,0
shape (OrthoPolyLine
uid 2339,0
va (VaSet
vasetType 3
)
xt "36000,28000,41000,28000"
pts [
"41000,28000"
"36000,28000"
]
)
start &49
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2342,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2343,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,26600,39800,28000"
st "clock"
blo "36000,27800"
tm "WireNameMgr"
)
)
on &1
)
*296 (Wire
uid 2346,0
shape (OrthoPolyLine
uid 2347,0
va (VaSet
vasetType 3
)
xt "47000,24000,67250,54000"
pts [
"47000,24000"
"62000,24000"
"62000,54000"
"67250,54000"
]
)
start &52
end &260
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2348,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2349,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,22600,58600,24000"
st "restartSynch"
blo "49000,23800"
tm "WireNameMgr"
)
)
on &147
)
*297 (Wire
uid 2387,0
shape (OrthoPolyLine
uid 2388,0
va (VaSet
vasetType 3
)
xt "103000,64000,108250,64000"
pts [
"103000,64000"
"108250,64000"
]
)
start &58
end &93
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2389,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2390,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,62600,108900,64000"
st "sensor2"
blo "103000,63800"
tm "WireNameMgr"
)
)
on &169
)
*298 (Wire
uid 2391,0
shape (OrthoPolyLine
uid 2392,0
va (VaSet
vasetType 3
)
xt "103000,68000,108000,68000"
pts [
"103000,68000"
"108000,68000"
]
)
start &59
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2395,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2396,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,66600,108800,68000"
st "clock"
blo "105000,67800"
tm "WireNameMgr"
)
)
on &1
)
*299 (Wire
uid 2397,0
shape (OrthoPolyLine
uid 2398,0
va (VaSet
vasetType 3
)
xt "100000,70000,108000,72000"
pts [
"100000,70000"
"100000,72000"
"108000,72000"
]
)
start &61
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2401,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2402,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,70600,109600,72000"
st "resetSynch"
blo "101000,71800"
tm "WireNameMgr"
)
)
on &77
)
*300 (Wire
uid 2407,0
shape (OrthoPolyLine
uid 2408,0
va (VaSet
vasetType 3
)
xt "84750,64000,97000,64000"
pts [
"84750,64000"
"97000,64000"
]
)
start &266
end &62
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2409,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2410,0
va (VaSet
font "Verdana,12,0"
)
xt "85000,62600,95400,64000"
st "sensor2Synch"
blo "85000,63800"
tm "WireNameMgr"
)
)
on &168
)
*301 (Wire
uid 2431,0
shape (OrthoPolyLine
uid 2432,0
va (VaSet
vasetType 3
)
xt "84750,48000,120000,58000"
pts [
"84750,58000"
"92000,58000"
"92000,48000"
"120000,48000"
]
)
start &265
end &67
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2435,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2436,0
va (VaSet
font "Verdana,12,0"
)
xt "114000,46600,118200,48000"
st "side2"
blo "114000,47800"
tm "WireNameMgr"
)
)
on &175
)
*302 (Wire
uid 2439,0
shape (OrthoPolyLine
uid 2440,0
va (VaSet
vasetType 3
)
xt "84750,46000,120000,56000"
pts [
"84750,56000"
"90000,56000"
"90000,46000"
"120000,46000"
]
)
start &259
end &66
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2443,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2444,0
va (VaSet
font "Verdana,12,0"
)
xt "116000,44600,120200,46000"
st "side1"
blo "116000,45800"
tm "WireNameMgr"
)
)
on &174
)
*303 (Wire
uid 2499,0
shape (OrthoPolyLine
uid 2500,0
va (VaSet
vasetType 3
)
xt "36000,86000,41000,86000"
pts [
"41000,86000"
"36000,86000"
]
)
start &70
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2503,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2504,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,84600,39800,86000"
st "clock"
blo "36000,85800"
tm "WireNameMgr"
)
)
on &1
)
*304 (Wire
uid 2507,0
shape (OrthoPolyLine
uid 2508,0
va (VaSet
vasetType 3
)
xt "36000,82000,41000,82000"
pts [
"41000,82000"
"36000,82000"
]
)
start &69
end &78
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2511,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2512,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,80600,40400,82000"
st "logic1"
blo "36000,81800"
tm "WireNameMgr"
)
)
on &82
)
*305 (Wire
uid 2517,0
shape (OrthoPolyLine
uid 2518,0
va (VaSet
vasetType 3
)
xt "38750,88000,44000,92000"
pts [
"38750,92000"
"44000,92000"
"44000,88000"
]
)
start &19
end &72
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2519,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2520,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,90600,44100,92000"
st "reset"
blo "40000,91800"
tm "WireNameMgr"
)
)
on &16
)
*306 (Wire
uid 2598,0
shape (OrthoPolyLine
uid 2599,0
va (VaSet
vasetType 3
)
xt "47000,82000,50000,82000"
pts [
"47000,82000"
"50000,82000"
]
)
start &73
end &84
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 2600,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2601,0
va (VaSet
font "Verdana,12,0"
)
xt "44000,80600,54200,82000"
st "resetSynch_n"
blo "44000,81800"
tm "WireNameMgr"
)
)
on &90
)
*307 (Wire
uid 2646,0
shape (OrthoPolyLine
uid 2647,0
va (VaSet
vasetType 3
)
xt "114000,64000,120000,64000"
pts [
"120000,64000"
"114000,64000"
]
)
start &56
end &92
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 2648,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2649,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,62600,122500,64000"
st "sensor2_n"
blo "115000,63800"
tm "WireNameMgr"
)
s (Text
uid 2672,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,64000,115000,64000"
blo "115000,64000"
tm "SignalTypeMgr"
)
)
on &170
)
*308 (Wire
uid 2680,0
shape (OrthoPolyLine
uid 2681,0
va (VaSet
vasetType 3
)
xt "112000,32000,120000,32000"
pts [
"112000,32000"
"120000,32000"
]
)
start &103
end &98
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2684,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2685,0
va (VaSet
font "Verdana,12,0"
)
xt "117000,30600,121000,32000"
st "LED1"
blo "117000,31800"
tm "WireNameMgr"
)
)
on &99
)
*309 (Wire
uid 2695,0
shape (OrthoPolyLine
uid 2696,0
va (VaSet
vasetType 3
)
xt "112000,34000,120000,34000"
pts [
"112000,34000"
"120000,34000"
]
)
start &103
end &100
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2699,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2700,0
va (VaSet
font "Verdana,12,0"
)
xt "117000,32600,121000,34000"
st "LED2"
blo "117000,33800"
tm "WireNameMgr"
)
)
on &101
)
*310 (Wire
uid 2786,0
shape (OrthoPolyLine
uid 2787,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "76000,34000,92000,49250"
pts [
"76000,49250"
"76000,46000"
"84000,46000"
"84000,34000"
"92000,34000"
]
)
start &277
end &103
sat 32
eat 1
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2790,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2791,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "74600,42450,76000,48050"
st "testOut"
blo "75800,48050"
tm "WireNameMgr"
)
)
on &102
)
*311 (Wire
uid 3020,0
shape (OrthoPolyLine
uid 3021,0
va (VaSet
vasetType 3
)
xt "38750,48000,41000,48000"
pts [
"38750,48000"
"41000,48000"
]
)
start &109
end &30
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3022,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3023,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,46600,43950,48000"
st "go2"
blo "40750,47800"
tm "WireNameMgr"
)
s (Text
uid 3108,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,48000,40750,48000"
blo "40750,48000"
tm "SignalTypeMgr"
)
)
on &178
)
*312 (Wire
uid 3066,0
shape (OrthoPolyLine
uid 3067,0
va (VaSet
vasetType 3
)
xt "38750,60000,41000,60000"
pts [
"38750,60000"
"41000,60000"
]
)
start &123
end &39
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3068,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3069,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,58600,46750,60000"
st "setPoint"
blo "40750,59800"
tm "WireNameMgr"
)
s (Text
uid 3109,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,60000,40750,60000"
blo "40750,60000"
tm "SignalTypeMgr"
)
)
on &176
)
*313 (Wire
uid 3072,0
shape (OrthoPolyLine
uid 3073,0
va (VaSet
vasetType 3
)
xt "38750,24000,41000,24000"
pts [
"38750,24000"
"41000,24000"
]
)
start &116
end &48
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3074,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3075,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,22600,45850,24000"
st "restart"
blo "40750,23800"
tm "WireNameMgr"
)
s (Text
uid 3110,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,24000,40750,24000"
blo "40750,24000"
tm "SignalTypeMgr"
)
)
on &145
)
*314 (Wire
uid 3269,0
shape (OrthoPolyLine
uid 3270,0
va (VaSet
vasetType 3
)
xt "47000,36000,67250,56000"
pts [
"47000,36000"
"60000,36000"
"60000,56000"
"67250,56000"
]
)
start &141
end &264
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3273,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3274,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,34600,55900,36000"
st "go1Synch"
blo "49000,35800"
tm "WireNameMgr"
)
)
on &180
)
*315 (Wire
uid 3275,0
shape (OrthoPolyLine
uid 3276,0
va (VaSet
vasetType 3
)
xt "36000,42000,44000,44000"
pts [
"44000,42000"
"44000,44000"
"36000,44000"
]
)
start &140
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3279,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3280,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,42600,44600,44000"
st "resetSynch"
blo "36000,43800"
tm "WireNameMgr"
)
)
on &77
)
*316 (Wire
uid 3281,0
shape (OrthoPolyLine
uid 3282,0
va (VaSet
vasetType 3
)
xt "28000,36000,33000,36000"
pts [
"33000,36000"
"28000,36000"
]
)
start &130
end &128
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3283,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3284,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,34600,32800,36000"
st "go1_n"
blo "28000,35800"
tm "WireNameMgr"
)
)
on &182
)
*317 (Wire
uid 3285,0
shape (OrthoPolyLine
uid 3286,0
va (VaSet
vasetType 3
)
xt "36000,40000,41000,40000"
pts [
"41000,40000"
"36000,40000"
]
)
start &138
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3289,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3290,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,38600,39800,40000"
st "clock"
blo "36000,39800"
tm "WireNameMgr"
)
)
on &1
)
*318 (Wire
uid 3291,0
shape (OrthoPolyLine
uid 3292,0
va (VaSet
vasetType 3
)
xt "38750,36000,41000,36000"
pts [
"38750,36000"
"41000,36000"
]
)
start &131
end &137
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3293,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3294,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,34600,43950,36000"
st "go1"
blo "40750,35800"
tm "WireNameMgr"
)
s (Text
uid 3295,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,36000,40750,36000"
blo "40750,36000"
tm "SignalTypeMgr"
)
)
on &181
)
*319 (Wire
uid 3383,0
shape (OrthoPolyLine
uid 3384,0
va (VaSet
vasetType 3
)
xt "103000,56000,108000,56000"
pts [
"103000,56000"
"108000,56000"
]
)
start &153
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3387,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3388,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,54600,108800,56000"
st "clock"
blo "105000,55800"
tm "WireNameMgr"
)
)
on &1
)
*320 (Wire
uid 3389,0
shape (OrthoPolyLine
uid 3390,0
va (VaSet
vasetType 3
)
xt "84750,52000,97000,62000"
pts [
"84750,62000"
"94000,62000"
"94000,52000"
"97000,52000"
]
)
start &262
end &156
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3393,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3394,0
va (VaSet
font "Verdana,12,0"
)
xt "85000,60600,95400,62000"
st "sensor1Synch"
blo "85000,61800"
tm "WireNameMgr"
)
)
on &150
)
*321 (Wire
uid 3395,0
shape (OrthoPolyLine
uid 3396,0
va (VaSet
vasetType 3
)
xt "100000,58000,108000,60000"
pts [
"100000,58000"
"100000,60000"
"108000,60000"
]
)
start &155
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3399,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3400,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,58600,109600,60000"
st "resetSynch"
blo "101000,59800"
tm "WireNameMgr"
)
)
on &77
)
*322 (Wire
uid 3401,0
shape (OrthoPolyLine
uid 3402,0
va (VaSet
vasetType 3
)
xt "103000,52000,108250,52000"
pts [
"103000,52000"
"108250,52000"
]
)
start &152
end &162
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3403,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3404,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,50600,108900,52000"
st "sensor1"
blo "103000,51800"
tm "WireNameMgr"
)
)
on &149
)
*323 (Wire
uid 3405,0
shape (OrthoPolyLine
uid 3406,0
va (VaSet
vasetType 3
)
xt "114000,52000,120000,52000"
pts [
"120000,52000"
"114000,52000"
]
)
start &167
end &161
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3407,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3408,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,50600,122500,52000"
st "sensor1_n"
blo "115000,51800"
tm "WireNameMgr"
)
s (Text
uid 3409,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,52000,115000,52000"
blo "115000,52000"
tm "SignalTypeMgr"
)
)
on &148
)
*324 (Wire
uid 3529,0
shape (OrthoPolyLine
uid 3530,0
va (VaSet
vasetType 3
)
xt "84750,44000,120000,54000"
pts [
"84750,54000"
"88000,54000"
"88000,44000"
"120000,44000"
]
)
start &267
end &172
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3533,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3534,0
va (VaSet
font "Verdana,12,0"
)
xt "114000,42600,120300,44000"
st "motorOn"
blo "114000,43800"
tm "WireNameMgr"
)
)
on &171
)
*325 (Wire
uid 3743,0
shape (OrthoPolyLine
uid 3744,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "112000,36000,120000,36000"
pts [
"112000,36000"
"120000,36000"
]
)
start &103
end &173
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3747,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3748,0
va (VaSet
font "Verdana,12,0"
)
xt "117000,34600,120900,36000"
st "LEDs"
blo "117000,35800"
tm "WireNameMgr"
)
)
on &255
)
*326 (Wire
uid 4193,0
shape (OrthoPolyLine
uid 4194,0
va (VaSet
vasetType 3
)
xt "103000,92000,108000,92000"
pts [
"103000,92000"
"108000,92000"
]
)
start &185
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4197,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4198,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,90600,108800,92000"
st "clock"
blo "105000,91800"
tm "WireNameMgr"
)
)
on &1
)
*327 (Wire
uid 4199,0
shape (OrthoPolyLine
uid 4200,0
va (VaSet
vasetType 3
)
xt "103000,88000,108250,88000"
pts [
"103000,88000"
"108250,88000"
]
)
start &184
end &203
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4201,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4202,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,86600,109700,88000"
st "encoderB"
blo "103000,87800"
tm "WireNameMgr"
)
)
on &236
)
*328 (Wire
uid 4203,0
shape (OrthoPolyLine
uid 4204,0
va (VaSet
vasetType 3
)
xt "100000,94000,108000,96000"
pts [
"100000,94000"
"100000,96000"
"108000,96000"
]
)
start &187
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4207,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4208,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,94600,109600,96000"
st "resetSynch"
blo "101000,95800"
tm "WireNameMgr"
)
)
on &77
)
*329 (Wire
uid 4209,0
shape (OrthoPolyLine
uid 4210,0
va (VaSet
vasetType 3
)
xt "114000,88000,120000,88000"
pts [
"120000,88000"
"114000,88000"
]
)
start &215
end &202
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4211,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4212,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,86600,124100,88000"
st "encoderB_n"
blo "115000,87800"
tm "WireNameMgr"
)
s (Text
uid 4213,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,88000,115000,88000"
blo "115000,88000"
tm "SignalTypeMgr"
)
)
on &242
)
*330 (Wire
uid 4214,0
shape (OrthoPolyLine
uid 4215,0
va (VaSet
vasetType 3
)
xt "100000,82000,108000,84000"
pts [
"100000,82000"
"100000,84000"
"108000,84000"
]
)
start &196
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4218,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4219,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,82600,109600,84000"
st "resetSynch"
blo "101000,83800"
tm "WireNameMgr"
)
)
on &77
)
*331 (Wire
uid 4220,0
shape (OrthoPolyLine
uid 4221,0
va (VaSet
vasetType 3
)
xt "103000,80000,108000,80000"
pts [
"103000,80000"
"108000,80000"
]
)
start &194
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4224,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4225,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,78600,108800,80000"
st "clock"
blo "105000,79800"
tm "WireNameMgr"
)
)
on &1
)
*332 (Wire
uid 4226,0
shape (OrthoPolyLine
uid 4227,0
va (VaSet
vasetType 3
)
xt "114000,76000,120000,76000"
pts [
"120000,76000"
"114000,76000"
]
)
start &216
end &209
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4228,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4229,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,74600,124100,76000"
st "encoderA_n"
blo "115000,75800"
tm "WireNameMgr"
)
s (Text
uid 4230,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,76000,115000,76000"
blo "115000,76000"
tm "SignalTypeMgr"
)
)
on &241
)
*333 (Wire
uid 4231,0
shape (OrthoPolyLine
uid 4232,0
va (VaSet
vasetType 3
)
xt "103000,76000,108250,76000"
pts [
"103000,76000"
"108250,76000"
]
)
start &193
end &210
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4233,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4234,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,74600,109700,76000"
st "encoderA"
blo "103000,75800"
tm "WireNameMgr"
)
)
on &240
)
*334 (Wire
uid 4288,0
shape (OrthoPolyLine
uid 4289,0
va (VaSet
vasetType 3
)
xt "103000,104000,108000,104000"
pts [
"103000,104000"
"108000,104000"
]
)
start &219
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4292,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4293,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,102600,108800,104000"
st "clock"
blo "105000,103800"
tm "WireNameMgr"
)
)
on &1
)
*335 (Wire
uid 4294,0
shape (OrthoPolyLine
uid 4295,0
va (VaSet
vasetType 3
)
xt "114000,100000,120000,100000"
pts [
"120000,100000"
"114000,100000"
]
)
start &233
end &227
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4296,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4297,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,98600,123800,100000"
st "encoderI_n"
blo "115000,99800"
tm "WireNameMgr"
)
s (Text
uid 4298,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,100000,115000,100000"
blo "115000,100000"
tm "SignalTypeMgr"
)
)
on &239
)
*336 (Wire
uid 4299,0
shape (OrthoPolyLine
uid 4300,0
va (VaSet
vasetType 3
)
xt "100000,106000,108000,108000"
pts [
"100000,106000"
"100000,108000"
"108000,108000"
]
)
start &221
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4303,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4304,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,106600,109600,108000"
st "resetSynch"
blo "101000,107800"
tm "WireNameMgr"
)
)
on &77
)
*337 (Wire
uid 4305,0
shape (OrthoPolyLine
uid 4306,0
va (VaSet
vasetType 3
)
xt "103000,100000,108250,100000"
pts [
"103000,100000"
"108250,100000"
]
)
start &218
end &228
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4307,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4308,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,98600,109400,100000"
st "encoderI"
blo "103000,99800"
tm "WireNameMgr"
)
)
on &238
)
*338 (Wire
uid 4319,0
shape (OrthoPolyLine
uid 4320,0
va (VaSet
vasetType 3
)
xt "84750,68000,97000,76000"
pts [
"84750,68000"
"94000,68000"
"94000,76000"
"97000,76000"
]
)
start &268
end &197
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4321,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4322,0
va (VaSet
font "Verdana,12,0"
)
xt "86750,66600,97950,68000"
st "encoderASynch"
blo "86750,67800"
tm "WireNameMgr"
)
)
on &234
)
*339 (Wire
uid 4325,0
shape (OrthoPolyLine
uid 4326,0
va (VaSet
vasetType 3
)
xt "84750,70000,97000,88000"
pts [
"84750,70000"
"92000,70000"
"92000,88000"
"97000,88000"
]
)
start &269
end &188
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4327,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4328,0
va (VaSet
font "Verdana,12,0"
)
xt "86750,68600,97950,70000"
st "encoderBSynch"
blo "86750,69800"
tm "WireNameMgr"
)
)
on &235
)
*340 (Wire
uid 4331,0
shape (OrthoPolyLine
uid 4332,0
va (VaSet
vasetType 3
)
xt "84750,72000,97000,100000"
pts [
"84750,72000"
"90000,72000"
"90000,100000"
"97000,100000"
]
)
start &270
end &222
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4333,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4334,0
va (VaSet
font "Verdana,12,0"
)
xt "86750,70600,97650,72000"
st "encoderISynch"
blo "86750,71800"
tm "WireNameMgr"
)
)
on &237
)
*341 (Wire
uid 4884,0
shape (OrthoPolyLine
uid 4885,0
va (VaSet
vasetType 3
)
xt "60000,64000,67250,64000"
pts [
"67250,64000"
"60000,64000"
]
)
start &272
end &245
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4888,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4889,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,62600,69200,64000"
st "LCD_CS1_n"
blo "61000,63800"
tm "WireNameMgr"
)
)
on &250
)
*342 (Wire
uid 4892,0
shape (OrthoPolyLine
uid 4893,0
va (VaSet
vasetType 3
)
xt "60000,66000,67250,66000"
pts [
"67250,66000"
"60000,66000"
]
)
start &273
end &246
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4896,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4897,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,64600,67500,66000"
st "LCD_SCL"
blo "61000,65800"
tm "WireNameMgr"
)
)
on &251
)
*343 (Wire
uid 4900,0
shape (OrthoPolyLine
uid 4901,0
va (VaSet
vasetType 3
)
xt "60000,68000,67250,68000"
pts [
"67250,68000"
"60000,68000"
]
)
start &274
end &247
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4904,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4905,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,66600,66400,68000"
st "LCD_SI"
blo "61000,67800"
tm "WireNameMgr"
)
)
on &252
)
*344 (Wire
uid 4908,0
shape (OrthoPolyLine
uid 4909,0
va (VaSet
vasetType 3
)
xt "60000,70000,67250,70000"
pts [
"67250,70000"
"60000,70000"
]
)
start &275
end &248
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4912,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4913,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,68600,66700,70000"
st "LCD_A0"
blo "61000,69800"
tm "WireNameMgr"
)
)
on &253
)
*345 (Wire
uid 4916,0
shape (OrthoPolyLine
uid 4917,0
va (VaSet
vasetType 3
)
xt "60000,72000,67250,72000"
pts [
"67250,72000"
"60000,72000"
]
)
start &276
end &249
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4920,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4921,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,70600,69000,72000"
st "LCD_RST_n"
blo "61000,71800"
tm "WireNameMgr"
)
)
on &254
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "32768,32768,32768"
)
packageList *346 (PackageList
uid 187,0
stg "VerticalLayoutStrategy"
textVec [
*347 (Text
uid 1297,0
va (VaSet
font "Verdana,8,1"
)
xt "-7000,19000,-500,19900"
st "Package List"
blo "-7000,19700"
)
*348 (MLText
uid 1298,0
va (VaSet
)
xt "-7000,20000,10700,28400"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;
LIBRARY gates;
  USE gates.gates.all;
LIBRARY Common;
  USE Common.CommonLib.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 190,0
stg "VerticalLayoutStrategy"
textVec [
*349 (Text
uid 191,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,0,32000,1000"
st "Compiler Directives"
blo "20000,800"
)
*350 (Text
uid 192,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,1400,33800,2400"
st "Pre-module directives:"
blo "20000,2200"
)
*351 (MLText
uid 193,0
va (VaSet
isHidden 1
)
xt "20000,2800,32100,5200"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*352 (Text
uid 194,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,5600,34400,6600"
st "Post-module directives:"
blo "20000,6400"
)
*353 (MLText
uid 195,0
va (VaSet
isHidden 1
)
xt "20000,7000,20000,7000"
tm "BdCompilerDirectivesTextMgr"
)
*354 (Text
uid 196,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,7200,33800,8200"
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constant position1 : positive := integer(8.0 * real(stepsPerTurn) / cmPerTurn);
constant position2 : positive := integer(12.0 * real(stepsPerTurn) / cmPerTurn);
constant pwmBitNb : positive := 8;
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