DocumentHdrVersion "1.1" Header (DocumentHdr version 2 dialect 11 dmPackageRefs [ (DmPackageRef library "ieee" unitName "std_logic_1164" ) (DmPackageRef library "ieee" unitName "numeric_std" ) (DmPackageRef library "gates" unitName "gates" ) ] libraryRefs [ "ieee" "gates" ] ) version "26.1" appVersion "2018.1 (Build 12)" model (Symbol commonDM (CommonDM ldm (LogicalDM ordering 1 suid 8,0 usingSuid 1 emptyRow *1 (LEmptyRow ) uid 53,0 optionalChildren [ *2 (RefLabelRowHdr ) *3 (TitleRowHdr ) *4 (FilterRowHdr ) *5 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *6 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *7 (GroupColHdr tm "GroupColHdrMgr" ) *8 (NameColHdr tm "NameColHdrMgr" ) *9 (ModeColHdr tm "ModeColHdrMgr" ) *10 (TypeColHdr tm "TypeColHdrMgr" ) *11 (BoundsColHdr tm "BoundsColHdrMgr" ) *12 (InitColHdr tm "InitColHdrMgr" ) *13 (EolColHdr tm "EolColHdrMgr" ) *14 (LogPort port (LogicalPort decl (Decl n "clock" t "std_ulogic" o 8 suid 1,0 ) ) uid 148,0 ) *15 (LogPort port (LogicalPort m 1 decl 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*64 (MRCItem litem &47 pos 0 dimension 20 uid 101,0 ) *65 (MRCItem litem &49 pos 1 dimension 50 uid 102,0 ) *66 (MRCItem litem &50 pos 2 dimension 100 uid 103,0 ) *67 (MRCItem litem &51 pos 3 dimension 100 uid 104,0 ) *68 (MRCItem litem &52 pos 4 dimension 50 uid 105,0 ) *69 (MRCItem litem &53 pos 5 dimension 50 uid 106,0 ) *70 (MRCItem litem &54 pos 6 dimension 80 uid 107,0 ) ] ) fixedCol 3 fixedRow 2 name "Ports" uid 95,0 vaOverrides [ ] ) ] ) uid 81,0 type 1 ) VExpander (VariableExpander vvMap [ (vvPair variable "HDLDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hdl" ) (vvPair variable "HDSDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" ) (vvPair variable "SideDataDesignDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@bus@width@adaption/symbol.sb.info" ) (vvPair variable "SideDataUserDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@bus@width@adaption/symbol.sb.user" ) (vvPair variable "SourceDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "symbol" ) (vvPair variable "concat_file" value "concatenated" ) (vvPair variable "config" value "%(unit)_%(view)_config" ) (vvPair variable "d" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@bus@width@adaption" ) (vvPair variable "d_logical" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifoBridgeBusWidthAdaption" ) (vvPair variable "date" value "08/28/19" ) (vvPair variable "day" value "Wed" ) (vvPair variable "day_long" value "Wednesday" ) (vvPair variable "dd" value "28" ) (vvPair variable "designName" value "$DESIGN_NAME" ) (vvPair variable "entity_name" value "fifoBridgeBusWidthAdaption" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "symbol.sb" ) (vvPair variable "f_logical" value "symbol.sb" ) (vvPair variable "f_noext" value "symbol" ) (vvPair variable "graphical_source_author" value "francois" ) (vvPair variable "graphical_source_date" value "08/28/19" ) (vvPair variable "graphical_source_group" value "francois" ) (vvPair variable "graphical_source_host" value "Aphelia" ) (vvPair variable "graphical_source_time" value "13:45:15" ) (vvPair variable "group" value "francois" ) (vvPair variable "host" value "Aphelia" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "Memory" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/Libs/Memory/work" ) (vvPair variable "mm" value "08" ) (vvPair variable "module_name" value "fifoBridgeBusWidthAdaption" ) (vvPair variable "month" value "Aug" ) (vvPair variable "month_long" value "August" ) (vvPair variable "p" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@bus@width@adaption/symbol.sb" ) (vvPair variable "p_logical" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifoBridgeBusWidthAdaption/symbol.sb" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "hds" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_HDSPath" value "$HDS_HOME" ) (vvPair variable "task_ISEBinPath" value "$ISE_HOME" ) (vvPair variable "task_ISEPath" value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" ) (vvPair variable "task_ModelSimPath" value "$MODELSIM_HOME\\win32" ) (vvPair variable "this_ext" value "sb" ) (vvPair variable "this_file" value "symbol" ) (vvPair variable "this_file_logical" value "symbol" ) (vvPair variable "time" value "13:45:15" ) (vvPair variable "unit" value "fifoBridgeBusWidthAdaption" ) (vvPair variable "user" value "francois" ) (vvPair variable "version" value "2018.1 (Build 12)" ) (vvPair variable "view" value "symbol" ) (vvPair variable "year" value "2019" ) (vvPair variable "yy" value "19" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 51,0 optionalChildren [ *71 (SymbolBody uid 8,0 optionalChildren [ *72 (CptPort uid 108,0 ps "OnEdgeStrategy" shape (Triangle uid 109,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,21625,15000,22375" ) tg (CPTG uid 110,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 111,0 va (VaSet ) xt "16000,21500,18100,22500" st "clock" blo "16000,22300" tm "CptPortNameMgr" ) ) dt (MLText uid 112,0 va (VaSet font "courier,8,0" ) xt "44000,8300,58500,9200" st "clock : IN std_ulogic " ) thePort (LogicalPort decl (Decl n "clock" t "std_ulogic" o 8 suid 1,0 ) ) ) *73 (CptPort uid 113,0 ps "OnEdgeStrategy" shape (Triangle uid 114,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "23000,15625,23750,16375" ) tg (CPTG uid 115,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 116,0 va (VaSet ) xt "19400,15500,22000,16500" st "dataTx" ju 2 blo "22000,16300" tm "CptPortNameMgr" ) ) dt (MLText uid 117,0 va (VaSet font "courier,8,0" ) xt "44000,2000,75000,2900" st "dataTx : OUT std_ulogic_vector (dataBitNbTx-1 DOWNTO 0) ;" ) thePort (LogicalPort m 1 decl (Decl n "dataTx" t "std_ulogic_vector" b "(dataBitNbTx-1 DOWNTO 0)" o 1 suid 2,0 ) ) ) *74 (CptPort uid 118,0 ps "OnEdgeStrategy" shape (Triangle uid 119,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,15625,15000,16375" ) tg (CPTG uid 120,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 121,0 va (VaSet ) xt "16000,15500,18700,16500" st "dataRx" blo "16000,16300" tm "CptPortNameMgr" ) ) dt (MLText uid 122,0 va (VaSet font "courier,8,0" ) xt "44000,2900,75000,3800" st "dataRx : IN std_ulogic_vector (dataBitNbRx-1 DOWNTO 0) ;" ) thePort (LogicalPort decl (Decl n "dataRx" t "std_ulogic_vector" b "(dataBitNbRx-1 DOWNTO 0)" o 2 suid 3,0 ) ) ) *75 (CptPort uid 123,0 ps "OnEdgeStrategy" shape (Triangle uid 124,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,17625,15000,18375" ) tg (CPTG uid 125,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 126,0 va (VaSet ) xt "16000,17500,19200,18500" st "emptyRx" blo "16000,18300" tm "CptPortNameMgr" ) ) dt (MLText uid 127,0 va (VaSet font "courier,8,0" ) xt "44000,5600,59500,6500" st "emptyRx : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "emptyRx" t "std_ulogic" o 5 suid 4,0 ) ) ) *76 (CptPort uid 128,0 ps "OnEdgeStrategy" shape (Triangle uid 129,0 ro 270 va (VaSet vasetType 1 fg "0,65535,0" ) xt "23000,17625,23750,18375" ) tg (CPTG uid 130,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 131,0 va (VaSet ) xt "19800,17500,22000,18500" st "fullTx" ju 2 blo "22000,18300" tm "CptPortNameMgr" ) ) dt (MLText uid 132,0 va (VaSet font "courier,8,0" ) xt "44000,3800,59500,4700" st "fullTx : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "fullTx" t "std_ulogic" o 3 suid 5,0 ) ) ) *77 (CptPort uid 133,0 ps "OnEdgeStrategy" shape (Triangle uid 134,0 ro 270 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,19625,15000,20375" ) tg (CPTG uid 135,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 136,0 va (VaSet ) xt "16000,19500,18800,20500" st "readRx" blo "16000,20300" tm "CptPortNameMgr" ) ) dt (MLText uid 137,0 va (VaSet font "courier,8,0" ) xt "44000,7400,59500,8300" st "readRx : OUT std_ulogic ;" ) thePort (LogicalPort m 1 decl (Decl n "readRx" t "std_ulogic" o 7 suid 6,0 ) ) ) *78 (CptPort uid 138,0 ps "OnEdgeStrategy" shape (Triangle uid 139,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,23625,15000,24375" ) tg (CPTG uid 140,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 141,0 va (VaSet ) xt "16000,23500,18100,24500" st "reset" blo "16000,24300" tm "CptPortNameMgr" ) ) dt (MLText uid 142,0 va (VaSet font "courier,8,0" ) xt "44000,6500,59500,7400" st "reset : IN std_uLogic ;" ) thePort (LogicalPort decl (Decl n "reset" t "std_uLogic" o 6 suid 7,0 ) ) ) *79 (CptPort uid 143,0 ps "OnEdgeStrategy" shape (Triangle uid 144,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "23000,19625,23750,20375" ) tg (CPTG uid 145,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 146,0 va (VaSet ) xt "19200,19500,22000,20500" st "writeTx" ju 2 blo "22000,20300" tm "CptPortNameMgr" ) ) dt (MLText uid 147,0 va (VaSet font "courier,8,0" ) xt "44000,4700,59500,5600" st "writeTx : OUT std_ulogic ;" ) thePort (LogicalPort m 1 decl (Decl n "writeTx" t "std_ulogic" o 4 suid 8,0 ) ) ) ] shape (Rectangle uid 187,0 va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,14000,23000,26000" ) oxt "15000,6000,33000,26000" biTextGroup (BiTextGroup uid 10,0 ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text uid 11,0 va (VaSet font "courier,8,1" ) xt "15600,26000,18600,26900" st "Memory" blo "15600,26700" ) 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