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dialect 11
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unitName "std_logic_1164"
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VExpander (VariableExpander
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(vvPair
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value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
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(vvPair
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(vvPair
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)
(vvPair
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value "08/28/19"
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(vvPair
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(vvPair
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(vvPair
variable "designName"
value "$DESIGN_NAME"
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(vvPair
variable "entity_name"
value "flashController"
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value "<TBD>"
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value "symbol.sb"
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variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
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value "francois"
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(vvPair
variable "graphical_source_date"
value "08/28/19"
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(vvPair
variable "graphical_source_group"
value "francois"
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(vvPair
variable "graphical_source_host"
value "Aphelia"
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(vvPair
variable "graphical_source_time"
value "13:45:14"
)
(vvPair
variable "group"
value "francois"
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(vvPair
variable "host"
value "Aphelia"
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(vvPair
variable "language"
value "VHDL"
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(vvPair
variable "library"
value "Memory"
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)
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)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "flashController"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/flash@controller/symbol.sb"
)
(vvPair
variable "p_logical"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/flashController/symbol.sb"
)
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variable "package_name"
value "<Undefined Variable>"
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variable "project_name"
value "hds"
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variable "series"
value "HDL Designer Series"
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value "<TBD>"
)
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value "$HDS_HOME"
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value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR"
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(vvPair
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value "<TBD>"
)
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variable "task_ModelSimPath"
value "$MODELSIM_HOME\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
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value "sb"
)
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value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
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variable "time"
value "13:45:14"
)
(vvPair
variable "unit"
value "flashController"
)
(vvPair
variable "user"
value "francois"
)
(vvPair
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value "2018.1 (Build 12)"
)
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value "symbol"
)
(vvPair
variable "year"
value "2019"
)
(vvPair
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value "19"
)
]
)
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)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "courier,8,0"
)
xt "0,750,3500,1650"
st "Buffer0"
blo "0,1450"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "courier,8,0"
)
)
thePort (LogicalPort
lang 11
m 3
decl (Decl
n "Buffer0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
DeclarativeBlock *132 (SymDeclBlock
uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "courier,8,1"
)
xt "-2000,10400,3400,11400"
st "Declarations"
blo "-2000,11200"
)
portLabel (Text
uid 3,0
va (VaSet
font "courier,8,1"
)
xt "-2000,11400,700,12400"
st "Ports:"
blo "-2000,12200"
)
externalLabel (Text
uid 4,0
va (VaSet
font "courier,8,1"
)
xt "-2000,28600,500,29500"
st "User:"
blo "-2000,29300"
)
internalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "courier,8,1"
)
xt "-2000,10400,3800,11400"
st "Internal User:"
blo "-2000,11200"
)
externalText (MLText
uid 5,0
va (VaSet
font "courier,8,0"
)
xt "0,29500,0,29500"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
uid 7,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-2000,10400,-2000,10400"
tm "SyDeclarativeTextMgr"
)
)
lastUid 800,0
okToSyncOnLoad 1
OkToSyncGenericsOnLoad 1
activeModelName "Symbol:GEN"
)