DocumentHdrVersion "1.1" Header (DocumentHdr version 2 dialect 11 dmPackageRefs [ (DmPackageRef library "ieee" unitName "std_logic_1164" ) (DmPackageRef library "ieee" unitName "numeric_std" ) ] libraryRefs [ "ieee" ] ) version "26.1" appVersion "2018.1 (Build 12)" model (Symbol commonDM (CommonDM ldm (LogicalDM suid 24,0 usingSuid 1 emptyRow *1 (LEmptyRow ) uid 81,0 optionalChildren [ *2 (RefLabelRowHdr ) *3 (TitleRowHdr ) *4 (FilterRowHdr ) *5 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *6 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *7 (GroupColHdr tm "GroupColHdrMgr" ) *8 (NameColHdr tm "NameColHdrMgr" ) *9 (ModeColHdr tm "ModeColHdrMgr" ) *10 (TypeColHdr tm "TypeColHdrMgr" ) *11 (BoundsColHdr tm "BoundsColHdrMgr" ) *12 (InitColHdr tm "InitColHdrMgr" ) *13 (EolColHdr tm "EolColHdrMgr" ) *14 (LogPort port (LogicalPort decl (Decl n "addrSelCol" t "std_ulogic" o 26 suid 18,0 ) ) uid 360,0 ) *15 (LogPort port (LogicalPort decl (Decl n "addrSelModeReg" t "std_ulogic" o 26 suid 19,0 ) ) uid 362,0 ) *16 (LogPort port (LogicalPort decl (Decl n "addrSelPrecharge" t "std_ulogic" o 26 suid 20,0 ) ) uid 364,0 ) *17 (LogPort port (LogicalPort decl (Decl n "addrSelRow" t "std_ulogic" o 26 suid 21,0 ) ) uid 366,0 ) *18 (LogPort port (LogicalPort m 1 decl (Decl n "memAddress" t "std_ulogic_vector" b "( chipAddressBitNb-1 DOWNTO 0 )" o 9 suid 22,0 ) ) uid 368,0 ) *19 (LogPort port (LogicalPort m 1 decl (Decl n "memBankAddress" t "std_ulogic_vector" b "( chipBankAddressBitNb-1 DOWNTO 0 )" o 10 suid 23,0 ) ) uid 370,0 ) *20 (LogPort port (LogicalPort decl (Decl n "ramAddr" t "unsigned" b "(addressBitNb-1 DOWNTO 0)" o 3 suid 24,0 ) ) uid 372,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 94,0 optionalChildren [ *21 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "courier,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "courier,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "courier,10,0" ) emptyMRCItem *22 (MRCItem litem &1 pos 7 dimension 20 ) uid 96,0 optionalChildren [ *23 (MRCItem litem &2 pos 0 dimension 20 uid 97,0 ) *24 (MRCItem litem &3 pos 1 dimension 23 uid 98,0 ) *25 (MRCItem litem &4 pos 2 hidden 1 dimension 20 uid 99,0 ) *26 (MRCItem litem &14 pos 0 dimension 20 uid 361,0 ) *27 (MRCItem litem &15 pos 1 dimension 20 uid 363,0 ) *28 (MRCItem litem &16 pos 2 dimension 20 uid 365,0 ) *29 (MRCItem litem &17 pos 3 dimension 20 uid 367,0 ) *30 (MRCItem litem &18 pos 4 dimension 20 uid 369,0 ) *31 (MRCItem litem &19 pos 5 dimension 20 uid 371,0 ) *32 (MRCItem litem &20 pos 6 dimension 20 uid 373,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "courier,10,0" textAngle 90 ) uid 100,0 optionalChildren [ *33 (MRCItem litem &5 pos 0 dimension 20 uid 101,0 ) *34 (MRCItem litem &7 pos 1 dimension 50 uid 102,0 ) *35 (MRCItem litem &8 pos 2 dimension 100 uid 103,0 ) *36 (MRCItem litem &9 pos 3 dimension 50 uid 104,0 ) *37 (MRCItem litem &10 pos 4 dimension 100 uid 105,0 ) *38 (MRCItem litem &11 pos 5 dimension 100 uid 106,0 ) *39 (MRCItem litem &12 pos 6 dimension 50 uid 107,0 ) *40 (MRCItem litem &13 pos 7 dimension 80 uid 108,0 ) ] ) fixedCol 4 fixedRow 2 name "Ports" uid 95,0 vaOverrides [ ] ) ] ) uid 80,0 ) genericsCommonDM (CommonDM ldm (LogicalDM emptyRow *41 (LEmptyRow ) uid 110,0 optionalChildren [ *42 (RefLabelRowHdr ) *43 (TitleRowHdr ) *44 (FilterRowHdr ) *45 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *46 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *47 (GroupColHdr tm "GroupColHdrMgr" ) *48 (NameColHdr tm "GenericNameColHdrMgr" ) *49 (TypeColHdr tm "GenericTypeColHdrMgr" ) *50 (InitColHdr tm "GenericValueColHdrMgr" ) *51 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) *52 (EolColHdr tm "GenericEolColHdrMgr" ) *53 (LogGeneric generic (GiElement name "addressBitNb" type "positive" value "24" ) uid 159,0 ) *54 (LogGeneric generic (GiElement name "chipAddressBitNb" type "positive" value "12" ) uid 161,0 ) *55 (LogGeneric generic (GiElement name "chipBankAddressBitNb" type "positive" value "2" ) uid 163,0 ) *56 (LogGeneric generic (GiElement name "rowAddressBitNb" type "positive" value "12" ) uid 420,0 ) *57 (LogGeneric generic (GiElement name "colAddressBitNb" type "positive" value "2" ) uid 422,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 122,0 optionalChildren [ *58 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "courier,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "courier,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "courier,10,0" ) emptyMRCItem *59 (MRCItem litem &41 pos 5 dimension 20 ) uid 124,0 optionalChildren [ *60 (MRCItem litem &42 pos 0 dimension 20 uid 125,0 ) *61 (MRCItem litem &43 pos 1 dimension 23 uid 126,0 ) *62 (MRCItem litem &44 pos 2 hidden 1 dimension 20 uid 127,0 ) *63 (MRCItem litem &53 pos 0 dimension 20 uid 160,0 ) *64 (MRCItem litem &54 pos 1 dimension 20 uid 162,0 ) *65 (MRCItem litem &55 pos 2 dimension 20 uid 164,0 ) *66 (MRCItem litem &56 pos 3 dimension 20 uid 421,0 ) *67 (MRCItem litem &57 pos 4 dimension 20 uid 423,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "courier,10,0" textAngle 90 ) uid 128,0 optionalChildren [ *68 (MRCItem litem &45 pos 0 dimension 20 uid 129,0 ) *69 (MRCItem litem &47 pos 1 dimension 50 uid 130,0 ) *70 (MRCItem litem &48 pos 2 dimension 100 uid 131,0 ) *71 (MRCItem litem &49 pos 3 dimension 100 uid 132,0 ) *72 (MRCItem litem &50 pos 4 dimension 50 uid 133,0 ) *73 (MRCItem litem &51 pos 5 dimension 50 uid 134,0 ) *74 (MRCItem litem &52 pos 6 dimension 80 uid 135,0 ) ] ) fixedCol 3 fixedRow 2 name "Ports" uid 123,0 vaOverrides [ ] ) ] ) uid 109,0 type 1 ) VExpander (VariableExpander vvMap [ (vvPair variable "HDLDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hdl" ) (vvPair variable "HDSDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" ) (vvPair variable "SideDataDesignDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@build@address/symbol.sb.info" ) (vvPair variable "SideDataUserDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@build@address/symbol.sb.user" ) (vvPair variable "SourceDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "symbol" ) (vvPair variable "concat_file" value "concatenated" ) (vvPair variable "config" value "%(unit)_%(view)_config" ) (vvPair variable "d" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@build@address" ) (vvPair variable "d_logical" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerBuildAddress" ) (vvPair variable "date" value "08/28/19" ) (vvPair variable "day" value "Wed" ) (vvPair variable "day_long" value "Wednesday" ) (vvPair variable "dd" value "28" ) (vvPair variable "designName" value "$DESIGN_NAME" ) (vvPair variable "entity_name" value "sdramControllerBuildAddress" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "symbol.sb" ) (vvPair variable "f_logical" value "symbol.sb" ) (vvPair variable "f_noext" value "symbol" ) (vvPair variable "graphical_source_author" value "francois" ) (vvPair variable "graphical_source_date" value "08/28/19" ) (vvPair variable "graphical_source_group" value "francois" ) (vvPair variable "graphical_source_host" value "Aphelia" ) (vvPair variable "graphical_source_time" value "13:45:14" ) (vvPair variable "group" value "francois" ) (vvPair variable "host" value "Aphelia" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "Memory" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/Libs/Memory/work" ) (vvPair variable "mm" value "08" ) (vvPair variable "module_name" value "sdramControllerBuildAddress" ) (vvPair variable "month" value "Aug" ) (vvPair variable "month_long" value "August" ) (vvPair variable "p" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@build@address/symbol.sb" ) (vvPair variable "p_logical" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerBuildAddress/symbol.sb" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "hds" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_DesignCompilerPath" value "" ) (vvPair variable "task_HDSPath" value "$HDS_HOME" ) (vvPair variable "task_ISEBinPath" value "$ISE_HOME" ) (vvPair variable "task_ISEPath" value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" ) (vvPair variable "task_LeonardoPath" value "" ) (vvPair variable "task_ModelSimPath" value "$MODELSIM_HOME\\win32" ) (vvPair variable "task_NC-SimPath" value "" ) (vvPair variable "task_PrecisionRTLPath" value "" ) (vvPair variable "task_QuestaSimPath" value "" ) (vvPair variable "task_VCSPath" value "" ) (vvPair variable "this_ext" value "sb" ) (vvPair variable "this_file" value "symbol" ) (vvPair variable "this_file_logical" value "symbol" ) (vvPair variable "time" value "13:45:14" ) (vvPair variable "unit" value "sdramControllerBuildAddress" ) (vvPair variable "user" value "francois" ) (vvPair variable "version" value "2018.1 (Build 12)" ) (vvPair variable "view" value "symbol" ) (vvPair variable "year" value "2019" ) (vvPair variable "yy" value "19" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 79,0 optionalChildren [ *75 (SymbolBody uid 8,0 optionalChildren [ *76 (CptPort uid 325,0 ps "OnEdgeStrategy" shape (Triangle uid 326,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33250,17625,34000,18375" ) tg (CPTG uid 327,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 328,0 va (VaSet ) xt "35000,17500,39600,18500" st "addrSelCol" blo "35000,18300" tm "CptPortNameMgr" ) ) dt (MLText uid 329,0 va (VaSet font "courier,8,0" ) xt "0,30400,20000,31300" st "addrSelCol : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "addrSelCol" t "std_ulogic" o 26 suid 18,0 ) ) ) *77 (CptPort uid 330,0 ps "OnEdgeStrategy" shape (Triangle uid 331,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33250,13625,34000,14375" ) tg (CPTG uid 332,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 333,0 va (VaSet ) xt "35000,13500,41800,14500" st "addrSelModeReg" blo "35000,14300" tm "CptPortNameMgr" ) ) dt (MLText uid 334,0 va (VaSet font "courier,8,0" ) xt "0,31300,20000,32200" st "addrSelModeReg : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "addrSelModeReg" t "std_ulogic" o 26 suid 19,0 ) ) ) *78 (CptPort uid 335,0 ps "OnEdgeStrategy" shape (Triangle uid 336,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33250,11625,34000,12375" ) tg (CPTG uid 337,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 338,0 va (VaSet ) xt "35000,11500,42000,12500" st "addrSelPrecharge" blo "35000,12300" tm "CptPortNameMgr" ) ) dt (MLText uid 339,0 va (VaSet font "courier,8,0" ) xt "0,32200,20000,33100" st "addrSelPrecharge : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "addrSelPrecharge" t "std_ulogic" o 26 suid 20,0 ) ) ) *79 (CptPort uid 340,0 ps "OnEdgeStrategy" shape (Triangle uid 341,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33250,15625,34000,16375" ) tg (CPTG uid 342,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 343,0 va (VaSet ) xt "35000,15500,39900,16500" st "addrSelRow" blo "35000,16300" tm "CptPortNameMgr" ) ) dt (MLText uid 344,0 va (VaSet font "courier,8,0" ) xt "0,33100,20000,34000" st "addrSelRow : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "addrSelRow" t "std_ulogic" o 26 suid 21,0 ) ) ) *80 (CptPort uid 345,0 ps "OnEdgeStrategy" shape (Triangle uid 346,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "50000,9625,50750,10375" ) tg (CPTG uid 347,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 348,0 va (VaSet ) xt "43800,9500,49000,10500" st "memAddress" ju 2 blo "49000,10300" tm "CptPortNameMgr" ) ) dt (MLText uid 349,0 va (VaSet font "courier,8,0" ) xt "0,34900,39000,35800" st "memAddress : OUT std_ulogic_vector ( chipAddressBitNb-1 DOWNTO 0 ) ;" ) thePort (LogicalPort m 1 decl (Decl n "memAddress" t "std_ulogic_vector" b "( chipAddressBitNb-1 DOWNTO 0 )" o 9 suid 22,0 ) ) ) *81 (CptPort uid 350,0 ps "OnEdgeStrategy" shape (Triangle uid 351,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "50000,11625,50750,12375" ) tg (CPTG uid 352,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 353,0 va (VaSet ) xt "42200,11500,49000,12500" st "memBankAddress" ju 2 blo "49000,12300" tm "CptPortNameMgr" ) ) dt (MLText uid 354,0 va (VaSet font "courier,8,0" ) xt "0,35800,40000,36700" st "memBankAddress : OUT std_ulogic_vector ( chipBankAddressBitNb-1 DOWNTO 0 )" ) thePort (LogicalPort m 1 decl (Decl n "memBankAddress" t "std_ulogic_vector" b "( chipBankAddressBitNb-1 DOWNTO 0 )" o 10 suid 23,0 ) ) ) *82 (CptPort uid 355,0 ps "OnEdgeStrategy" shape (Triangle uid 356,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33250,9625,34000,10375" ) tg (CPTG uid 357,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 358,0 va (VaSet ) xt "35000,9500,38300,10500" st "ramAddr" blo "35000,10300" tm "CptPortNameMgr" ) ) dt (MLText uid 359,0 va (VaSet font "courier,8,0" ) xt "0,34000,31500,34900" st "ramAddr : IN unsigned (addressBitNb-1 DOWNTO 0) ;" ) thePort (LogicalPort decl (Decl n "ramAddr" t "unsigned" b "(addressBitNb-1 DOWNTO 0)" o 3 suid 24,0 ) ) ) ] shape (Rectangle uid 9,0 va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "34000,6000,50000,22000" ) oxt "15000,6000,31000,23000" biTextGroup (BiTextGroup uid 10,0 ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text uid 11,0 va (VaSet font "courier,8,1" ) xt "33850,22500,36850,23400" st "Memory" blo "33850,23200" ) second (Text uid 12,0 va (VaSet font "courier,8,1" ) xt "33850,23400,47850,24300" st "sdramControllerBuildAddress" blo "33850,24100" ) ) gi *83 (GenericInterface uid 13,0 ps "CenterOffsetStrategy" matrix (Matrix uid 14,0 text (MLText uid 15,0 va (VaSet font "courier,8,0" ) xt "34000,26000,51500,32300" st "Generic Declarations addressBitNb positive 24 chipAddressBitNb positive 12 chipBankAddressBitNb positive 2 rowAddressBitNb positive 12 colAddressBitNb positive 2 " ) header "Generic Declarations" showHdrWhenContentsEmpty 1 ) elements [ (GiElement name "addressBitNb" type "positive" value "24" ) (GiElement name "chipAddressBitNb" type "positive" value "12" ) (GiElement name "chipBankAddressBitNb" type "positive" value "2" ) (GiElement name "rowAddressBitNb" type "positive" value "12" ) (GiElement name "colAddressBitNb" type "positive" value "2" ) ] ) portInstanceVisAsIs 1 portInstanceVis (PortSigDisplay sTC 0 sF 0 ) portVis (PortSigDisplay sTC 0 sF 0 ) ) *84 (Grouping uid 16,0 optionalChildren [ *85 (CommentText uid 18,0 shape (Rectangle uid 19,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "34000,48000,51000,49000" ) oxt "18000,70000,35000,71000" text (MLText uid 20,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "34200,48000,49200,49000" st " by %user on %dd %month %year " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 titleBlock 1 ) *86 (CommentText uid 21,0 shape (Rectangle uid 22,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "51000,44000,55000,45000" ) oxt "35000,66000,39000,67000" text (MLText uid 23,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "51200,44000,54800,45000" st " Project: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *87 (CommentText uid 24,0 shape (Rectangle uid 25,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "34000,46000,51000,47000" ) oxt "18000,68000,35000,69000" text (MLText uid 26,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "34200,46000,50400,47000" st " " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 titleBlock 1 ) *88 (CommentText uid 27,0 shape (Rectangle uid 28,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "30000,46000,34000,47000" ) oxt "14000,68000,18000,69000" text (MLText uid 29,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "30200,46000,33800,47000" st " Title: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *89 (CommentText uid 30,0 shape (Rectangle uid 31,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "51000,45000,71000,49000" ) oxt "35000,67000,55000,71000" text (MLText uid 32,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "51200,45200,64400,46200" st " " tm "CommentText" wrapOption 3 visibleHeight 4000 visibleWidth 20000 ) ignorePrefs 1 titleBlock 1 ) *90 (CommentText uid 33,0 shape (Rectangle uid 34,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "55000,44000,71000,45000" ) oxt "39000,66000,55000,67000" text (MLText uid 35,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "55200,44000,57000,45000" st " %project_name " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 16000 ) position 1 ignorePrefs 1 titleBlock 1 ) *91 (CommentText uid 36,0 shape (Rectangle uid 37,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "30000,44000,51000,46000" ) oxt "14000,66000,35000,68000" text (MLText uid 38,0 va (VaSet fg "32768,0,0" ) xt "36000,44500,45000,45500" st " " ju 0 tm "CommentText" wrapOption 3 visibleHeight 2000 visibleWidth 21000 ) position 1 ignorePrefs 1 titleBlock 1 ) *92 (CommentText uid 39,0 shape (Rectangle uid 40,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "30000,47000,34000,48000" ) oxt "14000,69000,18000,70000" text (MLText uid 41,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "30200,47000,33200,48000" st " Path: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *93 (CommentText uid 42,0 shape (Rectangle uid 43,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "30000,48000,34000,49000" ) oxt "14000,70000,18000,71000" text (MLText uid 44,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "30200,48000,33800,49000" st " Edited: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *94 (CommentText uid 45,0 shape (Rectangle uid 46,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "34000,47000,51000,48000" ) oxt "18000,69000,35000,70000" text (MLText uid 47,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "34200,47000,44400,48000" st " %library/%unit/%view " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 titleBlock 1 ) ] shape (GroupingShape uid 17,0 va (VaSet vasetType 1 fg "65535,65535,65535" lineStyle 2 lineWidth 2 ) xt "30000,44000,71000,49000" ) oxt "14000,66000,55000,71000" ) ] bg "65535,65535,65535" grid (Grid origin "0,0" isVisible 1 isActive 1 xSpacing 1000 xySpacing 1000 xShown 1 yShown 1 color "26368,26368,26368" ) packageList *95 (PackageList uid 48,0 stg "VerticalLayoutStrategy" textVec [ *96 (Text uid 49,0 va (VaSet font "courier,8,1" ) xt "-2000,0,3400,1000" st "Package List" blo "-2000,800" ) *97 (MLText uid 50,0 va (VaSet ) xt "-2000,1000,16600,4000" st "LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;" tm "PackageList" ) ] ) windowSize "11,45,1386,982" viewArea "-3100,-1100,72602,50512" cachedDiagramExtent "-2000,0,71000,49000" hasePageBreakOrigin 1 pageBreakOrigin "-2000,0" defaultCommentText (CommentText shape (Rectangle layer 0 va (VaSet vasetType 1 fg "65280,65280,46080" lineColor "0,0,32768" ) xt "0,0,15000,5000" ) text (MLText va (VaSet fg "0,0,32768" ) xt "200,200,2600,1200" st " Text " tm "CommentText" wrapOption 3 visibleHeight 4600 visibleWidth 14600 ) ) defaultRequirementText (RequirementText shape (ZoomableIcon layer 0 va (VaSet vasetType 1 fg "59904,39936,65280" lineColor "0,0,32768" ) xt "0,0,1500,1750" iconName "reqTracerRequirement.bmp" iconMaskName "reqTracerRequirement.msk" ) autoResize 1 text (MLText va (VaSet fg "0,0,32768" font "courier,8,0" ) xt "450,2150,1450,3050" st " Text " tm "RequirementText" wrapOption 3 visibleHeight 1350 visibleWidth 1100 ) ) defaultPanel (Panel shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "32768,0,0" lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (Text va (VaSet font "courier,8,1" ) xt "1000,1000,3800,2000" st "Panel0" blo "1000,1800" tm "PanelText" ) ) ) parentGraphicsRef (HdmGraphicsRef libraryName "memory" entityName "sdramController" viewName "struct.bd" ) defaultSymbolBody (SymbolBody shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,6000,33000,26000" ) biTextGroup (BiTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text va (VaSet font "courier,8,1" ) xt "22200,15000,25800,16000" st "" blo "22200,15800" ) second (Text va (VaSet font "courier,8,1" ) xt "22200,16000,24800,17000" st "" blo "22200,16800" ) ) gi *98 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix text (MLText va (VaSet font "courier,8,0" ) xt "0,12000,10500,12900" st "Generic Declarations" ) header "Generic Declarations" showHdrWhenContentsEmpty 1 ) elements [ ] ) portInstanceVisAsIs 1 portInstanceVis (PortSigDisplay sIVOD 1 ) portVis (PortSigDisplay sIVOD 1 ) ) defaultCptPort (CptPort ps "OnEdgeStrategy" shape (Triangle ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet font "courier,8,0" ) xt "0,750,1500,1650" st "In0" blo "0,1450" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "courier,8,0" ) ) thePort (LogicalPort lang 11 decl (Decl n "In0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) defaultCptPortBuffer (CptPort ps "OnEdgeStrategy" shape (Diamond va (VaSet vasetType 1 fg "65535,65535,65535" bg "0,0,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet font "courier,8,0" ) xt "0,750,3500,1650" st "Buffer0" blo "0,1450" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "courier,8,0" ) ) thePort (LogicalPort lang 11 m 3 decl (Decl n "Buffer0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) DeclarativeBlock *99 (SymDeclBlock uid 1,0 stg "SymDeclLayoutStrategy" declLabel (Text uid 2,0 va (VaSet font "courier,8,1" ) xt "-2000,28400,3400,29400" st "Declarations" blo "-2000,29200" ) portLabel (Text uid 3,0 va (VaSet font "courier,8,1" ) xt "-2000,29400,700,30400" st "Ports:" blo "-2000,30200" ) externalLabel (Text uid 4,0 va (VaSet font "courier,8,1" ) xt "-2000,36700,500,37600" st "User:" blo "-2000,37400" ) internalLabel (Text uid 6,0 va (VaSet isHidden 1 font "courier,8,1" ) xt "-2000,28400,3800,29400" st "Internal User:" blo "-2000,29200" ) externalText (MLText uid 5,0 va (VaSet font "courier,8,0" ) xt "0,37600,0,37600" tm "SyDeclarativeTextMgr" ) internalText (MLText uid 7,0 va (VaSet isHidden 1 font "courier,8,0" ) xt "-2000,28400,-2000,28400" tm "SyDeclarativeTextMgr" ) ) lastUid 446,0 activeModelName "Symbol:GEN" )