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"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor4\\symbol.sb.info" ) (vvPair variable "SideDataUserDir" value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor4\\symbol.sb.user" ) (vvPair variable "SourceDir" value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "symbol" ) (vvPair variable "concat_file" value "concatenated" ) (vvPair variable "config" value "%(unit)_%(view)_config" ) (vvPair variable "d" value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor4" ) (vvPair variable "d_logical" value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor4" ) (vvPair variable "date" value "11.09.2019" ) (vvPair variable "day" value "Wed" ) (vvPair variable "day_long" value "Wednesday" ) (vvPair variable "dd" value "11" ) (vvPair variable "entity_name" value "xor4" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "symbol.sb" ) (vvPair variable "f_logical" value "symbol.sb" ) (vvPair variable "f_noext" value "symbol" ) (vvPair variable "graphical_source_author" value "silvan.zahno" ) (vvPair variable "graphical_source_date" value "11.09.2019" ) (vvPair variable "graphical_source_group" value "UNKNOWN" ) (vvPair variable "graphical_source_host" value "WE6996" ) (vvPair variable "graphical_source_time" value "14:35:02" ) (vvPair variable "group" value "UNKNOWN" ) (vvPair variable "host" value "WE6996" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "gates" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/ElN/Libraries/Gates/work" ) (vvPair variable "mm" value "09" ) (vvPair variable "module_name" value "xor4" ) (vvPair variable "month" value "Sep" ) (vvPair variable "month_long" value "September" ) (vvPair variable "p" value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor4\\symbol.sb" ) (vvPair variable "p_logical" value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor4\\symbol.sb" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "hds" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_DesignCompilerPath" value "" ) (vvPair variable "task_ISEPath" value "D:\\Labs\\ElN\\Board\\Board\\ise" ) (vvPair variable "task_LeonardoPath" value "" ) (vvPair variable "task_ModelSimPath" value "c:\\eda\\modelsim\\win32" ) (vvPair variable "task_NC-SimPath" value "" ) (vvPair variable "task_PrecisionRTLPath" value "" ) (vvPair variable "task_QuestaSimPath" value "" ) (vvPair variable "task_VCSPath" value "" ) (vvPair variable "this_ext" value "sb" ) (vvPair variable "this_file" value "symbol" ) (vvPair variable "this_file_logical" value "symbol" ) (vvPair variable "time" value "14:35:02" ) (vvPair variable "unit" value "xor4" ) (vvPair variable "user" value "silvan.zahno" ) (vvPair variable "version" value "2018.1 (Build 12)" ) (vvPair variable "view" value "symbol" ) (vvPair variable "year" value "2019" ) (vvPair variable "yy" value "19" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 51,0 optionalChildren [ *63 (SymbolBody uid 8,0 optionalChildren [ *64 (CptPort uid 52,0 ps "OnEdgeStrategy" shape (Triangle uid 53,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33632,12625,34382,13375" ) tg (CPTG uid 54,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 55,0 va (VaSet isHidden 1 ) xt "35382,12350,36782,13350" st "in1" blo "35382,13150" tm "CptPortNameMgr" ) ) dt (MLText uid 56,0 va (VaSet font "Verdana,8,0" ) xt "2000,10800,14000,11800" st "in1 : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "in1" t "std_ulogic" o 1 suid 1,0 ) ) ) *65 (CptPort uid 57,0 ps "OnEdgeStrategy" shape (Triangle uid 58,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33973,13625,34723,14375" ) tg (CPTG uid 59,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 60,0 va (VaSet isHidden 1 ) xt "35723,13350,37123,14350" st "in2" blo "35723,14150" tm "CptPortNameMgr" ) ) dt (MLText uid 61,0 va (VaSet font "Verdana,8,0" ) xt "2000,11700,14000,12700" st "in2 : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "in2" t "std_ulogic" o 1 suid 2,0 ) ) ) *66 (CptPort uid 62,0 ps "OnEdgeStrategy" shape (Triangle uid 63,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33971,15625,34721,16375" ) tg (CPTG uid 64,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 65,0 va (VaSet isHidden 1 ) xt "35721,15350,37121,16350" st "in3" blo "35721,16150" tm "CptPortNameMgr" ) ) dt (MLText uid 66,0 va (VaSet font "Verdana,8,0" ) xt "2000,12600,14000,13600" st "in3 : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "in3" t "std_ulogic" o 1 suid 3,0 ) ) ) *67 (CptPort uid 67,0 ps "OnEdgeStrategy" shape (Triangle uid 68,0 ro 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"65535,65535,65535" grid (Grid origin "0,0" isVisible 1 isActive 1 xSpacing 1000 xySpacing 1000 xShown 1 yShown 1 color "32768,32768,32768" ) packageList *81 (PackageList uid 48,0 stg "VerticalLayoutStrategy" textVec [ *82 (Text uid 83,0 va (VaSet font "Verdana,8,1" ) xt "0,0,5400,1000" st "Package List" blo "0,800" ) *83 (MLText uid 84,0 va (VaSet ) xt "0,1000,17500,5800" st "LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY gates; USE gates.gates.all;" tm "PackageList" ) ] ) windowSize "15,54,1370,927" viewArea "-1000,-1000,77384,51371" cachedDiagramExtent "0,0,73000,49000" hasePageBreakOrigin 1 pageBreakOrigin "0,0" defaultCommentText (CommentText shape (Rectangle layer 0 va (VaSet vasetType 1 fg "65280,65280,46080" lineColor "0,0,32768" ) xt "0,0,15000,5000" ) text (MLText va (VaSet fg "0,0,32768" ) xt "200,200,3200,1400" st " Text " tm "CommentText" wrapOption 3 visibleHeight 4600 visibleWidth 14600 ) ) defaultRequirementText (RequirementText shape (ZoomableIcon layer 0 va (VaSet vasetType 1 fg "59904,39936,65280" lineColor "0,0,32768" ) xt "0,0,1500,1750" iconName "reqTracerRequirement.bmp" iconMaskName "reqTracerRequirement.msk" ) autoResize 1 text (MLText va (VaSet fg "0,0,32768" font "Verdana,8,0" ) xt "450,2150,1450,3150" st " Text " tm "RequirementText" wrapOption 3 visibleHeight 1350 visibleWidth 1100 ) ) defaultPanel (Panel shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "32768,0,0" lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (Text va (VaSet font "Verdana,8,1" ) xt "1000,1000,3800,2000" st "Panel0" blo "1000,1800" tm "PanelText" ) ) ) parentGraphicsRef (HdmGraphicsRef libraryName "" entityName "" viewName "" ) defaultSymbolBody (SymbolBody shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,6000,51000,26000" ) biTextGroup (BiTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text va (VaSet font "Verdana,8,1" ) xt "30500,14400,34100,15400" st "" blo "30500,15200" ) second (Text va (VaSet font "Verdana,8,1" ) xt "30500,15400,33100,16400" st "" blo "30500,16200" ) ) gi *84 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix text (MLText va (VaSet isHidden 1 ) xt "0,12000,0,12000" ) header "Generic Declarations" ) elements [ ] ) portInstanceVis (PortSigDisplay sT 1 sIVOD 1 ) portVis (PortSigDisplay sIVOD 1 ) ) defaultCptPort (CptPort ps "OnEdgeStrategy" shape (Triangle ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet font "Verdana,8,0" ) xt "0,750,1500,1650" st "In0" blo "0,1450" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "Verdana,8,0" ) ) thePort (LogicalPort lang 11 decl (Decl n "In0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) defaultCptPortBuffer (CptPort ps "OnEdgeStrategy" shape (Diamond va (VaSet vasetType 1 fg "65535,65535,65535" bg "0,0,0" ) xt "0,0,750,750" ) tg (CPTG ps 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