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value "13" ) ] ) LanguageMgr "VhdlLangMgr" uid 19,0 optionalChildren [ *75 (SymbolBody uid 8,0 optionalChildren [ *76 (CptPort uid 76,0 ps "OnEdgeStrategy" shape (Triangle uid 77,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "54000,5625,54750,6375" ) tg (CPTG uid 78,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 79,0 va (VaSet font "Verdana,9,0" ) xt "50800,5400,53000,6600" st "A0" ju 2 blo "53000,6400" tm "CptPortNameMgr" ) ) dt (MLText uid 80,0 va (VaSet font "Courier New,8,0" ) xt "2000,-1800,17500,-1000" st "A0 : OUT std_ulogic ;" ) thePort (LogicalPort m 1 decl (Decl n "A0" t "std_ulogic" o 5 suid 1,0 ) ) ) *77 (CptPort uid 86,0 ps "OnEdgeStrategy" shape (Triangle uid 87,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "37250,9625,38000,10375" ) tg (CPTG uid 88,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 89,0 va (VaSet font "Verdana,9,0" ) xt "39000,9400,42400,10600" st "clock" blo "39000,10400" tm "CptPortNameMgr" ) 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