DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
(DmPackageRef
library "gates"
unitName "gates"
)
(DmPackageRef
library "Common"
unitName "CommonLib"
)
]
instances [
(Instance
name "I1"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 1661,0
)
(Instance
name "I2"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 2212,0
)
(Instance
name "I3"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 2262,0
)
(Instance
name "I4"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 2306,0
)
(Instance
name "I5"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 2361,0
)
(Instance
name "I6"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 2473,0
)
(Instance
name "I7"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 2576,0
)
(Instance
name "I8"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 2624,0
)
(Instance
name "I9"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 2998,0
)
(Instance
name "I10"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 3024,0
)
(Instance
name "I11"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 3044,0
)
(Instance
name "I12"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 3223,0
)
(Instance
name "I13"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 3243,0
)
(Instance
name "I14"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 3330,0
)
(Instance
name "I15"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 3356,0
)
(Instance
name "I16"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 4087,0
)
(Instance
name "I17"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 4113,0
)
(Instance
name "I18"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 4139,0
)
(Instance
name "I19"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 4159,0
)
(Instance
name "I20"
duLibraryName "sequential"
duName "DFF"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 4235,0
)
(Instance
name "I21"
duLibraryName "gates"
duName "inverter"
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
mwi 0
uid 4261,0
)
(Instance
name "I0"
duLibraryName "Cursor"
duName "cursorCircuit"
elements [
(GiElement
name "position0"
type "positive"
value "position0"
)
(GiElement
name "position1"
type "positive"
value "position1"
)
(GiElement
name "position2"
type "positive"
value "position2"
)
(GiElement
name "slopeShiftBitNb"
type "positive"
value "slopeShiftBitNb"
)
(GiElement
name "pwmBitNb"
type "positive"
value "pwmBitNb"
)
(GiElement
name "testLineNb"
type "positive"
value "testLineNb"
)
]
mwi 0
uid 5636,0
)
]
embeddedInstances [
(EmbeddedInstance
name "eb1"
number "1"
)
(EmbeddedInstance
name "eb2"
number "2"
)
]
libraryRefs [
"ieee"
"gates"
"Common"
]
)
version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor"
)
(vvPair
variable "d_logical"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\FPGA_cursor"
)
(vvPair
variable "date"
value "11.11.2019"
)
(vvPair
variable "day"
value "Mon"
)
(vvPair
variable "day_long"
value "Monday"
)
(vvPair
variable "dd"
value "11"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "FPGA_cursor"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "silvan.zahno"
)
(vvPair
variable "graphical_source_date"
value "11.11.2019"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE6996"
)
(vvPair
variable "graphical_source_time"
value "08:13:01"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE6996"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "Board"
)
(vvPair
variable "library_downstream_Concatenation"
value "$HDS_PROJECT_DIR/../Board/concat"
)
(vvPair
variable "library_downstream_Generic_1_file"
value "U:\\ELN_cursor\\Synthesis"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Board/work"
)
(vvPair
variable "library_downstream_SpyGlass"
value "U:\\ELN_cursor\\Synthesis"
)
(vvPair
variable "mm"
value "11"
)
(vvPair
variable "module_name"
value "FPGA_cursor"
)
(vvPair
variable "month"
value "Nov"
)
(vvPair
variable "month_long"
value "November"
)
(vvPair
variable "p"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\FPGA_cursor\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$SCRATCH_DIR\\$DESIGN_NAME\\Board\\ise"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "/usr/opt/Modelsim/modeltech/bin"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "08:13:01"
)
(vvPair
variable "unit"
value "FPGA_cursor"
)
(vvPair
variable "user"
value "silvan.zahno"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2019"
)
(vvPair
variable "yy"
value "19"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 198,0
optionalChildren [
*1 (Net
uid 1325,0
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 1,0
)
declText (MLText
uid 1326,0
va (VaSet
isHidden 1
)
xt "-5000,100800,8400,102000"
st "clock         : std_ulogic"
)
)
*2 (Grouping
uid 1487,0
optionalChildren [
*3 (CommentText
uid 1489,0
shape (Rectangle
uid 1490,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "121000,110000,140000,112000"
)
oxt "45000,22000,64000,24000"
text (MLText
uid 1491,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "121200,110400,136600,111600"
st "
<enter project name here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 18600
)
position 1
ignorePrefs 1
)
*4 (CommentText
uid 1492,0
shape (Rectangle
uid 1493,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,110000,115000,112000"
)
oxt "13000,22000,39000,24000"
text (MLText
uid 1494,0
va (VaSet
fg "32768,0,0"
font "Verdana,12,1"
)
xt "95150,110300,108850,111700"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 25600
)
position 1
ignorePrefs 1
)
*5 (CommentText
uid 1495,0
shape (Rectangle
uid 1496,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "94000,116000,115000,118000"
)
oxt "18000,28000,39000,30000"
text (MLText
uid 1497,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "94200,116400,112600,117600"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*6 (CommentText
uid 1498,0
shape (Rectangle
uid 1499,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "115000,110000,121000,112000"
)
oxt "39000,22000,45000,24000"
text (MLText
uid 1500,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "115200,110400,119900,111600"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 5600
)
position 1
ignorePrefs 1
)
*7 (CommentText
uid 1501,0
shape (Rectangle
uid 1502,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "94000,112000,115000,114000"
)
oxt "18000,24000,39000,26000"
text (MLText
uid 1503,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "94200,112400,109400,113600"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*8 (CommentText
uid 1504,0
shape (Rectangle
uid 1505,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,112000,94000,114000"
)
oxt "13000,24000,18000,26000"
text (MLText
uid 1506,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "89200,112400,92600,113600"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
*9 (CommentText
uid 1507,0
shape (Rectangle
uid 1508,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,114000,94000,116000"
)
oxt "13000,26000,18000,28000"
text (MLText
uid 1509,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "89200,114400,92600,115600"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
*10 (CommentText
uid 1510,0
shape (Rectangle
uid 1511,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "115000,112000,140000,118000"
)
oxt "39000,24000,64000,30000"
text (MLText
uid 1512,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "115200,112200,129300,113400"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 5600
visibleWidth 24600
)
ignorePrefs 1
)
*11 (CommentText
uid 1513,0
shape (Rectangle
uid 1514,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "94000,114000,115000,116000"
)
oxt "18000,26000,39000,28000"
text (MLText
uid 1515,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "94200,114400,109700,115600"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*12 (CommentText
uid 1516,0
shape (Rectangle
uid 1517,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,116000,94000,118000"
)
oxt "13000,28000,18000,30000"
text (MLText
uid 1518,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "89200,116400,93500,117600"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
uid 1488,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 1
)
xt "89000,110000,140000,118000"
)
oxt "13000,22000,64000,30000"
)
*13 (PortIoIn
uid 1583,0
shape (CompositeShape
uid 1584,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1585,0
sl 0
ro 270
xt "26000,77625,27500,78375"
)
(Line
uid 1586,0
sl 0
ro 270
xt "27500,78000,28000,78000"
pts [
"27500,78000"
"28000,78000"
]
)
]
)
tg (WTG
uid 1587,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1588,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "21200,77300,25000,78700"
st "clock"
ju 2
blo "25000,78500"
tm "WireNameMgr"
)
s (Text
uid 1589,0
va (VaSet
)
xt "21200,78700,21200,78700"
ju 2
blo "21200,78700"
tm "SignalTypeMgr"
)
)
)
*14 (PortIoIn
uid 1590,0
shape (CompositeShape
uid 1591,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1592,0
sl 0
ro 270
xt "26000,91625,27500,92375"
)
(Line
uid 1593,0
sl 0
ro 270
xt "27500,92000,28000,92000"
pts [
"27500,92000"
"28000,92000"
]
)
]
)
tg (WTG
uid 1594,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1595,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "19300,91300,25000,92700"
st "reset_n"
ju 2
blo "25000,92500"
tm "WireNameMgr"
)
s (Text
uid 1596,0
va (VaSet
)
xt "19300,92700,19300,92700"
ju 2
blo "19300,92700"
tm "SignalTypeMgr"
)
)
)
*15 (Net
uid 1633,0
decl (Decl
n "reset_n"
t "std_ulogic"
o 8
suid 2,0
)
declText (MLText
uid 1634,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,46000,11300,47000"
st "reset_n       : std_ulogic"
)
)
*16 (Net
uid 1635,0
decl (Decl
n "reset"
t "std_ulogic"
o 36
suid 3,0
)
declText (MLText
uid 1636,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,46000,14100,47000"
st "SIGNAL reset         : std_ulogic"
)
)
*17 (SaComponent
uid 1661,0
optionalChildren [
*18 (CptPort
uid 1652,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1653,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "32250,91625,33000,92375"
)
tg (CPTG
uid 1654,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1655,0
va (VaSet
isHidden 1
)
xt "33000,91500,34800,92500"
st "in1"
blo "33000,92300"
)
s (Text
uid 1670,0
va (VaSet
isHidden 1
)
xt "33000,92500,33000,92500"
blo "33000,92500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*19 (CptPort
uid 1656,0
optionalChildren [
*20 (Circle
uid 1660,0
va (VaSet
fg "0,65535,0"
)
xt "38000,91625,38750,92375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 1657,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "38750,91625,39500,92375"
)
tg (CPTG
uid 1658,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1659,0
va (VaSet
isHidden 1
)
xt "35350,91500,37750,92500"
st "out1"
ju 2
blo "37750,92300"
)
s (Text
uid 1671,0
va (VaSet
isHidden 1
)
xt "37750,92500,37750,92500"
ju 2
blo "37750,92500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 1662,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,89000,38000,95000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 1663,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*21 (Text
uid 1664,0
va (VaSet
isHidden 1
)
xt "33910,87700,36910,88700"
st "gates"
blo "33910,88500"
tm "BdLibraryNameMgr"
)
*22 (Text
uid 1665,0
va (VaSet
isHidden 1
)
xt "33910,88700,38710,89700"
st "inverter"
blo "33910,89500"
tm "CptNameMgr"
)
*23 (Text
uid 1666,0
va (VaSet
)
xt "33910,88700,35110,89700"
st "I1"
blo "33910,89500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1667,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1668,0
text (MLText
uid 1669,0
va (VaSet
isHidden 1
)
xt "33000,95400,46400,96600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*24 (Net
uid 2135,0
decl (Decl
n "testMode"
t "std_uLogic"
o 12
suid 4,0
)
declText (MLText
uid 2136,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,46000,11900,47000"
st "testMode      : std_uLogic"
)
)
*25 (PortIoIn
uid 2167,0
shape (CompositeShape
uid 2168,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2169,0
sl 0
ro 270
xt "26000,47625,27500,48375"
)
(Line
uid 2170,0
sl 0
ro 270
xt "27500,48000,28000,48000"
pts [
"27500,48000"
"28000,48000"
]
)
]
)
tg (WTG
uid 2171,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2172,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "21500,47300,25000,48600"
st "go2_n"
ju 2
blo "25000,48300"
tm "WireNameMgr"
)
s (Text
uid 2173,0
va (VaSet
)
xt "21000,48700,21000,48700"
ju 2
blo "21000,48700"
tm "SignalTypeMgr"
)
)
)
*26 (PortIoIn
uid 2174,0
shape (CompositeShape
uid 2175,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2176,0
sl 0
ro 270
xt "26000,59625,27500,60375"
)
(Line
uid 2177,0
sl 0
ro 270
xt "27500,60000,28000,60000"
pts [
"27500,60000"
"28000,60000"
]
)
]
)
tg (WTG
uid 2178,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2179,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "17600,59300,25000,60700"
st "button4_n"
ju 2
blo "25000,60500"
tm "WireNameMgr"
)
s (Text
uid 2180,0
va (VaSet
)
xt "17600,60700,17600,60700"
ju 2
blo "17600,60700"
tm "SignalTypeMgr"
)
)
)
*27 (PortIoIn
uid 2181,0
shape (CompositeShape
uid 2182,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2183,0
sl 0
ro 270
xt "26000,23625,27500,24375"
)
(Line
uid 2184,0
sl 0
ro 270
xt "27500,24000,28000,24000"
pts [
"27500,24000"
"28000,24000"
]
)
]
)
tg (WTG
uid 2185,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2186,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "18300,23300,25000,24700"
st "restart_n"
ju 2
blo "25000,24500"
tm "WireNameMgr"
)
s (Text
uid 2187,0
va (VaSet
)
xt "18300,24700,18300,24700"
ju 2
blo "18300,24700"
tm "SignalTypeMgr"
)
)
)
*28 (PortIoIn
uid 2188,0
shape (CompositeShape
uid 2189,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2190,0
sl 0
ro 270
xt "26000,75625,27500,76375"
)
(Line
uid 2191,0
sl 0
ro 270
xt "27500,76000,28000,76000"
pts [
"27500,76000"
"28000,76000"
]
)
]
)
tg (WTG
uid 2192,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2193,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "18300,75300,25000,76700"
st "testMode"
ju 2
blo "25000,76500"
tm "WireNameMgr"
)
s (Text
uid 2194,0
va (VaSet
)
xt "18300,76700,18300,76700"
ju 2
blo "18300,76700"
tm "SignalTypeMgr"
)
)
)
*29 (SaComponent
uid 2212,0
optionalChildren [
*30 (CptPort
uid 2195,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2196,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,47625,41000,48375"
)
tg (CPTG
uid 2197,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2198,0
va (VaSet
)
xt "42000,47300,42600,48300"
st "D"
blo "42000,48100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*31 (CptPort
uid 2199,0
optionalChildren [
*32 (FFT
pts [
"41750,52000"
"41000,52375"
"41000,51625"
]
uid 2203,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,51625,41750,52375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2200,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,51625,41000,52375"
)
tg (CPTG
uid 2201,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2202,0
va (VaSet
)
xt "42000,51400,43800,52400"
st "CLK"
blo "42000,52200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*33 (CptPort
uid 2204,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2205,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "43625,54000,44375,54750"
)
tg (CPTG
uid 2206,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2207,0
va (VaSet
)
xt "43000,52600,44800,53600"
st "CLR"
blo "43000,53400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*34 (CptPort
uid 2208,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2209,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "47000,47625,47750,48375"
)
tg (CPTG
uid 2210,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2211,0
va (VaSet
)
xt "45400,47300,46000,48300"
st "Q"
ju 2
blo "46000,48100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 2213,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,46000,47000,54000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2214,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*35 (Text
uid 2215,0
va (VaSet
)
xt "44600,53700,51200,54700"
st "sequential"
blo "44600,54500"
tm "BdLibraryNameMgr"
)
*36 (Text
uid 2216,0
va (VaSet
)
xt "44600,54700,46400,55700"
st "DFF"
blo "44600,55500"
tm "CptNameMgr"
)
*37 (Text
uid 2217,0
va (VaSet
)
xt "44600,55700,45800,56700"
st "I2"
blo "44600,56500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2218,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2219,0
text (MLText
uid 2220,0
va (VaSet
isHidden 1
)
xt "48000,53400,61400,54600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*38 (SaComponent
uid 2262,0
optionalChildren [
*39 (CptPort
uid 2271,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2272,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,59625,41000,60375"
)
tg (CPTG
uid 2273,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2274,0
va (VaSet
)
xt "42000,59300,42600,60300"
st "D"
blo "42000,60100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*40 (CptPort
uid 2275,0
optionalChildren [
*41 (FFT
pts [
"41750,64000"
"41000,64375"
"41000,63625"
]
uid 2279,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,63625,41750,64375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2276,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,63625,41000,64375"
)
tg (CPTG
uid 2277,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2278,0
va (VaSet
)
xt "42000,63400,43800,64400"
st "CLK"
blo "42000,64200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*42 (CptPort
uid 2280,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2281,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "43625,66000,44375,66750"
)
tg (CPTG
uid 2282,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2283,0
va (VaSet
)
xt "43000,64600,44800,65600"
st "CLR"
blo "43000,65400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*43 (CptPort
uid 2284,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2285,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "47000,59625,47750,60375"
)
tg (CPTG
uid 2286,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2287,0
va (VaSet
)
xt "45400,59300,46000,60300"
st "Q"
ju 2
blo "46000,60100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 2263,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,58000,47000,66000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2264,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*44 (Text
uid 2265,0
va (VaSet
)
xt "44600,65700,51200,66700"
st "sequential"
blo "44600,66500"
tm "BdLibraryNameMgr"
)
*45 (Text
uid 2266,0
va (VaSet
)
xt "44600,66700,46400,67700"
st "DFF"
blo "44600,67500"
tm "CptNameMgr"
)
*46 (Text
uid 2267,0
va (VaSet
)
xt "44600,67700,45800,68700"
st "I3"
blo "44600,68500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2268,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2269,0
text (MLText
uid 2270,0
va (VaSet
isHidden 1
)
xt "48000,65400,61400,66600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*47 (SaComponent
uid 2306,0
optionalChildren [
*48 (CptPort
uid 2315,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2316,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,23625,41000,24375"
)
tg (CPTG
uid 2317,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2318,0
va (VaSet
)
xt "42000,23300,42600,24300"
st "D"
blo "42000,24100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*49 (CptPort
uid 2319,0
optionalChildren [
*50 (FFT
pts [
"41750,28000"
"41000,28375"
"41000,27625"
]
uid 2323,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,27625,41750,28375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2320,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,27625,41000,28375"
)
tg (CPTG
uid 2321,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2322,0
va (VaSet
)
xt "42000,27400,43800,28400"
st "CLK"
blo "42000,28200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*51 (CptPort
uid 2324,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2325,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "43625,30000,44375,30750"
)
tg (CPTG
uid 2326,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2327,0
va (VaSet
)
xt "43000,28600,44800,29600"
st "CLR"
blo "43000,29400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*52 (CptPort
uid 2328,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2329,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "47000,23625,47750,24375"
)
tg (CPTG
uid 2330,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2331,0
va (VaSet
)
xt "45400,23300,46000,24300"
st "Q"
ju 2
blo "46000,24100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 2307,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,22000,47000,30000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2308,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*53 (Text
uid 2309,0
va (VaSet
)
xt "44600,29700,51200,30700"
st "sequential"
blo "44600,30500"
tm "BdLibraryNameMgr"
)
*54 (Text
uid 2310,0
va (VaSet
)
xt "44600,30700,46400,31700"
st "DFF"
blo "44600,31500"
tm "CptNameMgr"
)
*55 (Text
uid 2311,0
va (VaSet
)
xt "44600,31700,45800,32700"
st "I4"
blo "44600,32500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2312,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2313,0
text (MLText
uid 2314,0
va (VaSet
isHidden 1
)
xt "48000,29400,61400,30600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*56 (PortIoIn
uid 2354,0
shape (CompositeShape
uid 2355,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2356,0
sl 0
ro 90
xt "120500,63625,122000,64375"
)
(Line
uid 2357,0
sl 0
ro 90
xt "120000,64000,120500,64000"
pts [
"120500,64000"
"120000,64000"
]
)
]
)
tg (WTG
uid 2358,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2359,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,63300,130500,64700"
st "sensor2_n"
blo "123000,64500"
tm "WireNameMgr"
)
s (Text
uid 2360,0
va (VaSet
)
xt "123000,64700,123000,64700"
blo "123000,64700"
tm "SignalTypeMgr"
)
)
)
*57 (SaComponent
uid 2361,0
optionalChildren [
*58 (CptPort
uid 2370,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2371,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,63625,103750,64375"
)
tg (CPTG
uid 2372,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2373,0
va (VaSet
)
xt "101400,63300,102000,64300"
st "D"
ju 2
blo "102000,64100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*59 (CptPort
uid 2374,0
optionalChildren [
*60 (FFT
pts [
"102250,68000"
"103000,67625"
"103000,68375"
]
uid 2378,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "102250,67625,103000,68375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2375,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,67625,103750,68375"
)
tg (CPTG
uid 2376,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2377,0
va (VaSet
)
xt "100200,67400,102000,68400"
st "CLK"
ju 2
blo "102000,68200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*61 (CptPort
uid 2379,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2380,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "99625,70000,100375,70750"
)
tg (CPTG
uid 2381,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2382,0
va (VaSet
)
xt "98600,68600,100400,69600"
st "CLR"
blo "98600,69400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*62 (CptPort
uid 2383,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2384,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "96250,63625,97000,64375"
)
tg (CPTG
uid 2385,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2386,0
va (VaSet
)
xt "98000,63300,98600,64300"
st "Q"
blo "98000,64100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 2362,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,62000,103000,70000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2363,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*63 (Text
uid 2364,0
va (VaSet
)
xt "95600,69700,102200,70700"
st "sequential"
blo "95600,70500"
tm "BdLibraryNameMgr"
)
*64 (Text
uid 2365,0
va (VaSet
)
xt "95600,70700,97400,71700"
st "DFF"
blo "95600,71500"
tm "CptNameMgr"
)
*65 (Text
uid 2366,0
va (VaSet
)
xt "95600,71700,96800,72700"
st "I5"
blo "95600,72500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2367,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2368,0
text (MLText
uid 2369,0
va (VaSet
isHidden 1
)
xt "104000,69400,117400,70600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*66 (PortIoOut
uid 2445,0
shape (CompositeShape
uid 2446,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2447,0
sl 0
ro 270
xt "120500,45625,122000,46375"
)
(Line
uid 2448,0
sl 0
ro 270
xt "120000,46000,120500,46000"
pts [
"120000,46000"
"120500,46000"
]
)
]
)
tg (WTG
uid 2449,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2450,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,45300,127200,46700"
st "side1"
blo "123000,46500"
tm "WireNameMgr"
)
s (Text
uid 2451,0
va (VaSet
)
xt "123000,46700,123000,46700"
blo "123000,46700"
tm "SignalTypeMgr"
)
)
)
*67 (PortIoOut
uid 2452,0
shape (CompositeShape
uid 2453,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2454,0
sl 0
ro 270
xt "120500,47625,122000,48375"
)
(Line
uid 2455,0
sl 0
ro 270
xt "120000,48000,120500,48000"
pts [
"120000,48000"
"120500,48000"
]
)
]
)
tg (WTG
uid 2456,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2457,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,47300,127200,48700"
st "side2"
blo "123000,48500"
tm "WireNameMgr"
)
s (Text
uid 2458,0
va (VaSet
)
xt "123000,48700,123000,48700"
blo "123000,48700"
tm "SignalTypeMgr"
)
)
)
*68 (SaComponent
uid 2473,0
optionalChildren [
*69 (CptPort
uid 2482,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2483,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,81625,41000,82375"
)
tg (CPTG
uid 2484,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2485,0
va (VaSet
)
xt "42000,81300,42600,82300"
st "D"
blo "42000,82100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*70 (CptPort
uid 2486,0
optionalChildren [
*71 (FFT
pts [
"41750,86000"
"41000,86375"
"41000,85625"
]
uid 2490,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,85625,41750,86375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2487,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,85625,41000,86375"
)
tg (CPTG
uid 2488,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2489,0
va (VaSet
)
xt "42000,85400,43800,86400"
st "CLK"
blo "42000,86200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*72 (CptPort
uid 2491,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2492,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "43625,88000,44375,88750"
)
tg (CPTG
uid 2493,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2494,0
va (VaSet
)
xt "43000,86600,44800,87600"
st "CLR"
blo "43000,87400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*73 (CptPort
uid 2495,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2496,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "47000,81625,47750,82375"
)
tg (CPTG
uid 2497,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2498,0
va (VaSet
)
xt "45400,81300,46000,82300"
st "Q"
ju 2
blo "46000,82100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 2474,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,80000,47000,88000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2475,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*74 (Text
uid 2476,0
va (VaSet
)
xt "44600,87700,51200,88700"
st "sequential"
blo "44600,88500"
tm "BdLibraryNameMgr"
)
*75 (Text
uid 2477,0
va (VaSet
)
xt "44600,88700,46400,89700"
st "DFF"
blo "44600,89500"
tm "CptNameMgr"
)
*76 (Text
uid 2478,0
va (VaSet
)
xt "44600,89700,45800,90700"
st "I6"
blo "44600,90500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2479,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2480,0
text (MLText
uid 2481,0
va (VaSet
isHidden 1
)
xt "48000,87400,61400,88600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*77 (Net
uid 2521,0
decl (Decl
n "resetSynch"
t "std_ulogic"
o 37
suid 5,0
)
declText (MLText
uid 2522,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,73000,15000,74000"
st "SIGNAL resetSynch    : std_ulogic"
)
)
*78 (HdlText
uid 2543,0
optionalChildren [
*79 (EmbeddedText
uid 2548,0
commentText (CommentText
uid 2549,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 2550,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "29000,81000,35000,83000"
)
autoResize 1
oxt "0,0,18000,5000"
text (MLText
uid 2551,0
va (VaSet
)
xt "29200,81200,37400,82400"
st "
logic1 <= '1';
"
tm "HdlTextMgr"
visibleHeight 2000
visibleWidth 6000
)
)
)
]
shape (Rectangle
uid 2544,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "28000,80000,36000,84000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 2545,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*80 (Text
uid 2546,0
va (VaSet
)
xt "28400,84000,30200,85000"
st "eb1"
blo "28400,84800"
tm "HdlTextNameMgr"
)
*81 (Text
uid 2547,0
va (VaSet
)
xt "28400,85000,29000,86000"
st "1"
blo "28400,85800"
tm "HdlTextNumberMgr"
)
]
)
)
*82 (Net
uid 2574,0
decl (Decl
n "logic1"
t "std_uLogic"
o 35
suid 6,0
)
declText (MLText
uid 2575,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,2300,80000"
st "SIGNAL logic1        : std_uLogic"
)
)
*83 (SaComponent
uid 2576,0
optionalChildren [
*84 (CptPort
uid 2585,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2586,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "49250,81625,50000,82375"
)
tg (CPTG
uid 2587,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2588,0
va (VaSet
isHidden 1
)
xt "50000,81500,51800,82500"
st "in1"
blo "50000,82300"
)
s (Text
uid 2589,0
va (VaSet
isHidden 1
)
xt "50000,82500,50000,82500"
blo "50000,82500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*85 (CptPort
uid 2590,0
optionalChildren [
*86 (Circle
uid 2595,0
va (VaSet
fg "0,65535,0"
)
xt "55000,81625,55750,82375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2591,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "55750,81625,56500,82375"
)
tg (CPTG
uid 2592,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2593,0
va (VaSet
isHidden 1
)
xt "52350,81500,54750,82500"
st "out1"
ju 2
blo "54750,82300"
)
s (Text
uid 2594,0
va (VaSet
isHidden 1
)
xt "54750,82500,54750,82500"
ju 2
blo "54750,82500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 2577,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "50000,79000,55000,85000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2578,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*87 (Text
uid 2579,0
va (VaSet
isHidden 1
)
xt "50910,77700,53910,78700"
st "gates"
blo "50910,78500"
tm "BdLibraryNameMgr"
)
*88 (Text
uid 2580,0
va (VaSet
isHidden 1
)
xt "50910,78700,55710,79700"
st "inverter"
blo "50910,79500"
tm "CptNameMgr"
)
*89 (Text
uid 2581,0
va (VaSet
)
xt "50910,78700,52110,79700"
st "I7"
blo "50910,79500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2582,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2583,0
text (MLText
uid 2584,0
va (VaSet
isHidden 1
)
xt "50000,85400,63400,86600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*90 (Net
uid 2602,0
decl (Decl
n "resetSynch_n"
t "std_ulogic"
o 38
suid 7,0
)
declText (MLText
uid 2603,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,3400,80000"
st "SIGNAL resetSynch_n  : std_ulogic"
)
)
*91 (SaComponent
uid 2624,0
optionalChildren [
*92 (CptPort
uid 2633,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2634,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "114000,63625,114750,64375"
)
tg (CPTG
uid 2635,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2636,0
va (VaSet
isHidden 1
)
xt "178950,63500,180750,64500"
st "in1"
ju 2
blo "180750,64300"
)
s (Text
uid 2637,0
va (VaSet
isHidden 1
)
xt "180750,64500,180750,64500"
ju 2
blo "180750,64500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*93 (CptPort
uid 2638,0
optionalChildren [
*94 (Circle
uid 2643,0
va (VaSet
fg "0,65535,0"
)
xt "108250,63625,109000,64375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 2639,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "107500,63625,108250,64375"
)
tg (CPTG
uid 2640,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2641,0
va (VaSet
isHidden 1
)
xt "170100,63500,172500,64500"
st "out1"
blo "170100,64300"
)
s (Text
uid 2642,0
va (VaSet
isHidden 1
)
xt "170100,64500,170100,64500"
blo "170100,64500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 2625,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,61000,114000,67000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 2626,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*95 (Text
uid 2627,0
va (VaSet
isHidden 1
)
xt "109910,59700,112910,60700"
st "gates"
blo "109910,60500"
tm "BdLibraryNameMgr"
)
*96 (Text
uid 2628,0
va (VaSet
isHidden 1
)
xt "109910,60700,114710,61700"
st "inverter"
blo "109910,61500"
tm "CptNameMgr"
)
*97 (Text
uid 2629,0
va (VaSet
)
xt "109910,60700,111110,61700"
st "I8"
blo "109910,61500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2630,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2631,0
text (MLText
uid 2632,0
va (VaSet
isHidden 1
)
xt "109000,67400,122400,68600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*98 (PortIoOut
uid 2673,0
shape (CompositeShape
uid 2674,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2675,0
sl 0
ro 270
xt "120500,31625,122000,32375"
)
(Line
uid 2676,0
sl 0
ro 270
xt "120000,32000,120500,32000"
pts [
"120000,32000"
"120500,32000"
]
)
]
)
tg (WTG
uid 2677,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2678,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,31300,127000,32700"
st "LED1"
blo "123000,32500"
tm "WireNameMgr"
)
s (Text
uid 2679,0
va (VaSet
font "Verdana,12,0"
)
xt "123000,32700,123000,32700"
blo "123000,32700"
tm "SignalTypeMgr"
)
)
)
*99 (Net
uid 2686,0
decl (Decl
n "LED1"
t "std_uLogic"
o 18
suid 8,0
)
declText (MLText
uid 2687,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,-600,80000"
st "LED1          : std_uLogic"
)
)
*100 (PortIoOut
uid 2688,0
shape (CompositeShape
uid 2689,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2690,0
sl 0
ro 270
xt "120500,33625,122000,34375"
)
(Line
uid 2691,0
sl 0
ro 270
xt "120000,34000,120500,34000"
pts [
"120000,34000"
"120500,34000"
]
)
]
)
tg (WTG
uid 2692,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2693,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,33300,127000,34700"
st "LED2"
blo "123000,34500"
tm "WireNameMgr"
)
s (Text
uid 2694,0
va (VaSet
font "Verdana,12,0"
)
xt "123000,34700,123000,34700"
blo "123000,34700"
tm "SignalTypeMgr"
)
)
)
*101 (Net
uid 2701,0
decl (Decl
n "LED2"
t "std_ulogic"
o 19
suid 9,0
)
declText (MLText
uid 2702,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,-800,80000"
st "LED2          : std_ulogic"
)
)
*102 (Net
uid 2784,0
decl (Decl
n "testOut"
t "std_uLogic_vector"
b "(1 TO testLineNb)"
o 46
suid 10,0
)
declText (MLText
uid 2785,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,13300,80000"
st "SIGNAL testOut       : std_uLogic_vector(1 TO testLineNb)"
)
)
*103 (HdlText
uid 2792,0
optionalChildren [
*104 (EmbeddedText
uid 2797,0
commentText (CommentText
uid 2798,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 2799,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "92000,29000,112000,39000"
)
oxt "0,0,18000,5000"
text (MLText
uid 2800,0
va (VaSet
)
xt "92200,29200,108500,35200"
st "
LED1 <= testOut(16);
--LED2 <= not testOut(16);
LED2 <= testOut(15);

LEDs <= testOut(1 to 8);

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 20000
)
)
)
]
shape (Rectangle
uid 2793,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "92000,28000,112000,40000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 2794,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*105 (Text
uid 2795,0
va (VaSet
)
xt "92400,40000,94200,41000"
st "eb2"
blo "92400,40800"
tm "HdlTextNameMgr"
)
*106 (Text
uid 2796,0
va (VaSet
)
xt "92400,41000,93000,42000"
st "2"
blo "92400,41800"
tm "HdlTextNumberMgr"
)
]
)
)
*107 (SaComponent
uid 2998,0
optionalChildren [
*108 (CptPort
uid 3007,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3008,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "32250,47625,33000,48375"
)
tg (CPTG
uid 3009,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3010,0
va (VaSet
isHidden 1
)
xt "33000,47500,34800,48500"
st "in1"
blo "33000,48300"
)
s (Text
uid 3011,0
va (VaSet
isHidden 1
)
xt "33000,48500,33000,48500"
blo "33000,48500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*109 (CptPort
uid 3012,0
optionalChildren [
*110 (Circle
uid 3017,0
va (VaSet
fg "0,65535,0"
)
xt "38000,47625,38750,48375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 3013,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "38750,47625,39500,48375"
)
tg (CPTG
uid 3014,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3015,0
va (VaSet
isHidden 1
)
xt "35350,47500,37750,48500"
st "out1"
ju 2
blo "37750,48300"
)
s (Text
uid 3016,0
va (VaSet
isHidden 1
)
xt "37750,48500,37750,48500"
ju 2
blo "37750,48500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 2999,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,45000,38000,51000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 3000,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*111 (Text
uid 3001,0
va (VaSet
isHidden 1
)
xt "33910,43700,36910,44700"
st "gates"
blo "33910,44500"
tm "BdLibraryNameMgr"
)
*112 (Text
uid 3002,0
va (VaSet
isHidden 1
)
xt "33910,44700,38710,45700"
st "inverter"
blo "33910,45500"
tm "CptNameMgr"
)
*113 (Text
uid 3003,0
va (VaSet
)
xt "33910,44700,35110,45700"
st "I9"
blo "33910,45500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3004,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3005,0
text (MLText
uid 3006,0
va (VaSet
isHidden 1
)
xt "33000,51400,46400,52600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*114 (SaComponent
uid 3024,0
optionalChildren [
*115 (CptPort
uid 3033,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3034,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "32250,23625,33000,24375"
)
tg (CPTG
uid 3035,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3036,0
va (VaSet
isHidden 1
)
xt "33000,23500,34800,24500"
st "in1"
blo "33000,24300"
)
s (Text
uid 3037,0
va (VaSet
isHidden 1
)
xt "33000,24500,33000,24500"
blo "33000,24500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*116 (CptPort
uid 3038,0
optionalChildren [
*117 (Circle
uid 3043,0
va (VaSet
fg "0,65535,0"
)
xt "38000,23625,38750,24375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 3039,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "38750,23625,39500,24375"
)
tg (CPTG
uid 3040,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3041,0
va (VaSet
isHidden 1
)
xt "35350,23500,37750,24500"
st "out1"
ju 2
blo "37750,24300"
)
s (Text
uid 3042,0
va (VaSet
isHidden 1
)
xt "37750,24500,37750,24500"
ju 2
blo "37750,24500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 3025,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,21000,38000,27000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 3026,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*118 (Text
uid 3027,0
va (VaSet
isHidden 1
)
xt "33910,19700,36910,20700"
st "gates"
blo "33910,20500"
tm "BdLibraryNameMgr"
)
*119 (Text
uid 3028,0
va (VaSet
isHidden 1
)
xt "33910,20700,38710,21700"
st "inverter"
blo "33910,21500"
tm "CptNameMgr"
)
*120 (Text
uid 3029,0
va (VaSet
)
xt "33910,20700,35710,21700"
st "I10"
blo "33910,21500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3030,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3031,0
text (MLText
uid 3032,0
va (VaSet
isHidden 1
)
xt "33000,27400,46400,28600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*121 (SaComponent
uid 3044,0
optionalChildren [
*122 (CptPort
uid 3053,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3054,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "32250,59625,33000,60375"
)
tg (CPTG
uid 3055,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3056,0
va (VaSet
isHidden 1
)
xt "33000,59500,34800,60500"
st "in1"
blo "33000,60300"
)
s (Text
uid 3057,0
va (VaSet
isHidden 1
)
xt "33000,60500,33000,60500"
blo "33000,60500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*123 (CptPort
uid 3058,0
optionalChildren [
*124 (Circle
uid 3063,0
va (VaSet
fg "0,65535,0"
)
xt "38000,59625,38750,60375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 3059,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "38750,59625,39500,60375"
)
tg (CPTG
uid 3060,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3061,0
va (VaSet
isHidden 1
)
xt "35350,59500,37750,60500"
st "out1"
ju 2
blo "37750,60300"
)
s (Text
uid 3062,0
va (VaSet
isHidden 1
)
xt "37750,60500,37750,60500"
ju 2
blo "37750,60500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 3045,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,57000,38000,63000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 3046,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*125 (Text
uid 3047,0
va (VaSet
isHidden 1
)
xt "33910,55700,36910,56700"
st "gates"
blo "33910,56500"
tm "BdLibraryNameMgr"
)
*126 (Text
uid 3048,0
va (VaSet
isHidden 1
)
xt "33910,56700,38710,57700"
st "inverter"
blo "33910,57500"
tm "CptNameMgr"
)
*127 (Text
uid 3049,0
va (VaSet
)
xt "33910,56700,35710,57700"
st "I11"
blo "33910,57500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3050,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3051,0
text (MLText
uid 3052,0
va (VaSet
isHidden 1
)
xt "33000,63400,46400,64600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*128 (PortIoIn
uid 3216,0
shape (CompositeShape
uid 3217,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3218,0
sl 0
ro 270
xt "26000,35625,27500,36375"
)
(Line
uid 3219,0
sl 0
ro 270
xt "27500,36000,28000,36000"
pts [
"27500,36000"
"28000,36000"
]
)
]
)
tg (WTG
uid 3220,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3221,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "20200,35300,25000,36700"
st "go1_n"
ju 2
blo "25000,36500"
tm "WireNameMgr"
)
s (Text
uid 3222,0
va (VaSet
)
xt "20200,36700,20200,36700"
ju 2
blo "20200,36700"
tm "SignalTypeMgr"
)
)
)
*129 (SaComponent
uid 3223,0
optionalChildren [
*130 (CptPort
uid 3232,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3233,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "32250,35625,33000,36375"
)
tg (CPTG
uid 3234,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3235,0
va (VaSet
isHidden 1
)
xt "33000,35500,34800,36500"
st "in1"
blo "33000,36300"
)
s (Text
uid 3236,0
va (VaSet
isHidden 1
)
xt "33000,36500,33000,36500"
blo "33000,36500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*131 (CptPort
uid 3237,0
optionalChildren [
*132 (Circle
uid 3242,0
va (VaSet
fg "0,65535,0"
)
xt "38000,35625,38750,36375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 3238,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "38750,35625,39500,36375"
)
tg (CPTG
uid 3239,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3240,0
va (VaSet
isHidden 1
)
xt "35350,35500,37750,36500"
st "out1"
ju 2
blo "37750,36300"
)
s (Text
uid 3241,0
va (VaSet
isHidden 1
)
xt "37750,36500,37750,36500"
ju 2
blo "37750,36500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 3224,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33000,33000,38000,39000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 3225,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*133 (Text
uid 3226,0
va (VaSet
isHidden 1
)
xt "33910,31700,36910,32700"
st "gates"
blo "33910,32500"
tm "BdLibraryNameMgr"
)
*134 (Text
uid 3227,0
va (VaSet
isHidden 1
)
xt "33910,32700,38710,33700"
st "inverter"
blo "33910,33500"
tm "CptNameMgr"
)
*135 (Text
uid 3228,0
va (VaSet
)
xt "33910,32700,35710,33700"
st "I12"
blo "33910,33500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3229,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3230,0
text (MLText
uid 3231,0
va (VaSet
isHidden 1
)
xt "33000,39400,46400,40600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*136 (SaComponent
uid 3243,0
optionalChildren [
*137 (CptPort
uid 3252,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3253,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,35625,41000,36375"
)
tg (CPTG
uid 3254,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3255,0
va (VaSet
)
xt "42000,35300,42600,36300"
st "D"
blo "42000,36100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*138 (CptPort
uid 3256,0
optionalChildren [
*139 (FFT
pts [
"41750,40000"
"41000,40375"
"41000,39625"
]
uid 3260,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,39625,41750,40375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 3257,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,39625,41000,40375"
)
tg (CPTG
uid 3258,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3259,0
va (VaSet
)
xt "42000,39400,43800,40400"
st "CLK"
blo "42000,40200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*140 (CptPort
uid 3261,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3262,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "43625,42000,44375,42750"
)
tg (CPTG
uid 3263,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3264,0
va (VaSet
)
xt "43000,40600,44800,41600"
st "CLR"
blo "43000,41400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*141 (CptPort
uid 3265,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3266,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "47000,35625,47750,36375"
)
tg (CPTG
uid 3267,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3268,0
va (VaSet
)
xt "45400,35300,46000,36300"
st "Q"
ju 2
blo "46000,36100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 3244,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,34000,47000,42000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 3245,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*142 (Text
uid 3246,0
va (VaSet
)
xt "44600,41700,51200,42700"
st "sequential"
blo "44600,42500"
tm "BdLibraryNameMgr"
)
*143 (Text
uid 3247,0
va (VaSet
)
xt "44600,42700,46400,43700"
st "DFF"
blo "44600,43500"
tm "CptNameMgr"
)
*144 (Text
uid 3248,0
va (VaSet
)
xt "44600,43700,46400,44700"
st "I13"
blo "44600,44500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3249,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3250,0
text (MLText
uid 3251,0
va (VaSet
isHidden 1
)
xt "48000,41400,61400,42600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*145 (Net
uid 3308,0
decl (Decl
n "restart"
t "std_uLogic"
o 39
suid 11,0
)
declText (MLText
uid 3309,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,2300,80000"
st "SIGNAL restart       : std_uLogic"
)
)
*146 (Net
uid 3310,0
decl (Decl
n "restart_n"
t "std_uLogic"
o 9
suid 12,0
)
declText (MLText
uid 3311,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,-500,80000"
st "restart_n     : std_uLogic"
)
)
*147 (Net
uid 3312,0
decl (Decl
n "restartSynch"
t "std_uLogic"
o 40
suid 13,0
)
declText (MLText
uid 3313,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,3200,80000"
st "SIGNAL restartSynch  : std_uLogic"
)
)
*148 (Net
uid 3324,0
decl (Decl
n "sensor1_n"
t "std_uLogic"
o 10
suid 14,0
)
declText (MLText
uid 3325,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,0,80000"
st "sensor1_n     : std_uLogic"
)
)
*149 (Net
uid 3326,0
decl (Decl
n "sensor1"
t "std_uLogic"
o 41
suid 15,0
)
declText (MLText
uid 3327,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,2800,80000"
st "SIGNAL sensor1       : std_uLogic"
)
)
*150 (Net
uid 3328,0
decl (Decl
n "sensor1Synch"
t "std_uLogic"
o 42
suid 16,0
)
declText (MLText
uid 3329,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,3700,80000"
st "SIGNAL sensor1Synch  : std_uLogic"
)
)
*151 (SaComponent
uid 3330,0
optionalChildren [
*152 (CptPort
uid 3339,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3340,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,51625,103750,52375"
)
tg (CPTG
uid 3341,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3342,0
va (VaSet
)
xt "101400,51300,102000,52300"
st "D"
ju 2
blo "102000,52100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*153 (CptPort
uid 3343,0
optionalChildren [
*154 (FFT
pts [
"102250,56000"
"103000,55625"
"103000,56375"
]
uid 3347,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "102250,55625,103000,56375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 3344,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,55625,103750,56375"
)
tg (CPTG
uid 3345,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3346,0
va (VaSet
)
xt "100200,55400,102000,56400"
st "CLK"
ju 2
blo "102000,56200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*155 (CptPort
uid 3348,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3349,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "99625,58000,100375,58750"
)
tg (CPTG
uid 3350,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3351,0
va (VaSet
)
xt "98600,56600,100400,57600"
st "CLR"
blo "98600,57400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*156 (CptPort
uid 3352,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3353,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "96250,51625,97000,52375"
)
tg (CPTG
uid 3354,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3355,0
va (VaSet
)
xt "98000,51300,98600,52300"
st "Q"
blo "98000,52100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 3331,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,50000,103000,58000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 3332,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*157 (Text
uid 3333,0
va (VaSet
)
xt "95600,57700,102200,58700"
st "sequential"
blo "95600,58500"
tm "BdLibraryNameMgr"
)
*158 (Text
uid 3334,0
va (VaSet
)
xt "95600,58700,97400,59700"
st "DFF"
blo "95600,59500"
tm "CptNameMgr"
)
*159 (Text
uid 3335,0
va (VaSet
)
xt "95600,59700,97400,60700"
st "I14"
blo "95600,60500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3336,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3337,0
text (MLText
uid 3338,0
va (VaSet
isHidden 1
)
xt "104000,57400,117400,58600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*160 (SaComponent
uid 3356,0
optionalChildren [
*161 (CptPort
uid 3365,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3366,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "114000,51625,114750,52375"
)
tg (CPTG
uid 3367,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3368,0
va (VaSet
isHidden 1
)
xt "178950,51500,180750,52500"
st "in1"
ju 2
blo "180750,52300"
)
s (Text
uid 3369,0
va (VaSet
isHidden 1
)
xt "180750,52500,180750,52500"
ju 2
blo "180750,52500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*162 (CptPort
uid 3370,0
optionalChildren [
*163 (Circle
uid 3375,0
va (VaSet
fg "0,65535,0"
)
xt "108250,51625,109000,52375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 3371,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "107500,51625,108250,52375"
)
tg (CPTG
uid 3372,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3373,0
va (VaSet
isHidden 1
)
xt "170100,51500,172500,52500"
st "out1"
blo "170100,52300"
)
s (Text
uid 3374,0
va (VaSet
isHidden 1
)
xt "170100,52500,170100,52500"
blo "170100,52500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 3357,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,49000,114000,55000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 3358,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*164 (Text
uid 3359,0
va (VaSet
isHidden 1
)
xt "109910,47700,112910,48700"
st "gates"
blo "109910,48500"
tm "BdLibraryNameMgr"
)
*165 (Text
uid 3360,0
va (VaSet
isHidden 1
)
xt "109910,48700,114710,49700"
st "inverter"
blo "109910,49500"
tm "CptNameMgr"
)
*166 (Text
uid 3361,0
va (VaSet
)
xt "109910,48700,111710,49700"
st "I15"
blo "109910,49500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3362,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3363,0
text (MLText
uid 3364,0
va (VaSet
isHidden 1
)
xt "109000,55400,122400,56600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*167 (PortIoIn
uid 3376,0
shape (CompositeShape
uid 3377,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3378,0
sl 0
ro 90
xt "120500,51625,122000,52375"
)
(Line
uid 3379,0
sl 0
ro 90
xt "120000,52000,120500,52000"
pts [
"120500,52000"
"120000,52000"
]
)
]
)
tg (WTG
uid 3380,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3381,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,51300,130500,52700"
st "sensor1_n"
blo "123000,52500"
tm "WireNameMgr"
)
s (Text
uid 3382,0
va (VaSet
)
xt "123000,52700,123000,52700"
blo "123000,52700"
tm "SignalTypeMgr"
)
)
)
*168 (Net
uid 3410,0
decl (Decl
n "sensor2Synch"
t "std_uLogic"
o 44
suid 17,0
)
declText (MLText
uid 3411,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,3700,80000"
st "SIGNAL sensor2Synch  : std_uLogic"
)
)
*169 (Net
uid 3412,0
decl (Decl
n "sensor2"
t "std_uLogic"
o 43
suid 18,0
)
declText (MLText
uid 3413,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,2800,80000"
st "SIGNAL sensor2       : std_uLogic"
)
)
*170 (Net
uid 3414,0
decl (Decl
n "sensor2_n"
t "std_uLogic"
o 11
suid 19,0
)
declText (MLText
uid 3415,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,0,80000"
st "sensor2_n     : std_uLogic"
)
)
*171 (Net
uid 3527,0
decl (Decl
n "motorOn"
t "std_uLogic"
o 21
suid 20,0
)
declText (MLText
uid 3528,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,0,80000"
st "motorOn       : std_uLogic"
)
)
*172 (PortIoOut
uid 3535,0
shape (CompositeShape
uid 3536,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3537,0
sl 0
ro 270
xt "120500,43625,122000,44375"
)
(Line
uid 3538,0
sl 0
ro 270
xt "120000,44000,120500,44000"
pts [
"120000,44000"
"120500,44000"
]
)
]
)
tg (WTG
uid 3539,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3540,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,43300,129300,44700"
st "motorOn"
blo "123000,44500"
tm "WireNameMgr"
)
s (Text
uid 3541,0
va (VaSet
font "Verdana,12,0"
)
xt "123000,44700,123000,44700"
blo "123000,44700"
tm "SignalTypeMgr"
)
)
)
*173 (PortIoOut
uid 3736,0
shape (CompositeShape
uid 3737,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3738,0
sl 0
ro 270
xt "120500,35625,122000,36375"
)
(Line
uid 3739,0
sl 0
ro 270
xt "120000,36000,120500,36000"
pts [
"120000,36000"
"120500,36000"
]
)
]
)
tg (WTG
uid 3740,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3741,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,35300,134100,36700"
st "LEDs : (1 TO 8)"
blo "123000,36500"
tm "WireNameMgr"
)
s (Text
uid 3742,0
va (VaSet
font "Verdana,12,0"
)
xt "123000,36700,123000,36700"
blo "123000,36700"
tm "SignalTypeMgr"
)
)
)
*174 (Net
uid 3920,0
decl (Decl
n "side1"
t "std_uLogic"
o 22
suid 22,0
)
declText (MLText
uid 3921,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,-800,80000"
st "side1         : std_uLogic"
)
)
*175 (Net
uid 3922,0
decl (Decl
n "side2"
t "std_uLogic"
o 23
suid 23,0
)
declText (MLText
uid 3923,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-12000,79000,-800,80000"
st "side2         : std_uLogic"
)
)
*176 (Net
uid 4071,0
decl (Decl
n "setPoint"
t "std_uLogic"
o 45
suid 25,0
)
declText (MLText
uid 4072,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-38400,79600"
st "SIGNAL setPoint      : std_uLogic"
)
)
*177 (Net
uid 4075,0
decl (Decl
n "go2Synch"
t "std_uLogic"
o 34
suid 27,0
)
declText (MLText
uid 4076,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-37700,79600"
st "SIGNAL go2Synch      : std_uLogic"
)
)
*178 (Net
uid 4077,0
decl (Decl
n "go2"
t "std_uLogic"
o 33
suid 28,0
)
declText (MLText
uid 4078,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-38600,79600"
st "SIGNAL go2           : std_uLogic"
)
)
*179 (Net
uid 4079,0
decl (Decl
n "go2_n"
t "std_uLogic"
o 7
suid 29,0
)
declText (MLText
uid 4080,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-41400,79600"
st "go2_n         : std_uLogic"
)
)
*180 (Net
uid 4081,0
decl (Decl
n "go1Synch"
t "std_uLogic"
o 32
suid 30,0
)
declText (MLText
uid 4082,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-37700,79600"
st "SIGNAL go1Synch      : std_uLogic"
)
)
*181 (Net
uid 4083,0
decl (Decl
n "go1"
t "std_uLogic"
o 31
suid 31,0
)
declText (MLText
uid 4084,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-38600,79600"
st "SIGNAL go1           : std_uLogic"
)
)
*182 (Net
uid 4085,0
decl (Decl
n "go1_n"
t "std_uLogic"
o 6
suid 32,0
)
declText (MLText
uid 4086,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-53000,78600,-41400,79600"
st "go1_n         : std_uLogic"
)
)
*183 (SaComponent
uid 4087,0
optionalChildren [
*184 (CptPort
uid 4096,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4097,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,87625,103750,88375"
)
tg (CPTG
uid 4098,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4099,0
va (VaSet
)
xt "101400,87300,102000,88300"
st "D"
ju 2
blo "102000,88100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*185 (CptPort
uid 4100,0
optionalChildren [
*186 (FFT
pts [
"102250,92000"
"103000,91625"
"103000,92375"
]
uid 4104,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "102250,91625,103000,92375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 4101,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,91625,103750,92375"
)
tg (CPTG
uid 4102,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4103,0
va (VaSet
)
xt "100200,91400,102000,92400"
st "CLK"
ju 2
blo "102000,92200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*187 (CptPort
uid 4105,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4106,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "99625,94000,100375,94750"
)
tg (CPTG
uid 4107,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4108,0
va (VaSet
)
xt "98600,92600,100400,93600"
st "CLR"
blo "98600,93400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*188 (CptPort
uid 4109,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4110,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "96250,87625,97000,88375"
)
tg (CPTG
uid 4111,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4112,0
va (VaSet
)
xt "98000,87300,98600,88300"
st "Q"
blo "98000,88100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 4088,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,86000,103000,94000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 4089,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*189 (Text
uid 4090,0
va (VaSet
)
xt "95600,93700,102200,94700"
st "sequential"
blo "95600,94500"
tm "BdLibraryNameMgr"
)
*190 (Text
uid 4091,0
va (VaSet
)
xt "95600,94700,97400,95700"
st "DFF"
blo "95600,95500"
tm "CptNameMgr"
)
*191 (Text
uid 4092,0
va (VaSet
)
xt "95600,95700,97400,96700"
st "I16"
blo "95600,96500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4093,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4094,0
text (MLText
uid 4095,0
va (VaSet
isHidden 1
)
xt "104000,93400,117400,94600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*192 (SaComponent
uid 4113,0
optionalChildren [
*193 (CptPort
uid 4122,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4123,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,75625,103750,76375"
)
tg (CPTG
uid 4124,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4125,0
va (VaSet
)
xt "101400,75300,102000,76300"
st "D"
ju 2
blo "102000,76100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*194 (CptPort
uid 4126,0
optionalChildren [
*195 (FFT
pts [
"102250,80000"
"103000,79625"
"103000,80375"
]
uid 4130,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "102250,79625,103000,80375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 4127,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,79625,103750,80375"
)
tg (CPTG
uid 4128,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4129,0
va (VaSet
)
xt "100200,79400,102000,80400"
st "CLK"
ju 2
blo "102000,80200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*196 (CptPort
uid 4131,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4132,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "99625,82000,100375,82750"
)
tg (CPTG
uid 4133,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4134,0
va (VaSet
)
xt "98600,80600,100400,81600"
st "CLR"
blo "98600,81400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*197 (CptPort
uid 4135,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4136,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "96250,75625,97000,76375"
)
tg (CPTG
uid 4137,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4138,0
va (VaSet
)
xt "98000,75300,98600,76300"
st "Q"
blo "98000,76100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 4114,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,74000,103000,82000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 4115,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*198 (Text
uid 4116,0
va (VaSet
)
xt "95600,81700,102200,82700"
st "sequential"
blo "95600,82500"
tm "BdLibraryNameMgr"
)
*199 (Text
uid 4117,0
va (VaSet
)
xt "95600,82700,97400,83700"
st "DFF"
blo "95600,83500"
tm "CptNameMgr"
)
*200 (Text
uid 4118,0
va (VaSet
)
xt "95600,83700,97400,84700"
st "I17"
blo "95600,84500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4119,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4120,0
text (MLText
uid 4121,0
va (VaSet
isHidden 1
)
xt "104000,81400,117400,82600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*201 (SaComponent
uid 4139,0
optionalChildren [
*202 (CptPort
uid 4148,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4149,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "114000,87625,114750,88375"
)
tg (CPTG
uid 4150,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4151,0
va (VaSet
isHidden 1
)
xt "178950,87500,180750,88500"
st "in1"
ju 2
blo "180750,88300"
)
s (Text
uid 4152,0
va (VaSet
isHidden 1
)
xt "180750,88500,180750,88500"
ju 2
blo "180750,88500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*203 (CptPort
uid 4153,0
optionalChildren [
*204 (Circle
uid 4158,0
va (VaSet
fg "0,65535,0"
)
xt "108250,87625,109000,88375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 4154,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "107500,87625,108250,88375"
)
tg (CPTG
uid 4155,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4156,0
va (VaSet
isHidden 1
)
xt "170100,87500,172500,88500"
st "out1"
blo "170100,88300"
)
s (Text
uid 4157,0
va (VaSet
isHidden 1
)
xt "170100,88500,170100,88500"
blo "170100,88500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 4140,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,85000,114000,91000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 4141,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*205 (Text
uid 4142,0
va (VaSet
isHidden 1
)
xt "109910,83700,112910,84700"
st "gates"
blo "109910,84500"
tm "BdLibraryNameMgr"
)
*206 (Text
uid 4143,0
va (VaSet
isHidden 1
)
xt "109910,84700,114710,85700"
st "inverter"
blo "109910,85500"
tm "CptNameMgr"
)
*207 (Text
uid 4144,0
va (VaSet
)
xt "109910,84700,111710,85700"
st "I18"
blo "109910,85500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4145,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4146,0
text (MLText
uid 4147,0
va (VaSet
isHidden 1
)
xt "109000,91400,122400,92600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*208 (SaComponent
uid 4159,0
optionalChildren [
*209 (CptPort
uid 4168,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4169,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "114000,75625,114750,76375"
)
tg (CPTG
uid 4170,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4171,0
va (VaSet
isHidden 1
)
xt "178950,75500,180750,76500"
st "in1"
ju 2
blo "180750,76300"
)
s (Text
uid 4172,0
va (VaSet
isHidden 1
)
xt "180750,76500,180750,76500"
ju 2
blo "180750,76500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*210 (CptPort
uid 4173,0
optionalChildren [
*211 (Circle
uid 4178,0
va (VaSet
fg "0,65535,0"
)
xt "108250,75625,109000,76375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 4174,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "107500,75625,108250,76375"
)
tg (CPTG
uid 4175,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4176,0
va (VaSet
isHidden 1
)
xt "170100,75500,172500,76500"
st "out1"
blo "170100,76300"
)
s (Text
uid 4177,0
va (VaSet
isHidden 1
)
xt "170100,76500,170100,76500"
blo "170100,76500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 4160,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,73000,114000,79000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 4161,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*212 (Text
uid 4162,0
va (VaSet
isHidden 1
)
xt "109910,71700,112910,72700"
st "gates"
blo "109910,72500"
tm "BdLibraryNameMgr"
)
*213 (Text
uid 4163,0
va (VaSet
isHidden 1
)
xt "109910,72700,114710,73700"
st "inverter"
blo "109910,73500"
tm "CptNameMgr"
)
*214 (Text
uid 4164,0
va (VaSet
)
xt "109910,72700,111710,73700"
st "I19"
blo "109910,73500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4165,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4166,0
text (MLText
uid 4167,0
va (VaSet
isHidden 1
)
xt "109000,79400,122400,80600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*215 (PortIoIn
uid 4179,0
shape (CompositeShape
uid 4180,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4181,0
sl 0
ro 90
xt "120500,87625,122000,88375"
)
(Line
uid 4182,0
sl 0
ro 90
xt "120000,88000,120500,88000"
pts [
"120500,88000"
"120000,88000"
]
)
]
)
tg (WTG
uid 4183,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4184,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,87300,132100,88700"
st "encoderB_n"
blo "123000,88500"
tm "WireNameMgr"
)
s (Text
uid 4185,0
va (VaSet
)
xt "123000,88700,123000,88700"
blo "123000,88700"
tm "SignalTypeMgr"
)
)
)
*216 (PortIoIn
uid 4186,0
shape (CompositeShape
uid 4187,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4188,0
sl 0
ro 90
xt "120500,75625,122000,76375"
)
(Line
uid 4189,0
sl 0
ro 90
xt "120000,76000,120500,76000"
pts [
"120500,76000"
"120000,76000"
]
)
]
)
tg (WTG
uid 4190,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4191,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,75300,132100,76700"
st "encoderA_n"
blo "123000,76500"
tm "WireNameMgr"
)
s (Text
uid 4192,0
va (VaSet
)
xt "123000,76700,123000,76700"
blo "123000,76700"
tm "SignalTypeMgr"
)
)
)
*217 (SaComponent
uid 4235,0
optionalChildren [
*218 (CptPort
uid 4244,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4245,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,99625,103750,100375"
)
tg (CPTG
uid 4246,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4247,0
va (VaSet
)
xt "101400,99300,102000,100300"
st "D"
ju 2
blo "102000,100100"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*219 (CptPort
uid 4248,0
optionalChildren [
*220 (FFT
pts [
"102250,104000"
"103000,103625"
"103000,104375"
]
uid 4252,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "102250,103625,103000,104375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 4249,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103000,103625,103750,104375"
)
tg (CPTG
uid 4250,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4251,0
va (VaSet
)
xt "100200,103400,102000,104400"
st "CLK"
ju 2
blo "102000,104200"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*221 (CptPort
uid 4253,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4254,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "99625,106000,100375,106750"
)
tg (CPTG
uid 4255,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4256,0
va (VaSet
)
xt "98600,104600,100400,105600"
st "CLR"
blo "98600,105400"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*222 (CptPort
uid 4257,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4258,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "96250,99625,97000,100375"
)
tg (CPTG
uid 4259,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4260,0
va (VaSet
)
xt "98000,99300,98600,100300"
st "Q"
blo "98000,100100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 4236,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,98000,103000,106000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 4237,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*223 (Text
uid 4238,0
va (VaSet
)
xt "95600,105700,102200,106700"
st "sequential"
blo "95600,106500"
tm "BdLibraryNameMgr"
)
*224 (Text
uid 4239,0
va (VaSet
)
xt "95600,106700,97400,107700"
st "DFF"
blo "95600,107500"
tm "CptNameMgr"
)
*225 (Text
uid 4240,0
va (VaSet
)
xt "95600,107700,97400,108700"
st "I20"
blo "95600,108500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4241,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4242,0
text (MLText
uid 4243,0
va (VaSet
isHidden 1
)
xt "104000,105400,117400,106600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*226 (SaComponent
uid 4261,0
optionalChildren [
*227 (CptPort
uid 4270,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4271,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "114000,99625,114750,100375"
)
tg (CPTG
uid 4272,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4273,0
va (VaSet
isHidden 1
)
xt "178950,99500,180750,100500"
st "in1"
ju 2
blo "180750,100300"
)
s (Text
uid 4274,0
va (VaSet
isHidden 1
)
xt "180750,100500,180750,100500"
ju 2
blo "180750,100500"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*228 (CptPort
uid 4275,0
optionalChildren [
*229 (Circle
uid 4280,0
va (VaSet
fg "0,65535,0"
)
xt "108250,99625,109000,100375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 4276,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "107500,99625,108250,100375"
)
tg (CPTG
uid 4277,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4278,0
va (VaSet
isHidden 1
)
xt "170100,99500,172500,100500"
st "out1"
blo "170100,100300"
)
s (Text
uid 4279,0
va (VaSet
isHidden 1
)
xt "170100,100500,170100,100500"
blo "170100,100500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 4262,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109000,97000,114000,103000"
)
showPorts 0
oxt "-850,0,8850,10000"
ttg (MlTextGroup
uid 4263,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*230 (Text
uid 4264,0
va (VaSet
isHidden 1
)
xt "109910,95700,112910,96700"
st "gates"
blo "109910,96500"
tm "BdLibraryNameMgr"
)
*231 (Text
uid 4265,0
va (VaSet
isHidden 1
)
xt "109910,96700,114710,97700"
st "inverter"
blo "109910,97500"
tm "CptNameMgr"
)
*232 (Text
uid 4266,0
va (VaSet
)
xt "109910,96700,111710,97700"
st "I21"
blo "109910,97500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4267,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4268,0
text (MLText
uid 4269,0
va (VaSet
isHidden 1
)
xt "109000,103400,122400,104600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*233 (PortIoIn
uid 4281,0
shape (CompositeShape
uid 4282,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4283,0
sl 0
ro 90
xt "120500,99625,122000,100375"
)
(Line
uid 4284,0
sl 0
ro 90
xt "120000,100000,120500,100000"
pts [
"120500,100000"
"120000,100000"
]
)
]
)
tg (WTG
uid 4285,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4286,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "123000,99300,131800,100700"
st "encoderI_n"
blo "123000,100500"
tm "WireNameMgr"
)
s (Text
uid 4287,0
va (VaSet
)
xt "123000,100700,123000,100700"
blo "123000,100700"
tm "SignalTypeMgr"
)
)
)
*234 (Net
uid 4335,0
decl (Decl
n "encoderASynch"
t "std_uLogic"
o 26
suid 33,0
)
declText (MLText
uid 4336,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,74600,16000,75600"
st "SIGNAL encoderASynch : std_uLogic"
)
)
*235 (Net
uid 4341,0
decl (Decl
n "encoderBSynch"
t "std_uLogic"
o 28
suid 34,0
)
declText (MLText
uid 4342,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,74600,16000,75600"
st "SIGNAL encoderBSynch : std_uLogic"
)
)
*236 (Net
uid 4343,0
decl (Decl
n "encoderB"
t "std_uLogic"
o 27
suid 35,0
)
declText (MLText
uid 4344,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,74600,15100,75600"
st "SIGNAL encoderB      : std_uLogic"
)
)
*237 (Net
uid 4347,0
decl (Decl
n "encoderISynch"
t "std_uLogic"
o 30
suid 36,0
)
declText (MLText
uid 4348,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,74600,15800,75600"
st "SIGNAL encoderISynch : std_uLogic"
)
)
*238 (Net
uid 4349,0
decl (Decl
n "encoderI"
t "std_uLogic"
o 29
suid 37,0
)
declText (MLText
uid 4350,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,74600,14900,75600"
st "SIGNAL encoderI      : std_uLogic"
)
)
*239 (Net
uid 4351,0
decl (Decl
n "encoderI_n"
t "std_uLogic"
o 5
suid 38,0
)
declText (MLText
uid 4352,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,74600,12100,75600"
st "encoderI_n    : std_uLogic"
)
)
*240 (Net
uid 4353,0
decl (Decl
n "encoderA"
t "std_uLogic"
o 25
suid 39,0
)
declText (MLText
uid 4354,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,74600,15100,75600"
st "SIGNAL encoderA      : std_uLogic"
)
)
*241 (Net
uid 4355,0
decl (Decl
n "encoderA_n"
t "std_uLogic"
o 3
suid 40,0
)
declText (MLText
uid 4356,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,74600,12300,75600"
st "encoderA_n    : std_uLogic"
)
)
*242 (Net
uid 4357,0
decl (Decl
n "encoderB_n"
t "std_uLogic"
o 4
suid 41,0
)
declText (MLText
uid 4358,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,74600,12300,75600"
st "encoderB_n    : std_uLogic"
)
)
*243 (Net
uid 4689,0
decl (Decl
n "button4_n"
t "std_uLogic"
o 1
suid 42,0
)
declText (MLText
uid 4690,0
va (VaSet
isHidden 1
)
xt "0,74600,14900,75800"
st "button4_n     : std_uLogic"
)
)
*244 (Net
uid 4691,0
decl (Decl
n "button4Synch"
t "std_uLogic"
o 24
suid 43,0
)
declText (MLText
uid 4692,0
va (VaSet
isHidden 1
)
xt "0,74600,20400,75800"
st "SIGNAL button4Synch  : std_uLogic"
)
)
*245 (PortIoOut
uid 4922,0
shape (CompositeShape
uid 4923,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4924,0
sl 0
ro 90
xt "58000,63625,59500,64375"
)
(Line
uid 4925,0
sl 0
ro 90
xt "59500,64000,60000,64000"
pts [
"60000,64000"
"59500,64000"
]
)
]
)
tg (WTG
uid 4926,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4927,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "48800,63300,57000,64700"
st "LCD_CS1_n"
ju 2
blo "57000,64500"
tm "WireNameMgr"
)
s (Text
uid 4928,0
va (VaSet
font "Verdana,12,0"
)
xt "48800,64700,48800,64700"
ju 2
blo "48800,64700"
tm "SignalTypeMgr"
)
)
)
*246 (PortIoOut
uid 4929,0
shape (CompositeShape
uid 4930,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4931,0
sl 0
ro 90
xt "58000,65625,59500,66375"
)
(Line
uid 4932,0
sl 0
ro 90
xt "59500,66000,60000,66000"
pts [
"60000,66000"
"59500,66000"
]
)
]
)
tg (WTG
uid 4933,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4934,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "50500,65300,57000,66700"
st "LCD_SCL"
ju 2
blo "57000,66500"
tm "WireNameMgr"
)
s (Text
uid 4935,0
va (VaSet
font "Verdana,12,0"
)
xt "50500,66700,50500,66700"
ju 2
blo "50500,66700"
tm "SignalTypeMgr"
)
)
)
*247 (PortIoOut
uid 4936,0
shape (CompositeShape
uid 4937,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4938,0
sl 0
ro 90
xt "58000,67625,59500,68375"
)
(Line
uid 4939,0
sl 0
ro 90
xt "59500,68000,60000,68000"
pts [
"60000,68000"
"59500,68000"
]
)
]
)
tg (WTG
uid 4940,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4941,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "51600,67300,57000,68700"
st "LCD_SI"
ju 2
blo "57000,68500"
tm "WireNameMgr"
)
s (Text
uid 4942,0
va (VaSet
font "Verdana,12,0"
)
xt "51600,68700,51600,68700"
ju 2
blo "51600,68700"
tm "SignalTypeMgr"
)
)
)
*248 (PortIoOut
uid 4943,0
shape (CompositeShape
uid 4944,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4945,0
sl 0
ro 90
xt "58000,69625,59500,70375"
)
(Line
uid 4946,0
sl 0
ro 90
xt "59500,70000,60000,70000"
pts [
"60000,70000"
"59500,70000"
]
)
]
)
tg (WTG
uid 4947,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4948,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "51300,69300,57000,70700"
st "LCD_A0"
ju 2
blo "57000,70500"
tm "WireNameMgr"
)
s (Text
uid 4949,0
va (VaSet
font "Verdana,12,0"
)
xt "51300,70700,51300,70700"
ju 2
blo "51300,70700"
tm "SignalTypeMgr"
)
)
)
*249 (PortIoOut
uid 4950,0
shape (CompositeShape
uid 4951,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4952,0
sl 0
ro 90
xt "58000,71625,59500,72375"
)
(Line
uid 4953,0
sl 0
ro 90
xt "59500,72000,60000,72000"
pts [
"60000,72000"
"59500,72000"
]
)
]
)
tg (WTG
uid 4954,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4955,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "49000,71300,57000,72700"
st "LCD_RST_n"
ju 2
blo "57000,72500"
tm "WireNameMgr"
)
s (Text
uid 4956,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,72700,49000,72700"
ju 2
blo "49000,72700"
tm "SignalTypeMgr"
)
)
)
*250 (Net
uid 5038,0
decl (Decl
n "LCD_CS1_n"
t "std_ulogic"
o 14
suid 49,0
)
declText (MLText
uid 5039,0
va (VaSet
isHidden 1
)
xt "0,74600,15700,75800"
st "LCD_CS1_n     : std_ulogic"
)
)
*251 (Net
uid 5040,0
decl (Decl
n "LCD_SCL"
t "std_ulogic"
o 16
suid 50,0
)
declText (MLText
uid 5041,0
va (VaSet
isHidden 1
)
xt "0,74600,15000,75800"
st "LCD_SCL       : std_ulogic"
)
)
*252 (Net
uid 5042,0
decl (Decl
n "LCD_SI"
t "std_ulogic"
o 17
suid 51,0
)
declText (MLText
uid 5043,0
va (VaSet
isHidden 1
)
xt "0,74600,14400,75800"
st "LCD_SI        : std_ulogic"
)
)
*253 (Net
uid 5044,0
decl (Decl
n "LCD_A0"
t "std_ulogic"
o 13
suid 52,0
)
declText (MLText
uid 5045,0
va (VaSet
isHidden 1
)
xt "0,74600,14700,75800"
st "LCD_A0        : std_ulogic"
)
)
*254 (Net
uid 5046,0
decl (Decl
n "LCD_RST_n"
t "std_ulogic"
o 15
suid 53,0
)
declText (MLText
uid 5047,0
va (VaSet
isHidden 1
)
xt "0,74600,15600,75800"
st "LCD_RST_n     : std_ulogic"
)
)
*255 (SaComponent
uid 5636,0
optionalChildren [
*256 (CptPort
uid 5531,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5532,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,77625,68000,78375"
)
tg (CPTG
uid 5533,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5534,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,77300,72500,78600"
st "clock"
blo "69000,78300"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 1,0
)
)
)
*257 (CptPort
uid 5536,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5537,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,79625,68000,80375"
)
tg (CPTG
uid 5538,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5539,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,79300,72500,80600"
st "reset"
blo "69000,80300"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 8
suid 2,0
)
)
)
*258 (CptPort
uid 5541,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5542,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,55625,84750,56375"
)
tg (CPTG
uid 5543,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5544,0
va (VaSet
font "Verdana,12,0"
)
xt "79500,55400,83000,56700"
st "side1"
ju 2
blo "83000,56400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "side1"
t "std_uLogic"
o 19
suid 3,0
)
)
)
*259 (CptPort
uid 5546,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5547,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,53625,68000,54375"
)
tg (CPTG
uid 5548,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5549,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,53300,73900,54600"
st "restart"
blo "69000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "restart"
t "std_uLogic"
o 9
suid 4,0
)
)
)
*260 (CptPort
uid 5551,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5552,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,57625,68000,58375"
)
tg (CPTG
uid 5553,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5554,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,57300,71100,58600"
st "go2"
blo "69000,58300"
)
)
thePort (LogicalPort
decl (Decl
n "go2"
t "std_uLogic"
o 7
suid 5,0
)
)
)
*261 (CptPort
uid 5556,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5557,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,61625,84750,62375"
)
tg (CPTG
uid 5558,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5559,0
va (VaSet
font "Verdana,12,0"
)
xt "78100,61400,83000,62700"
st "sensor1"
ju 2
blo "83000,62400"
)
)
thePort (LogicalPort
decl (Decl
n "sensor1"
t "std_uLogic"
o 10
suid 6,0
)
)
)
*262 (CptPort
uid 5561,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5562,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,75625,68000,76375"
)
tg (CPTG
uid 5563,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5564,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,75300,74600,76600"
st "testMode"
blo "69000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "testMode"
t "std_uLogic"
o 12
suid 7,0
)
)
)
*263 (CptPort
uid 5566,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5567,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "75625,49250,76375,50000"
)
tg (CPTG
uid 5568,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5569,0
va (VaSet
font "Verdana,12,0"
)
xt "73700,51000,78600,52300"
st "testOut"
ju 2
blo "78600,52000"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_uLogic_vector"
b "(1 TO testLineNb)"
o 21
suid 8,0
)
)
)
*264 (CptPort
uid 5571,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5572,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,55625,68000,56375"
)
tg (CPTG
uid 5573,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5574,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,55300,71100,56600"
st "go1"
blo "69000,56300"
)
)
thePort (LogicalPort
decl (Decl
n "go1"
t "std_uLogic"
o 6
suid 9,0
)
)
)
*265 (CptPort
uid 5576,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5577,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,57625,84750,58375"
)
tg (CPTG
uid 5578,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5579,0
va (VaSet
font "Verdana,12,0"
)
xt "79500,57400,83000,58700"
st "side2"
ju 2
blo "83000,58400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "side2"
t "std_uLogic"
o 20
suid 10,0
)
)
)
*266 (CptPort
uid 5581,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5582,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,63625,84750,64375"
)
tg (CPTG
uid 5583,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5584,0
va (VaSet
font "Verdana,12,0"
)
xt "78100,63300,83000,64600"
st "sensor2"
ju 2
blo "83000,64300"
)
)
thePort (LogicalPort
decl (Decl
n "sensor2"
t "std_uLogic"
o 11
suid 11,0
)
)
)
*267 (CptPort
uid 5586,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5587,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,53625,84750,54375"
)
tg (CPTG
uid 5588,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5589,0
va (VaSet
font "Verdana,12,0"
)
xt "78100,53400,83000,54700"
st "motorOn"
ju 2
blo "83000,54400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "motorOn"
t "std_uLogic"
o 18
suid 12,0
)
)
)
*268 (CptPort
uid 5591,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5592,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,67625,84750,68375"
)
tg (CPTG
uid 5593,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5594,0
va (VaSet
font "Verdana,12,0"
)
xt "77400,67400,83000,68700"
st "encoderA"
ju 2
blo "83000,68400"
)
)
thePort (LogicalPort
decl (Decl
n "encoderA"
t "std_uLogic"
o 3
suid 13,0
)
)
)
*269 (CptPort
uid 5596,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5597,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,69625,84750,70375"
)
tg (CPTG
uid 5598,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5599,0
va (VaSet
font "Verdana,12,0"
)
xt "77400,69400,83000,70700"
st "encoderB"
ju 2
blo "83000,70400"
)
)
thePort (LogicalPort
decl (Decl
n "encoderB"
t "std_uLogic"
o 4
suid 14,0
)
)
)
*270 (CptPort
uid 5601,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5602,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,71625,84750,72375"
)
tg (CPTG
uid 5603,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5604,0
va (VaSet
font "Verdana,12,0"
)
xt "77400,71400,83000,72700"
st "encoderI"
ju 2
blo "83000,72400"
)
)
thePort (LogicalPort
decl (Decl
n "encoderI"
t "std_uLogic"
o 5
suid 15,0
)
)
)
*271 (CptPort
uid 5606,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5607,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,59625,68000,60375"
)
tg (CPTG
uid 5608,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5609,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,59300,73900,60600"
st "button4"
blo "69000,60300"
)
)
thePort (LogicalPort
decl (Decl
n "button4"
t "std_uLogic"
o 1
suid 16,0
)
)
)
*272 (CptPort
uid 5611,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5612,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,63625,68000,64375"
)
tg (CPTG
uid 5613,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5614,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,63300,72500,64600"
st "CS1_n"
blo "69000,64300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CS1_n"
t "std_ulogic"
o 14
suid 2017,0
)
)
)
*273 (CptPort
uid 5616,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5617,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,65625,68000,66375"
)
tg (CPTG
uid 5618,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5619,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,65300,71100,66600"
st "SCL"
blo "69000,66300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SCL"
t "std_ulogic"
o 16
suid 2018,0
)
)
)
*274 (CptPort
uid 5621,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5622,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,67625,68000,68375"
)
tg (CPTG
uid 5623,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5624,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,67300,70400,68600"
st "SI"
blo "69000,68300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SI"
t "std_ulogic"
o 17
suid 2019,0
)
)
)
*275 (CptPort
uid 5626,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5627,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,69625,68000,70375"
)
tg (CPTG
uid 5628,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5629,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,69300,70400,70600"
st "A0"
blo "69000,70300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "A0"
t "std_ulogic"
o 13
suid 2020,0
)
)
)
*276 (CptPort
uid 5631,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5632,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,71625,68000,72375"
)
tg (CPTG
uid 5633,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5634,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,71300,72500,72600"
st "RST_n"
blo "69000,72300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RST_n"
t "std_ulogic"
o 15
suid 2021,0
)
)
)
]
shape (Rectangle
uid 5637,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "68000,50000,84000,82000"
)
oxt "40000,2000,56000,34000"
ttg (MlTextGroup
uid 5638,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*277 (Text
uid 5639,0
va (VaSet
font "Verdana,8,1"
)
xt "68100,81700,71100,82600"
st "Cursor"
blo "68100,82400"
tm "BdLibraryNameMgr"
)
*278 (Text
uid 5640,0
va (VaSet
font "Verdana,8,1"
)
xt "68100,82700,75100,83600"
st "cursorCircuit"
blo "68100,83400"
tm "CptNameMgr"
)
*279 (Text
uid 5641,0
va (VaSet
font "Verdana,8,1"
)
xt "68100,83700,69100,84600"
st "I0"
blo "68100,84400"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5642,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5643,0
text (MLText
uid 5644,0
va (VaSet
font "Verdana,8,0"
)
xt "68000,85200,90000,91200"
st "position0       = position0          ( positive )  
position1       = position1          ( positive )  
position2       = position2          ( positive )  
slopeShiftBitNb = slopeShiftBitNb    ( positive )  
pwmBitNb        = pwmBitNb           ( positive )  
testLineNb      = testLineNb         ( positive )  "
)
header ""
)
elements [
(GiElement
name "position0"
type "positive"
value "position0"
)
(GiElement
name "position1"
type "positive"
value "position1"
)
(GiElement
name "position2"
type "positive"
value "position2"
)
(GiElement
name "slopeShiftBitNb"
type "positive"
value "slopeShiftBitNb"
)
(GiElement
name "pwmBitNb"
type "positive"
value "pwmBitNb"
)
(GiElement
name "testLineNb"
type "positive"
value "testLineNb"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*280 (Net
uid 5716,0
decl (Decl
n "LEDs"
t "std_uLogic_vector"
b "(1 TO 8)"
o 20
suid 55,0
)
declText (MLText
uid 5717,0
va (VaSet
isHidden 1
)
xt "0,0,22900,1200"
st "LEDs          : std_uLogic_vector(1 TO 8)"
)
)
*281 (Wire
uid 1317,0
shape (OrthoPolyLine
uid 1318,0
va (VaSet
vasetType 3
)
xt "28000,92000,33000,92000"
pts [
"33000,92000"
"28000,92000"
]
)
start &18
end &14
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1321,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1322,0
va (VaSet
font "Verdana,12,0"
)
xt "27000,90600,32700,92000"
st "reset_n"
blo "27000,91800"
tm "WireNameMgr"
)
)
on &15
)
*282 (Wire
uid 1327,0
shape (OrthoPolyLine
uid 1328,0
va (VaSet
vasetType 3
)
xt "28000,78000,67250,78000"
pts [
"67250,78000"
"28000,78000"
]
)
start &256
end &13
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1331,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1332,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,76600,31800,78000"
st "clock"
blo "28000,77800"
tm "WireNameMgr"
)
)
on &1
)
*283 (Wire
uid 1625,0
shape (OrthoPolyLine
uid 1626,0
va (VaSet
vasetType 3
)
xt "55750,80000,67250,82000"
pts [
"67250,80000"
"59000,80000"
"59000,82000"
"55750,82000"
]
)
start &257
end &85
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1629,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1630,0
va (VaSet
font "Verdana,12,0"
)
xt "60000,78600,68600,80000"
st "resetSynch"
blo "60000,79800"
tm "WireNameMgr"
)
)
on &77
)
*284 (Wire
uid 2137,0
shape (OrthoPolyLine
uid 2138,0
va (VaSet
vasetType 3
)
xt "28000,76000,67250,76000"
pts [
"67250,76000"
"28000,76000"
]
)
start &262
end &28
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2141,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2142,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,74600,34700,76000"
st "testMode"
blo "28000,75800"
tm "WireNameMgr"
)
)
on &24
)
*285 (Wire
uid 2145,0
shape (OrthoPolyLine
uid 2146,0
va (VaSet
vasetType 3
)
xt "28000,24000,33000,24000"
pts [
"33000,24000"
"28000,24000"
]
)
start &115
end &27
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2149,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2150,0
va (VaSet
font "Verdana,12,0"
)
xt "27000,22600,33700,24000"
st "restart_n"
blo "27000,23800"
tm "WireNameMgr"
)
)
on &146
)
*286 (Wire
uid 2153,0
shape (OrthoPolyLine
uid 2154,0
va (VaSet
vasetType 3
)
xt "28000,60000,33000,60000"
pts [
"33000,60000"
"28000,60000"
]
)
start &122
end &26
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2157,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2158,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,58600,35400,60000"
st "button4_n"
blo "28000,59800"
tm "WireNameMgr"
)
)
on &243
)
*287 (Wire
uid 2161,0
shape (OrthoPolyLine
uid 2162,0
va (VaSet
vasetType 3
)
xt "28000,48000,33000,48000"
pts [
"33000,48000"
"28000,48000"
]
)
start &108
end &25
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2165,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2166,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,46600,31500,47900"
st "go2_n"
blo "28000,47600"
tm "WireNameMgr"
)
)
on &179
)
*288 (Wire
uid 2238,0
shape (OrthoPolyLine
uid 2239,0
va (VaSet
vasetType 3
)
xt "36000,52000,41000,52000"
pts [
"41000,52000"
"36000,52000"
]
)
start &31
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2244,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2245,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,50600,39800,52000"
st "clock"
blo "36000,51800"
tm "WireNameMgr"
)
)
on &1
)
*289 (Wire
uid 2246,0
shape (OrthoPolyLine
uid 2247,0
va (VaSet
vasetType 3
)
xt "36000,54000,44000,56000"
pts [
"44000,54000"
"44000,56000"
"36000,56000"
]
)
start &33
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2252,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2253,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,54600,44600,56000"
st "resetSynch"
blo "36000,55800"
tm "WireNameMgr"
)
)
on &77
)
*290 (Wire
uid 2256,0
shape (OrthoPolyLine
uid 2257,0
va (VaSet
vasetType 3
)
xt "47000,48000,67250,58000"
pts [
"47000,48000"
"58000,48000"
"58000,58000"
"67250,58000"
]
)
start &34
end &260
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2258,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2259,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,46600,55900,48000"
st "go2Synch"
blo "49000,47800"
tm "WireNameMgr"
)
)
on &177
)
*291 (Wire
uid 2288,0
shape (OrthoPolyLine
uid 2289,0
va (VaSet
vasetType 3
)
xt "36000,66000,44000,68000"
pts [
"44000,66000"
"44000,68000"
"36000,68000"
]
)
start &42
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2292,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2293,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,66600,44600,68000"
st "resetSynch"
blo "36000,67800"
tm "WireNameMgr"
)
)
on &77
)
*292 (Wire
uid 2294,0
shape (OrthoPolyLine
uid 2295,0
va (VaSet
vasetType 3
)
xt "36000,64000,41000,64000"
pts [
"41000,64000"
"36000,64000"
]
)
start &40
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2298,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2299,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,62600,39800,64000"
st "clock"
blo "36000,63800"
tm "WireNameMgr"
)
)
on &1
)
*293 (Wire
uid 2302,0
shape (OrthoPolyLine
uid 2303,0
va (VaSet
vasetType 3
)
xt "47000,60000,67250,60000"
pts [
"47000,60000"
"67250,60000"
]
)
start &43
end &271
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2304,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2305,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,58600,59300,60000"
st "button4Synch"
blo "49000,59800"
tm "WireNameMgr"
)
)
on &244
)
*294 (Wire
uid 2332,0
shape (OrthoPolyLine
uid 2333,0
va (VaSet
vasetType 3
)
xt "36000,30000,44000,32000"
pts [
"44000,30000"
"44000,32000"
"36000,32000"
]
)
start &51
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2336,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2337,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,30600,44600,32000"
st "resetSynch"
blo "36000,31800"
tm "WireNameMgr"
)
)
on &77
)
*295 (Wire
uid 2338,0
shape (OrthoPolyLine
uid 2339,0
va (VaSet
vasetType 3
)
xt "36000,28000,41000,28000"
pts [
"41000,28000"
"36000,28000"
]
)
start &49
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2342,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2343,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,26600,39800,28000"
st "clock"
blo "36000,27800"
tm "WireNameMgr"
)
)
on &1
)
*296 (Wire
uid 2346,0
shape (OrthoPolyLine
uid 2347,0
va (VaSet
vasetType 3
)
xt "47000,24000,67250,54000"
pts [
"47000,24000"
"62000,24000"
"62000,54000"
"67250,54000"
]
)
start &52
end &259
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2348,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2349,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,22600,58600,24000"
st "restartSynch"
blo "49000,23800"
tm "WireNameMgr"
)
)
on &147
)
*297 (Wire
uid 2387,0
shape (OrthoPolyLine
uid 2388,0
va (VaSet
vasetType 3
)
xt "103000,64000,108250,64000"
pts [
"103000,64000"
"108250,64000"
]
)
start &58
end &93
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2389,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2390,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,62600,108900,64000"
st "sensor2"
blo "103000,63800"
tm "WireNameMgr"
)
)
on &169
)
*298 (Wire
uid 2391,0
shape (OrthoPolyLine
uid 2392,0
va (VaSet
vasetType 3
)
xt "103000,68000,108000,68000"
pts [
"103000,68000"
"108000,68000"
]
)
start &59
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2395,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2396,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,66600,108800,68000"
st "clock"
blo "105000,67800"
tm "WireNameMgr"
)
)
on &1
)
*299 (Wire
uid 2397,0
shape (OrthoPolyLine
uid 2398,0
va (VaSet
vasetType 3
)
xt "100000,70000,108000,72000"
pts [
"100000,70000"
"100000,72000"
"108000,72000"
]
)
start &61
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2401,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2402,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,70600,109600,72000"
st "resetSynch"
blo "101000,71800"
tm "WireNameMgr"
)
)
on &77
)
*300 (Wire
uid 2407,0
shape (OrthoPolyLine
uid 2408,0
va (VaSet
vasetType 3
)
xt "84750,64000,97000,64000"
pts [
"84750,64000"
"97000,64000"
]
)
start &266
end &62
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2409,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2410,0
va (VaSet
font "Verdana,12,0"
)
xt "85000,62600,95400,64000"
st "sensor2Synch"
blo "85000,63800"
tm "WireNameMgr"
)
)
on &168
)
*301 (Wire
uid 2431,0
shape (OrthoPolyLine
uid 2432,0
va (VaSet
vasetType 3
)
xt "84750,48000,120000,58000"
pts [
"84750,58000"
"92000,58000"
"92000,48000"
"120000,48000"
]
)
start &265
end &67
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2435,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2436,0
va (VaSet
font "Verdana,12,0"
)
xt "114000,46600,118200,48000"
st "side2"
blo "114000,47800"
tm "WireNameMgr"
)
)
on &175
)
*302 (Wire
uid 2439,0
shape (OrthoPolyLine
uid 2440,0
va (VaSet
vasetType 3
)
xt "84750,46000,120000,56000"
pts [
"84750,56000"
"90000,56000"
"90000,46000"
"120000,46000"
]
)
start &258
end &66
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2443,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2444,0
va (VaSet
font "Verdana,12,0"
)
xt "116000,44600,120200,46000"
st "side1"
blo "116000,45800"
tm "WireNameMgr"
)
)
on &174
)
*303 (Wire
uid 2499,0
shape (OrthoPolyLine
uid 2500,0
va (VaSet
vasetType 3
)
xt "36000,86000,41000,86000"
pts [
"41000,86000"
"36000,86000"
]
)
start &70
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2503,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2504,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,84600,39800,86000"
st "clock"
blo "36000,85800"
tm "WireNameMgr"
)
)
on &1
)
*304 (Wire
uid 2507,0
shape (OrthoPolyLine
uid 2508,0
va (VaSet
vasetType 3
)
xt "36000,82000,41000,82000"
pts [
"41000,82000"
"36000,82000"
]
)
start &69
end &78
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2511,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2512,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,80600,40400,82000"
st "logic1"
blo "36000,81800"
tm "WireNameMgr"
)
)
on &82
)
*305 (Wire
uid 2517,0
shape (OrthoPolyLine
uid 2518,0
va (VaSet
vasetType 3
)
xt "38750,88000,44000,92000"
pts [
"38750,92000"
"44000,92000"
"44000,88000"
]
)
start &19
end &72
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2519,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2520,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,90600,44100,92000"
st "reset"
blo "40000,91800"
tm "WireNameMgr"
)
)
on &16
)
*306 (Wire
uid 2598,0
shape (OrthoPolyLine
uid 2599,0
va (VaSet
vasetType 3
)
xt "47000,82000,50000,82000"
pts [
"47000,82000"
"50000,82000"
]
)
start &73
end &84
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 2600,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2601,0
va (VaSet
font "Verdana,12,0"
)
xt "44000,80600,54200,82000"
st "resetSynch_n"
blo "44000,81800"
tm "WireNameMgr"
)
)
on &90
)
*307 (Wire
uid 2646,0
shape (OrthoPolyLine
uid 2647,0
va (VaSet
vasetType 3
)
xt "114000,64000,120000,64000"
pts [
"120000,64000"
"114000,64000"
]
)
start &56
end &92
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 2648,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2649,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,62600,122500,64000"
st "sensor2_n"
blo "115000,63800"
tm "WireNameMgr"
)
s (Text
uid 2672,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,64000,115000,64000"
blo "115000,64000"
tm "SignalTypeMgr"
)
)
on &170
)
*308 (Wire
uid 2680,0
shape (OrthoPolyLine
uid 2681,0
va (VaSet
vasetType 3
)
xt "112000,32000,120000,32000"
pts [
"112000,32000"
"120000,32000"
]
)
start &103
end &98
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2684,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2685,0
va (VaSet
font "Verdana,12,0"
)
xt "117000,30600,121000,32000"
st "LED1"
blo "117000,31800"
tm "WireNameMgr"
)
)
on &99
)
*309 (Wire
uid 2695,0
shape (OrthoPolyLine
uid 2696,0
va (VaSet
vasetType 3
)
xt "112000,34000,120000,34000"
pts [
"112000,34000"
"120000,34000"
]
)
start &103
end &100
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2699,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2700,0
va (VaSet
font "Verdana,12,0"
)
xt "117000,32600,121000,34000"
st "LED2"
blo "117000,33800"
tm "WireNameMgr"
)
)
on &101
)
*310 (Wire
uid 2786,0
shape (OrthoPolyLine
uid 2787,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "76000,34000,92000,49250"
pts [
"76000,49250"
"76000,34000"
"92000,34000"
]
)
start &263
end &103
sat 32
eat 1
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2790,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2791,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "74600,42450,76000,48050"
st "testOut"
blo "75800,48050"
tm "WireNameMgr"
)
)
on &102
)
*311 (Wire
uid 3020,0
shape (OrthoPolyLine
uid 3021,0
va (VaSet
vasetType 3
)
xt "38750,48000,41000,48000"
pts [
"38750,48000"
"41000,48000"
]
)
start &109
end &30
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3022,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3023,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,46600,43950,48000"
st "go2"
blo "40750,47800"
tm "WireNameMgr"
)
s (Text
uid 3108,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,48000,40750,48000"
blo "40750,48000"
tm "SignalTypeMgr"
)
)
on &178
)
*312 (Wire
uid 3066,0
shape (OrthoPolyLine
uid 3067,0
va (VaSet
vasetType 3
)
xt "38750,60000,41000,60000"
pts [
"38750,60000"
"41000,60000"
]
)
start &123
end &39
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3068,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3069,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,58600,46750,60000"
st "setPoint"
blo "40750,59800"
tm "WireNameMgr"
)
s (Text
uid 3109,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,60000,40750,60000"
blo "40750,60000"
tm "SignalTypeMgr"
)
)
on &176
)
*313 (Wire
uid 3072,0
shape (OrthoPolyLine
uid 3073,0
va (VaSet
vasetType 3
)
xt "38750,24000,41000,24000"
pts [
"38750,24000"
"41000,24000"
]
)
start &116
end &48
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3074,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3075,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,22600,45850,24000"
st "restart"
blo "40750,23800"
tm "WireNameMgr"
)
s (Text
uid 3110,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,24000,40750,24000"
blo "40750,24000"
tm "SignalTypeMgr"
)
)
on &145
)
*314 (Wire
uid 3269,0
shape (OrthoPolyLine
uid 3270,0
va (VaSet
vasetType 3
)
xt "47000,36000,67250,56000"
pts [
"47000,36000"
"60000,36000"
"60000,56000"
"67250,56000"
]
)
start &141
end &264
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3273,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3274,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,34600,55900,36000"
st "go1Synch"
blo "49000,35800"
tm "WireNameMgr"
)
)
on &180
)
*315 (Wire
uid 3275,0
shape (OrthoPolyLine
uid 3276,0
va (VaSet
vasetType 3
)
xt "36000,42000,44000,44000"
pts [
"44000,42000"
"44000,44000"
"36000,44000"
]
)
start &140
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3279,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3280,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,42600,44600,44000"
st "resetSynch"
blo "36000,43800"
tm "WireNameMgr"
)
)
on &77
)
*316 (Wire
uid 3281,0
shape (OrthoPolyLine
uid 3282,0
va (VaSet
vasetType 3
)
xt "28000,36000,33000,36000"
pts [
"33000,36000"
"28000,36000"
]
)
start &130
end &128
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3283,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3284,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,34600,32800,36000"
st "go1_n"
blo "28000,35800"
tm "WireNameMgr"
)
)
on &182
)
*317 (Wire
uid 3285,0
shape (OrthoPolyLine
uid 3286,0
va (VaSet
vasetType 3
)
xt "36000,40000,41000,40000"
pts [
"41000,40000"
"36000,40000"
]
)
start &138
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3289,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3290,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,38600,39800,40000"
st "clock"
blo "36000,39800"
tm "WireNameMgr"
)
)
on &1
)
*318 (Wire
uid 3291,0
shape (OrthoPolyLine
uid 3292,0
va (VaSet
vasetType 3
)
xt "38750,36000,41000,36000"
pts [
"38750,36000"
"41000,36000"
]
)
start &131
end &137
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3293,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3294,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,34600,43950,36000"
st "go1"
blo "40750,35800"
tm "WireNameMgr"
)
s (Text
uid 3295,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "40750,36000,40750,36000"
blo "40750,36000"
tm "SignalTypeMgr"
)
)
on &181
)
*319 (Wire
uid 3383,0
shape (OrthoPolyLine
uid 3384,0
va (VaSet
vasetType 3
)
xt "103000,56000,108000,56000"
pts [
"103000,56000"
"108000,56000"
]
)
start &153
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3387,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3388,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,54600,108800,56000"
st "clock"
blo "105000,55800"
tm "WireNameMgr"
)
)
on &1
)
*320 (Wire
uid 3389,0
shape (OrthoPolyLine
uid 3390,0
va (VaSet
vasetType 3
)
xt "84750,52000,97000,62000"
pts [
"84750,62000"
"94000,62000"
"94000,52000"
"97000,52000"
]
)
start &261
end &156
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3393,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3394,0
va (VaSet
font "Verdana,12,0"
)
xt "85000,60600,95400,62000"
st "sensor1Synch"
blo "85000,61800"
tm "WireNameMgr"
)
)
on &150
)
*321 (Wire
uid 3395,0
shape (OrthoPolyLine
uid 3396,0
va (VaSet
vasetType 3
)
xt "100000,58000,108000,60000"
pts [
"100000,58000"
"100000,60000"
"108000,60000"
]
)
start &155
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3399,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3400,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,58600,109600,60000"
st "resetSynch"
blo "101000,59800"
tm "WireNameMgr"
)
)
on &77
)
*322 (Wire
uid 3401,0
shape (OrthoPolyLine
uid 3402,0
va (VaSet
vasetType 3
)
xt "103000,52000,108250,52000"
pts [
"103000,52000"
"108250,52000"
]
)
start &152
end &162
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3403,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3404,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,50600,108900,52000"
st "sensor1"
blo "103000,51800"
tm "WireNameMgr"
)
)
on &149
)
*323 (Wire
uid 3405,0
shape (OrthoPolyLine
uid 3406,0
va (VaSet
vasetType 3
)
xt "114000,52000,120000,52000"
pts [
"120000,52000"
"114000,52000"
]
)
start &167
end &161
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3407,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3408,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,50600,122500,52000"
st "sensor1_n"
blo "115000,51800"
tm "WireNameMgr"
)
s (Text
uid 3409,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,52000,115000,52000"
blo "115000,52000"
tm "SignalTypeMgr"
)
)
on &148
)
*324 (Wire
uid 3529,0
shape (OrthoPolyLine
uid 3530,0
va (VaSet
vasetType 3
)
xt "84750,44000,120000,54000"
pts [
"84750,54000"
"88000,54000"
"88000,44000"
"120000,44000"
]
)
start &267
end &172
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 3533,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3534,0
va (VaSet
font "Verdana,12,0"
)
xt "114000,42600,120300,44000"
st "motorOn"
blo "114000,43800"
tm "WireNameMgr"
)
)
on &171
)
*325 (Wire
uid 3743,0
shape (OrthoPolyLine
uid 3744,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "112000,36000,120000,36000"
pts [
"112000,36000"
"120000,36000"
]
)
start &103
end &173
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3747,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3748,0
va (VaSet
font "Verdana,12,0"
)
xt "117000,34600,120900,36000"
st "LEDs"
blo "117000,35800"
tm "WireNameMgr"
)
)
on &280
)
*326 (Wire
uid 4193,0
shape (OrthoPolyLine
uid 4194,0
va (VaSet
vasetType 3
)
xt "103000,92000,108000,92000"
pts [
"103000,92000"
"108000,92000"
]
)
start &185
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4197,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4198,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,90600,108800,92000"
st "clock"
blo "105000,91800"
tm "WireNameMgr"
)
)
on &1
)
*327 (Wire
uid 4199,0
shape (OrthoPolyLine
uid 4200,0
va (VaSet
vasetType 3
)
xt "103000,88000,108250,88000"
pts [
"103000,88000"
"108250,88000"
]
)
start &184
end &203
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4201,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4202,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,86600,109700,88000"
st "encoderB"
blo "103000,87800"
tm "WireNameMgr"
)
)
on &236
)
*328 (Wire
uid 4203,0
shape (OrthoPolyLine
uid 4204,0
va (VaSet
vasetType 3
)
xt "100000,94000,108000,96000"
pts [
"100000,94000"
"100000,96000"
"108000,96000"
]
)
start &187
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4207,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4208,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,94600,109600,96000"
st "resetSynch"
blo "101000,95800"
tm "WireNameMgr"
)
)
on &77
)
*329 (Wire
uid 4209,0
shape (OrthoPolyLine
uid 4210,0
va (VaSet
vasetType 3
)
xt "114000,88000,120000,88000"
pts [
"120000,88000"
"114000,88000"
]
)
start &215
end &202
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4211,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4212,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,86600,124100,88000"
st "encoderB_n"
blo "115000,87800"
tm "WireNameMgr"
)
s (Text
uid 4213,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,88000,115000,88000"
blo "115000,88000"
tm "SignalTypeMgr"
)
)
on &242
)
*330 (Wire
uid 4214,0
shape (OrthoPolyLine
uid 4215,0
va (VaSet
vasetType 3
)
xt "100000,82000,108000,84000"
pts [
"100000,82000"
"100000,84000"
"108000,84000"
]
)
start &196
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4218,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4219,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,82600,109600,84000"
st "resetSynch"
blo "101000,83800"
tm "WireNameMgr"
)
)
on &77
)
*331 (Wire
uid 4220,0
shape (OrthoPolyLine
uid 4221,0
va (VaSet
vasetType 3
)
xt "103000,80000,108000,80000"
pts [
"103000,80000"
"108000,80000"
]
)
start &194
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4224,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4225,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,78600,108800,80000"
st "clock"
blo "105000,79800"
tm "WireNameMgr"
)
)
on &1
)
*332 (Wire
uid 4226,0
shape (OrthoPolyLine
uid 4227,0
va (VaSet
vasetType 3
)
xt "114000,76000,120000,76000"
pts [
"120000,76000"
"114000,76000"
]
)
start &216
end &209
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4228,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4229,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,74600,124100,76000"
st "encoderA_n"
blo "115000,75800"
tm "WireNameMgr"
)
s (Text
uid 4230,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,76000,115000,76000"
blo "115000,76000"
tm "SignalTypeMgr"
)
)
on &241
)
*333 (Wire
uid 4231,0
shape (OrthoPolyLine
uid 4232,0
va (VaSet
vasetType 3
)
xt "103000,76000,108250,76000"
pts [
"103000,76000"
"108250,76000"
]
)
start &193
end &210
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4233,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4234,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,74600,109700,76000"
st "encoderA"
blo "103000,75800"
tm "WireNameMgr"
)
)
on &240
)
*334 (Wire
uid 4288,0
shape (OrthoPolyLine
uid 4289,0
va (VaSet
vasetType 3
)
xt "103000,104000,108000,104000"
pts [
"103000,104000"
"108000,104000"
]
)
start &219
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4292,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4293,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,102600,108800,104000"
st "clock"
blo "105000,103800"
tm "WireNameMgr"
)
)
on &1
)
*335 (Wire
uid 4294,0
shape (OrthoPolyLine
uid 4295,0
va (VaSet
vasetType 3
)
xt "114000,100000,120000,100000"
pts [
"120000,100000"
"114000,100000"
]
)
start &233
end &227
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4296,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4297,0
va (VaSet
font "Verdana,12,0"
)
xt "115000,98600,123800,100000"
st "encoderI_n"
blo "115000,99800"
tm "WireNameMgr"
)
s (Text
uid 4298,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "115000,100000,115000,100000"
blo "115000,100000"
tm "SignalTypeMgr"
)
)
on &239
)
*336 (Wire
uid 4299,0
shape (OrthoPolyLine
uid 4300,0
va (VaSet
vasetType 3
)
xt "100000,106000,108000,108000"
pts [
"100000,106000"
"100000,108000"
"108000,108000"
]
)
start &221
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4303,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4304,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,106600,109600,108000"
st "resetSynch"
blo "101000,107800"
tm "WireNameMgr"
)
)
on &77
)
*337 (Wire
uid 4305,0
shape (OrthoPolyLine
uid 4306,0
va (VaSet
vasetType 3
)
xt "103000,100000,108250,100000"
pts [
"103000,100000"
"108250,100000"
]
)
start &218
end &228
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4307,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4308,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,98600,109400,100000"
st "encoderI"
blo "103000,99800"
tm "WireNameMgr"
)
)
on &238
)
*338 (Wire
uid 4319,0
shape (OrthoPolyLine
uid 4320,0
va (VaSet
vasetType 3
)
xt "84750,68000,97000,76000"
pts [
"84750,68000"
"94000,68000"
"94000,76000"
"97000,76000"
]
)
start &268
end &197
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4321,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4322,0
va (VaSet
font "Verdana,12,0"
)
xt "86750,66600,97950,68000"
st "encoderASynch"
blo "86750,67800"
tm "WireNameMgr"
)
)
on &234
)
*339 (Wire
uid 4325,0
shape (OrthoPolyLine
uid 4326,0
va (VaSet
vasetType 3
)
xt "84750,70000,97000,88000"
pts [
"84750,70000"
"92000,70000"
"92000,88000"
"97000,88000"
]
)
start &269
end &188
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4327,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4328,0
va (VaSet
font "Verdana,12,0"
)
xt "86750,68600,97950,70000"
st "encoderBSynch"
blo "86750,69800"
tm "WireNameMgr"
)
)
on &235
)
*340 (Wire
uid 4331,0
shape (OrthoPolyLine
uid 4332,0
va (VaSet
vasetType 3
)
xt "84750,72000,97000,100000"
pts [
"84750,72000"
"90000,72000"
"90000,100000"
"97000,100000"
]
)
start &270
end &222
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4333,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4334,0
va (VaSet
font "Verdana,12,0"
)
xt "86750,70600,97650,72000"
st "encoderISynch"
blo "86750,71800"
tm "WireNameMgr"
)
)
on &237
)
*341 (Wire
uid 4884,0
shape (OrthoPolyLine
uid 4885,0
va (VaSet
vasetType 3
)
xt "60000,64000,67250,64000"
pts [
"67250,64000"
"60000,64000"
]
)
start &272
end &245
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4888,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4889,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,62600,69200,64000"
st "LCD_CS1_n"
blo "61000,63800"
tm "WireNameMgr"
)
)
on &250
)
*342 (Wire
uid 4892,0
shape (OrthoPolyLine
uid 4893,0
va (VaSet
vasetType 3
)
xt "60000,66000,67250,66000"
pts [
"67250,66000"
"60000,66000"
]
)
start &273
end &246
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4896,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4897,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,64600,67500,66000"
st "LCD_SCL"
blo "61000,65800"
tm "WireNameMgr"
)
)
on &251
)
*343 (Wire
uid 4900,0
shape (OrthoPolyLine
uid 4901,0
va (VaSet
vasetType 3
)
xt "60000,68000,67250,68000"
pts [
"67250,68000"
"60000,68000"
]
)
start &274
end &247
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4904,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4905,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,66600,66400,68000"
st "LCD_SI"
blo "61000,67800"
tm "WireNameMgr"
)
)
on &252
)
*344 (Wire
uid 4908,0
shape (OrthoPolyLine
uid 4909,0
va (VaSet
vasetType 3
)
xt "60000,70000,67250,70000"
pts [
"67250,70000"
"60000,70000"
]
)
start &275
end &248
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4912,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4913,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,68600,66700,70000"
st "LCD_A0"
blo "61000,69800"
tm "WireNameMgr"
)
)
on &253
)
*345 (Wire
uid 4916,0
shape (OrthoPolyLine
uid 4917,0
va (VaSet
vasetType 3
)
xt "60000,72000,67250,72000"
pts [
"67250,72000"
"60000,72000"
]
)
start &276
end &249
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 4920,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4921,0
va (VaSet
font "Verdana,12,0"
)
xt "61000,70600,69000,72000"
st "LCD_RST_n"
blo "61000,71800"
tm "WireNameMgr"
)
)
on &254
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "32768,32768,32768"
)
packageList *346 (PackageList
uid 187,0
stg "VerticalLayoutStrategy"
textVec [
*347 (Text
uid 1297,0
va (VaSet
font "Verdana,8,1"
)
xt "-7000,19000,-500,19900"
st "Package List"
blo "-7000,19700"
)
*348 (MLText
uid 1298,0
va (VaSet
)
xt "-7000,20000,10700,28400"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;
LIBRARY gates;
  USE gates.gates.all;
LIBRARY Common;
  USE Common.CommonLib.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 190,0
stg "VerticalLayoutStrategy"
textVec [
*349 (Text
uid 191,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,0,32000,1000"
st "Compiler Directives"
blo "20000,800"
)
*350 (Text
uid 192,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,1400,33800,2400"
st "Pre-module directives:"
blo "20000,2200"
)
*351 (MLText
uid 193,0
va (VaSet
isHidden 1
)
xt "20000,2800,32100,5200"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*352 (Text
uid 194,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,5600,34400,6600"
st "Post-module directives:"
blo "20000,6400"
)
*353 (MLText
uid 195,0
va (VaSet
isHidden 1
)
xt "20000,7000,20000,7000"
tm "BdCompilerDirectivesTextMgr"
)
*354 (Text
uid 196,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,7200,33800,8200"
st "End-module directives:"
blo "20000,8000"
)
*355 (MLText
uid 197,0
va (VaSet
isHidden 1
)
xt "20000,1200,20000,1200"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "84,44,1182,895"
viewArea "-9157,16860,147244,120270"
cachedDiagramExtent "-53000,0,180750,118000"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\SUN\\PREA203_HPLJ2430DTN.PRINTERS.SYSTEM.SION.HEVs,winspool,"
fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
toPrinter 1
numCopies 2
xMargin 48
yMargin 48
paperWidth 761
paperHeight 1077
unixPaperWidth 595
unixPaperHeight 842
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4"
unixPaperName "A4  (210mm x 297mm)"
windowsPaperName "A4"
scale 50
titlesVisible 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "-7000,19000"
lastUid 6003,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,10,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*356 (Text
va (VaSet
)
xt "1500,2550,6100,3750"
st "<library>"
blo "1500,3550"
tm "BdLibraryNameMgr"
)
*357 (Text
va (VaSet
)
xt "1500,3750,5600,4950"
st "<block>"
blo "1500,4750"
tm "BlkNameMgr"
)
*358 (Text
va (VaSet
)
xt "1500,4950,2700,6150"
st "I0"
blo "1500,5950"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "1500,12550,1500,12550"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-600,0,8600,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*359 (Text
va (VaSet
)
xt "-100,3000,2200,4000"
st "Library"
blo "-100,3800"
)
*360 (Text
va (VaSet
)
xt "-100,4000,5900,5000"
st "MWComponent"
blo "-100,4800"
)
*361 (Text
va (VaSet
)
xt "-100,5000,500,6000"
st "I0"
blo "-100,5800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-7100,1000,-7100,1000"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-850,0,8850,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*362 (Text
va (VaSet
)
xt "-350,2550,1950,3550"
st "Library"
blo "-350,3350"
tm "BdLibraryNameMgr"
)
*363 (Text
va (VaSet
)
xt "-350,3550,5150,4550"
st "SaComponent"
blo "-350,4350"
tm "CptNameMgr"
)
*364 (Text
va (VaSet
)
xt "-350,4550,250,5550"
st "I0"
blo "-350,5350"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-7350,550,-7350,550"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-1350,0,9350,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*365 (Text
va (VaSet
)
xt "-850,2550,1450,3550"
st "Library"
blo "-850,3350"
)
*366 (Text
va (VaSet
)
xt "-850,3550,5250,4550"
st "VhdlComponent"
blo "-850,4350"
)
*367 (Text
va (VaSet
)
xt "-850,4550,-250,5550"
st "I0"
blo "-850,5350"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-7850,550,-7850,550"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2100,0,10100,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*368 (Text
va (VaSet
)
xt "-1600,2550,700,3550"
st "Library"
blo "-1600,3350"
)
*369 (Text
va (VaSet
)
xt "-1600,3550,5500,4550"
st "VerilogComponent"
blo "-1600,4350"
)
*370 (Text
va (VaSet
)
xt "-1600,4550,-1000,5550"
st "I0"
blo "-1600,5350"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-8600,550,-8600,550"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*371 (Text
va (VaSet
)
xt "2950,3400,4150,4400"
st "eb1"
blo "2950,4200"
tm "HdlTextNameMgr"
)
*372 (Text
va (VaSet
)
xt "2950,4400,3350,5400"
st "1"
blo "2950,5200"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,3200,1400"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-2875,-375,-2875,-375"
ju 2
blo "-2875,-375"
tm "WireNameMgr"
)
s (Text
va (VaSet
font "Verdana,12,0"
)
xt "-2875,-375,-2875,-375"
ju 2
blo "-2875,-375"
tm "SignalTypeMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "2875,-375,2875,-375"
blo "2875,-375"
tm "WireNameMgr"
)
s (Text
va (VaSet
font "Verdana,12,0"
)
xt "2875,-375,2875,-375"
blo "2875,-375"
tm "SignalTypeMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
s (Text
va (VaSet
font "Verdana,12,0"
)
xt "3000,500,3000,500"
blo "3000,500"
tm "SignalTypeMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
s (Text
va (VaSet
font "Verdana,12,0"
)
xt "3000,500,3000,500"
blo "3000,500"
tm "SignalTypeMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1500,2200"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,50000"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
xt "0,0,5000,1200"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1000,9600,2200"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1400,18500,-200"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1750"
)
num (Text
va (VaSet
)
xt "200,300,600,1300"
st "1"
blo "200,1100"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*373 (Text
va (VaSet
font "Verdana,8,1"
)
xt "11800,20000,19700,21000"
st "Frame Declarations"
blo "11800,20800"
)
*374 (MLText
va (VaSet
)
xt "11800,21000,11800,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1400,11000,-200"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1750"
)
num (Text
va (VaSet
)
xt "200,300,600,1300"
st "1"
blo "200,1100"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*375 (Text
va (VaSet
font "Verdana,8,1"
)
xt "11800,20000,19700,21000"
st "Frame Declarations"
blo "11800,20800"
)
*376 (MLText
va (VaSet
)
xt "11800,21000,11800,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
isHidden 1
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
)
xt "-7000,98400,-500,99300"
st "Declarations"
blo "-7000,99100"
)
portLabel (Text
uid 3,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "-7000,99600,-4000,100500"
st "Ports:"
blo "-7000,100300"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "-7000,99300,-2500,100200"
st "Pre User:"
blo "-7000,100000"
)
preUserText (MLText
uid 5,0
va (VaSet
)
xt "-5000,100200,53300,109800"
st "constant stepsPerTurn : positive := 500 * 4;
constant cmPerTurn : real:= 0.175;
constant position0 : positive := integer(3.5 * real(stepsPerTurn) / cmPerTurn);
constant position1 : positive := integer(8.0 * real(stepsPerTurn) / cmPerTurn);
constant position2 : positive := integer(12.0 * real(stepsPerTurn) / cmPerTurn);
constant pwmBitNb : positive := 8;
constant slopeShiftBitNb : positive := requiredBitNb(integer(real(stepsPerTurn)/cmPerTurn+0.5)) - pwmBitNb;
constant testLineNb : positive := 16;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "-7000,99600,1500,100500"
st "Diagram Signals:"
blo "-7000,100300"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "-7000,99600,-1500,100500"
st "Post User:"
blo "-7000,100300"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
)
xt "-5000,114000,-5000,114000"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 55,0
usingSuid 1
emptyRow *377 (LEmptyRow
)
uid 4442,0
optionalChildren [
*378 (RefLabelRowHdr
)
*379 (TitleRowHdr
)
*380 (FilterRowHdr
)
*381 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*382 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*383 (GroupColHdr
tm "GroupColHdrMgr"
)
*384 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*385 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*386 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*387 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*388 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*389 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*390 (LeafLogPort
port (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 1,0
)
)
uid 4359,0
)
*391 (LeafLogPort
port (LogicalPort
decl (Decl
n "reset_n"
t "std_ulogic"
o 8
suid 2,0
)
)
uid 4361,0
)
*392 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset"
t "std_ulogic"
o 36
suid 3,0
)
)
uid 4363,0
)
*393 (LeafLogPort
port (LogicalPort
decl (Decl
n "testMode"
t "std_uLogic"
o 12
suid 4,0
)
)
uid 4365,0
)
*394 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "resetSynch"
t "std_ulogic"
o 37
suid 5,0
)
)
uid 4367,0
)
*395 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "logic1"
t "std_uLogic"
o 35
suid 6,0
)
)
uid 4369,0
)
*396 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "resetSynch_n"
t "std_ulogic"
o 38
suid 7,0
)
)
uid 4371,0
)
*397 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LED1"
t "std_uLogic"
o 18
suid 8,0
)
)
uid 4373,0
)
*398 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LED2"
t "std_ulogic"
o 19
suid 9,0
)
)
uid 4375,0
)
*399 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "testOut"
t "std_uLogic_vector"
b "(1 TO testLineNb)"
o 46
suid 10,0
)
)
uid 4377,0
)
*400 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "restart"
t "std_uLogic"
o 39
suid 11,0
)
)
uid 4379,0
)
*401 (LeafLogPort
port (LogicalPort
decl (Decl
n "restart_n"
t "std_uLogic"
o 9
suid 12,0
)
)
uid 4381,0
)
*402 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "restartSynch"
t "std_uLogic"
o 40
suid 13,0
)
)
uid 4383,0
)
*403 (LeafLogPort
port (LogicalPort
decl (Decl
n "sensor1_n"
t "std_uLogic"
o 10
suid 14,0
)
)
uid 4385,0
)
*404 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor1"
t "std_uLogic"
o 41
suid 15,0
)
)
uid 4387,0
)
*405 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor1Synch"
t "std_uLogic"
o 42
suid 16,0
)
)
uid 4389,0
)
*406 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor2Synch"
t "std_uLogic"
o 44
suid 17,0
)
)
uid 4391,0
)
*407 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor2"
t "std_uLogic"
o 43
suid 18,0
)
)
uid 4393,0
)
*408 (LeafLogPort
port (LogicalPort
decl (Decl
n "sensor2_n"
t "std_uLogic"
o 11
suid 19,0
)
)
uid 4395,0
)
*409 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "motorOn"
t "std_uLogic"
o 21
suid 20,0
)
)
uid 4397,0
)
*410 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "side1"
t "std_uLogic"
o 22
suid 22,0
)
)
uid 4401,0
)
*411 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "side2"
t "std_uLogic"
o 23
suid 23,0
)
)
uid 4403,0
)
*412 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "setPoint"
t "std_uLogic"
o 45
suid 25,0
)
)
uid 4407,0
)
*413 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "go2Synch"
t "std_uLogic"
o 34
suid 27,0
)
)
uid 4411,0
)
*414 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "go2"
t "std_uLogic"
o 33
suid 28,0
)
)
uid 4413,0
)
*415 (LeafLogPort
port (LogicalPort
decl (Decl
n "go2_n"
t "std_uLogic"
o 7
suid 29,0
)
)
uid 4415,0
)
*416 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "go1Synch"
t "std_uLogic"
o 32
suid 30,0
)
)
uid 4417,0
)
*417 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "go1"
t "std_uLogic"
o 31
suid 31,0
)
)
uid 4419,0
)
*418 (LeafLogPort
port (LogicalPort
decl (Decl
n "go1_n"
t "std_uLogic"
o 6
suid 32,0
)
)
uid 4421,0
)
*419 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "encoderASynch"
t "std_uLogic"
o 26
suid 33,0
)
)
uid 4423,0
)
*420 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "encoderBSynch"
t "std_uLogic"
o 28
suid 34,0
)
)
uid 4425,0
)
*421 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "encoderB"
t "std_uLogic"
o 27
suid 35,0
)
)
uid 4427,0
)
*422 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "encoderISynch"
t "std_uLogic"
o 30
suid 36,0
)
)
uid 4429,0
)
*423 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "encoderI"
t "std_uLogic"
o 29
suid 37,0
)
)
uid 4431,0
)
*424 (LeafLogPort
port (LogicalPort
decl (Decl
n "encoderI_n"
t "std_uLogic"
o 5
suid 38,0
)
)
uid 4433,0
)
*425 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "encoderA"
t "std_uLogic"
o 25
suid 39,0
)
)
uid 4435,0
)
*426 (LeafLogPort
port (LogicalPort
decl (Decl
n "encoderA_n"
t "std_uLogic"
o 3
suid 40,0
)
)
uid 4437,0
)
*427 (LeafLogPort
port (LogicalPort
decl (Decl
n "encoderB_n"
t "std_uLogic"
o 4
suid 41,0
)
)
uid 4439,0
)
*428 (LeafLogPort
port (LogicalPort
decl (Decl
n "button4_n"
t "std_uLogic"
o 1
suid 42,0
)
)
uid 4693,0
)
*429 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "button4Synch"
t "std_uLogic"
o 24
suid 43,0
)
)
uid 4695,0
)
*430 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LCD_CS1_n"
t "std_ulogic"
o 14
suid 49,0
)
)
uid 5048,0
)
*431 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LCD_SCL"
t "std_ulogic"
o 16
suid 50,0
)
)
uid 5050,0
)
*432 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LCD_SI"
t "std_ulogic"
o 17
suid 51,0
)
)
uid 5052,0
)
*433 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LCD_A0"
t "std_ulogic"
o 13
suid 52,0
)
)
uid 5054,0
)
*434 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LCD_RST_n"
t "std_ulogic"
o 15
suid 53,0
)
)
uid 5056,0
)
*435 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LEDs"
t "std_uLogic_vector"
b "(1 TO 8)"
o 20
suid 55,0
)
)
uid 5718,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 4455,0
optionalChildren [
*436 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *437 (MRCItem
litem &377
pos 46
dimension 20
)
uid 4457,0
optionalChildren [
*438 (MRCItem
litem &378
pos 0
dimension 20
uid 4458,0
)
*439 (MRCItem
litem &379
pos 1
dimension 23
uid 4459,0
)
*440 (MRCItem
litem &380
pos 2
hidden 1
dimension 20
uid 4460,0
)
*441 (MRCItem
litem &390
pos 0
dimension 20
uid 4360,0
)
*442 (MRCItem
litem &391
pos 1
dimension 20
uid 4362,0
)
*443 (MRCItem
litem &392
pos 23
dimension 20
uid 4364,0
)
*444 (MRCItem
litem &393
pos 2
dimension 20
uid 4366,0
)
*445 (MRCItem
litem &394
pos 24
dimension 20
uid 4368,0
)
*446 (MRCItem
litem &395
pos 25
dimension 20
uid 4370,0
)
*447 (MRCItem
litem &396
pos 26
dimension 20
uid 4372,0
)
*448 (MRCItem
litem &397
pos 3
dimension 20
uid 4374,0
)
*449 (MRCItem
litem &398
pos 4
dimension 20
uid 4376,0
)
*450 (MRCItem
litem &399
pos 27
dimension 20
uid 4378,0
)
*451 (MRCItem
litem &400
pos 28
dimension 20
uid 4380,0
)
*452 (MRCItem
litem &401
pos 5
dimension 20
uid 4382,0
)
*453 (MRCItem
litem &402
pos 29
dimension 20
uid 4384,0
)
*454 (MRCItem
litem &403
pos 6
dimension 20
uid 4386,0
)
*455 (MRCItem
litem &404
pos 30
dimension 20
uid 4388,0
)
*456 (MRCItem
litem &405
pos 31
dimension 20
uid 4390,0
)
*457 (MRCItem
litem &406
pos 32
dimension 20
uid 4392,0
)
*458 (MRCItem
litem &407
pos 33
dimension 20
uid 4394,0
)
*459 (MRCItem
litem &408
pos 7
dimension 20
uid 4396,0
)
*460 (MRCItem
litem &409
pos 8
dimension 20
uid 4398,0
)
*461 (MRCItem
litem &410
pos 9
dimension 20
uid 4402,0
)
*462 (MRCItem
litem &411
pos 10
dimension 20
uid 4404,0
)
*463 (MRCItem
litem &412
pos 34
dimension 20
uid 4408,0
)
*464 (MRCItem
litem &413
pos 35
dimension 20
uid 4412,0
)
*465 (MRCItem
litem &414
pos 36
dimension 20
uid 4414,0
)
*466 (MRCItem
litem &415
pos 11
dimension 20
uid 4416,0
)
*467 (MRCItem
litem &416
pos 37
dimension 20
uid 4418,0
)
*468 (MRCItem
litem &417
pos 38
dimension 20
uid 4420,0
)
*469 (MRCItem
litem &418
pos 12
dimension 20
uid 4422,0
)
*470 (MRCItem
litem &419
pos 39
dimension 20
uid 4424,0
)
*471 (MRCItem
litem &420
pos 40
dimension 20
uid 4426,0
)
*472 (MRCItem
litem &421
pos 41
dimension 20
uid 4428,0
)
*473 (MRCItem
litem &422
pos 42
dimension 20
uid 4430,0
)
*474 (MRCItem
litem &423
pos 43
dimension 20
uid 4432,0
)
*475 (MRCItem
litem &424
pos 13
dimension 20
uid 4434,0
)
*476 (MRCItem
litem &425
pos 44
dimension 20
uid 4436,0
)
*477 (MRCItem
litem &426
pos 14
dimension 20
uid 4438,0
)
*478 (MRCItem
litem &427
pos 15
dimension 20
uid 4440,0
)
*479 (MRCItem
litem &428
pos 16
dimension 20
uid 4694,0
)
*480 (MRCItem
litem &429
pos 45
dimension 20
uid 4696,0
)
*481 (MRCItem
litem &430
pos 17
dimension 20
uid 5049,0
)
*482 (MRCItem
litem &431
pos 18
dimension 20
uid 5051,0
)
*483 (MRCItem
litem &432
pos 19
dimension 20
uid 5053,0
)
*484 (MRCItem
litem &433
pos 20
dimension 20
uid 5055,0
)
*485 (MRCItem
litem &434
pos 21
dimension 20
uid 5057,0
)
*486 (MRCItem
litem &435
pos 22
dimension 20
uid 5719,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 4461,0
optionalChildren [
*487 (MRCItem
litem &381
pos 0
dimension 20
uid 4462,0
)
*488 (MRCItem
litem &383
pos 1
dimension 50
uid 4463,0
)
*489 (MRCItem
litem &384
pos 2
dimension 100
uid 4464,0
)
*490 (MRCItem
litem &385
pos 3
dimension 50
uid 4465,0
)
*491 (MRCItem
litem &386
pos 4
dimension 100
uid 4466,0
)
*492 (MRCItem
litem &387
pos 5
dimension 100
uid 4467,0
)
*493 (MRCItem
litem &388
pos 6
dimension 50
uid 4468,0
)
*494 (MRCItem
litem &389
pos 7
dimension 80
uid 4469,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 4456,0
vaOverrides [
]
)
]
)
uid 4441,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *495 (LEmptyRow
)
uid 4471,0
optionalChildren [
*496 (RefLabelRowHdr
)
*497 (TitleRowHdr
)
*498 (FilterRowHdr
)
*499 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*500 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*501 (GroupColHdr
tm "GroupColHdrMgr"
)
*502 (NameColHdr
tm "GenericNameColHdrMgr"
)
*503 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*504 (InitColHdr
tm "GenericValueColHdrMgr"
)
*505 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*506 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 4483,0
optionalChildren [
*507 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *508 (MRCItem
litem &495
pos 0
dimension 20
)
uid 4485,0
optionalChildren [
*509 (MRCItem
litem &496
pos 0
dimension 20
uid 4486,0
)
*510 (MRCItem
litem &497
pos 1
dimension 23
uid 4487,0
)
*511 (MRCItem
litem &498
pos 2
hidden 1
dimension 20
uid 4488,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 4489,0
optionalChildren [
*512 (MRCItem
litem &499
pos 0
dimension 20
uid 4490,0
)
*513 (MRCItem
litem &501
pos 1
dimension 50
uid 4491,0
)
*514 (MRCItem
litem &502
pos 2
dimension 100
uid 4492,0
)
*515 (MRCItem
litem &503
pos 3
dimension 100
uid 4493,0
)
*516 (MRCItem
litem &504
pos 4
dimension 50
uid 4494,0
)
*517 (MRCItem
litem &505
pos 5
dimension 50
uid 4495,0
)
*518 (MRCItem
litem &506
pos 6
dimension 80
uid 4496,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 4484,0
vaOverrides [
]
)
]
)
uid 4470,0
type 1
)
activeModelName "BlockDiag"
)