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Cursor/Libs/Sequential/hdl/counter_rtl.vhd
2021-11-24 10:50:51 +01:00

19 lines
343 B
VHDL

ARCHITECTURE RTL OF counter IS
signal count: unsigned(countOut'range);
BEGIN
countEndlessly: process(reset, clock)
begin
if reset = '1' then
count <= (others => '0');
elsif rising_edge(clock) then
count <= count+1;
end if;
end process countEndlessly;
countOut <= count after delay;
END ARCHITECTURE RTL;