mirror of
https://github.com/Klagarge/Cursor.git
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3438 lines
42 KiB
Plaintext
3438 lines
42 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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instances [
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|
(Instance
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name "I_tester"
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duLibraryName "Lcd_test"
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duName "lcdController_tester"
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elements [
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|
(GiElement
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|
name "clockFrequency"
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|
type "real"
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value "clockFrequency"
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)
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|
(GiElement
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|
name "asciiBitNb"
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|
type "positive"
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|
value "asciiBitNb"
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|
)
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|
]
|
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mwi 0
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|
uid 175,0
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|
)
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|
(Instance
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|
name "I_dut"
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|
duLibraryName "Lcd"
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|
duName "lcdController"
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|
elements [
|
|
(GiElement
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|
name "baudRateDivide"
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|
type "integer"
|
|
value "baudRateDivide"
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|
)
|
|
(GiElement
|
|
name "asciiBitNb"
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type "positive"
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value "asciiBitNb"
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)
|
|
]
|
|
mwi 0
|
|
uid 3514,0
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|
)
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|
]
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libraryRefs [
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|
"ieee"
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|
]
|
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)
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|
version "32.1"
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|
appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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|
model (BlockDiag
|
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VExpander (VariableExpander
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|
vvMap [
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|
(vvPair
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|
variable " "
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|
value " "
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)
|
|
(vvPair
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|
variable "HDLDir"
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|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hdl"
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|
)
|
|
(vvPair
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|
variable "HDSDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds"
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|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
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|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tb\\struct.bd.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
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|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tb\\struct.bd.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
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|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tb"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdController_tb"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "11.11.2019"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Mon"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Monday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "lcdController_tb"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "11.11.2019"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "07:37:47"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Lcd_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "$HDS_PROJECT_DIR/../libs/SPI_test/concat"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/ElN/Libraries/Lcd_test/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "lcdController_tb"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Nov"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "November"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdController_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ActelPath"
|
|
value "D:\\Projects\\Trypano\\ControlBoard\\IglooTester\\Board\\actel\\boardTester"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$SCRATCH_DIR\\BoardTester\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "07:37:47"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "lcdController_tb"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
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|
)
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]
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)
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uid 20,0
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st "
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Edited:
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tm "CommentText"
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visibleWidth 4600
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)
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)
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xt "46000,58000,97000,66000"
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)
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oxt "13000,22000,64000,30000"
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va (VaSet
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)
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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)
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tm "BdLibraryNameMgr"
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tm "BlkNameMgr"
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font "Verdana,9,1"
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)
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xt "25300,50900,29300,51800"
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blo "25300,51600"
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)
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ga (GenericAssociation
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uid 181,0
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viewicon (ZoomableIcon
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uid 2324,0
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decl (Decl
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declText (MLText
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decl (Decl
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n "CS1_n"
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va (VaSet
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uid 3049,0
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decl (Decl
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n "RST_n"
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declText (MLText
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va (VaSet
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uid 3057,0
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decl (Decl
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n "A0"
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declText (MLText
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,14600,13600,15600"
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uid 3065,0
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decl (Decl
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n "SCL"
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)
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declText (MLText
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,17600,13800,18600"
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)
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)
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uid 3073,0
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decl (Decl
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n "SI"
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t "std_ulogic"
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o 5
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declText (MLText
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uid 3074,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,18600,13400,19600"
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uid 3199,0
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decl (Decl
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n "send"
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t "std_ulogic"
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o 10
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suid 53,0
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)
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declText (MLText
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uid 3200,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,23600,13900,24600"
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st "SIGNAL send : std_ulogic"
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)
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)
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*24 (Net
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uid 3207,0
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decl (Decl
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n "ascii"
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t "std_ulogic_vector"
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b "(asciiBitNb-1 downto 0)"
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o 6
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suid 54,0
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)
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declText (MLText
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uid 3208,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,19600,26500,20600"
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st "SIGNAL ascii : std_ulogic_vector(asciiBitNb-1 downto 0)"
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)
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uid 3414,0
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decl (Decl
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n "busy"
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t "std_ulogic"
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o 7
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|
suid 55,0
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)
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declText (MLText
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uid 3415,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,20600,13900,21600"
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st "SIGNAL busy : std_ulogic"
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uid 3514,0
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optionalChildren [
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uid 3474,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 3475,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
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uid 3476,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 3477,0
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va (VaSet
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)
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xt "46000,27400,48500,28300"
|
|
st "clock"
|
|
blo "46000,28100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
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|
decl (Decl
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n "clock"
|
|
t "std_ulogic"
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|
o 7
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|
suid 1,0
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)
|
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)
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)
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*28 (CptPort
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uid 3478,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 3479,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "44250,29625,45000,30375"
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)
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tg (CPTG
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uid 3480,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 3481,0
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va (VaSet
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)
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xt "46000,29400,48500,30300"
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st "reset"
|
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blo "46000,30100"
|
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)
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)
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thePort (LogicalPort
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decl (Decl
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n "reset"
|
|
t "std_ulogic"
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|
o 1
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|
suid 2,0
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)
|
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)
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)
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*29 (CptPort
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uid 3482,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 3483,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "61000,19625,61750,20375"
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)
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tg (CPTG
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uid 3484,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 3485,0
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va (VaSet
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)
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xt "59000,19400,60000,20300"
|
|
st "SI"
|
|
ju 2
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|
blo "60000,20100"
|
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)
|
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)
|
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thePort (LogicalPort
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m 1
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|
decl (Decl
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n "SI"
|
|
t "std_ulogic"
|
|
o 2
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|
suid 3,0
|
|
)
|
|
)
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|
)
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*30 (CptPort
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uid 3486,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 3487,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
|
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)
|
|
xt "61000,21625,61750,22375"
|
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)
|
|
tg (CPTG
|
|
uid 3488,0
|
|
ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 3489,0
|
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va (VaSet
|
|
)
|
|
xt "58500,21400,60000,22300"
|
|
st "SCL"
|
|
ju 2
|
|
blo "60000,22100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "SCL"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
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*31 (CptPort
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|
uid 3490,0
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ps "OnEdgeStrategy"
|
|
shape (Triangle
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uid 3491,0
|
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ro 90
|
|
va (VaSet
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|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "61000,23625,61750,24375"
|
|
)
|
|
tg (CPTG
|
|
uid 3492,0
|
|
ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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|
f (Text
|
|
uid 3493,0
|
|
va (VaSet
|
|
)
|
|
xt "59000,23400,60000,24300"
|
|
st "A0"
|
|
ju 2
|
|
blo "60000,24100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "A0"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*32 (CptPort
|
|
uid 3494,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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uid 3495,0
|
|
ro 90
|
|
va (VaSet
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|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "44250,19625,45000,20375"
|
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)
|
|
tg (CPTG
|
|
uid 3496,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3497,0
|
|
va (VaSet
|
|
)
|
|
xt "46000,19400,48500,20300"
|
|
st "ascii"
|
|
blo "46000,20100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "ascii"
|
|
t "std_ulogic_vector"
|
|
b "(asciiBitNb-1 downto 0)"
|
|
o 8
|
|
suid 11,0
|
|
)
|
|
)
|
|
)
|
|
*33 (CptPort
|
|
uid 3498,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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uid 3499,0
|
|
ro 90
|
|
va (VaSet
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|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "44250,21625,45000,22375"
|
|
)
|
|
tg (CPTG
|
|
uid 3500,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3501,0
|
|
va (VaSet
|
|
)
|
|
xt "46000,21400,48000,22300"
|
|
st "send"
|
|
blo "46000,22100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "send"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 21,0
|
|
)
|
|
)
|
|
)
|
|
*34 (CptPort
|
|
uid 3502,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3503,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "61000,27625,61750,28375"
|
|
)
|
|
tg (CPTG
|
|
uid 3504,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3505,0
|
|
va (VaSet
|
|
)
|
|
xt "57500,27400,60000,28300"
|
|
st "CS1_n"
|
|
ju 2
|
|
blo "60000,28100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "CS1_n"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 27,0
|
|
)
|
|
)
|
|
)
|
|
*35 (CptPort
|
|
uid 3506,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3507,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "61000,25625,61750,26375"
|
|
)
|
|
tg (CPTG
|
|
uid 3508,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3509,0
|
|
va (VaSet
|
|
)
|
|
xt "57500,25400,60000,26300"
|
|
st "RST_n"
|
|
ju 2
|
|
blo "60000,26100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "RST_n"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 28,0
|
|
)
|
|
)
|
|
)
|
|
*36 (CptPort
|
|
uid 3510,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3511,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "44250,23625,45000,24375"
|
|
)
|
|
tg (CPTG
|
|
uid 3512,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3513,0
|
|
va (VaSet
|
|
)
|
|
xt "46000,23400,48000,24300"
|
|
st "busy"
|
|
blo "46000,24100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "busy"
|
|
t "std_ulogic"
|
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o 10
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suid 29,0
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)
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)
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)
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shape (Rectangle
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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lineColor "0,32896,0"
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lineWidth 2
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)
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xt "45000,16000,61000,32000"
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)
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oxt "8000,12000,24000,28000"
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ttg (MlTextGroup
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uid 3516,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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va (VaSet
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)
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xt "45600,31800,47100,32700"
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st "Lcd"
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blo "45600,32500"
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tm "BdLibraryNameMgr"
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)
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*38 (Text
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uid 3518,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "45600,33000,52600,33900"
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st "lcdController"
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blo "45600,33700"
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tm "CptNameMgr"
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)
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uid 3519,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "45600,34200,48100,35100"
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st "I_dut"
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blo "45600,34900"
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tm "InstanceNameMgr"
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)
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|
]
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)
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ga (GenericAssociation
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uid 3520,0
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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uid 3521,0
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text (MLText
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uid 3522,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "45000,35800,67400,37800"
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st "baudRateDivide = baudRateDivide ( integer )
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asciiBitNb = asciiBitNb ( positive ) "
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)
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header ""
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)
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elements [
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name "baudRateDivide"
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type "integer"
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value "baudRateDivide"
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)
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name "asciiBitNb"
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type "positive"
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value "asciiBitNb"
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)
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)
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viewicon (ZoomableIcon
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uid 3523,0
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sl 0
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va (VaSet
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vasetType 1
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fg "49152,49152,49152"
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)
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xt "45250,30250,46750,31750"
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iconName "BlockDiagram.png"
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iconMaskName "BlockDiagram.msk"
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ftype 1
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)
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ordering 1
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viewiconposition 0
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portVis (PortSigDisplay
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sTC 0
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)
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archFileType "UNKNOWN"
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)
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va (VaSet
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vasetType 3
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)
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xt "43000,30000,44250,40000"
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pts [
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]
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)
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|
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end &12
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sat 32
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eat 2
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st 0
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sf 1
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si 0
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tg (WTG
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uid 2322,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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)
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xt "41250,28600,45350,30000"
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st "reset"
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blo "41250,29800"
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tm "WireNameMgr"
|
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)
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)
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on &16
|
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)
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*41 (Wire
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uid 2326,0
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shape (OrthoPolyLine
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uid 2327,0
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va (VaSet
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vasetType 3
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)
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xt "41000,28000,44250,40000"
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pts [
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"41000,28000"
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"41000,40000"
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]
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)
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start &27
|
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end &12
|
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sat 32
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eat 2
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st 0
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sf 1
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si 0
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tg (WTG
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uid 2330,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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uid 2331,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "41250,26600,45050,28000"
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st "clock"
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blo "41250,27800"
|
|
tm "WireNameMgr"
|
|
)
|
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)
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on &17
|
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)
|
|
*42 (Wire
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|
uid 3043,0
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shape (OrthoPolyLine
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uid 3044,0
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va (VaSet
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vasetType 3
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)
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xt "61750,28000,65000,40000"
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pts [
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|
"65000,28000"
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|
"65000,40000"
|
|
]
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)
|
|
start &34
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
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uid 3047,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
|
|
uid 3048,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "63750,26600,68650,28000"
|
|
st "CS1_n"
|
|
blo "63750,27800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &18
|
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)
|
|
*43 (Wire
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|
uid 3051,0
|
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shape (OrthoPolyLine
|
|
uid 3052,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61750,26000,67000,40000"
|
|
pts [
|
|
"61750,26000"
|
|
"67000,26000"
|
|
"67000,40000"
|
|
]
|
|
)
|
|
start &35
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3055,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3056,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
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)
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|
xt "63750,24600,68450,26000"
|
|
st "RST_n"
|
|
blo "63750,25800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*44 (Wire
|
|
uid 3059,0
|
|
shape (OrthoPolyLine
|
|
uid 3060,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61750,24000,69000,40000"
|
|
pts [
|
|
"61750,24000"
|
|
"69000,24000"
|
|
"69000,40000"
|
|
]
|
|
)
|
|
start &31
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3063,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3064,0
|
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va (VaSet
|
|
font "Verdana,12,0"
|
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)
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|
xt "63750,22600,66150,24000"
|
|
st "A0"
|
|
blo "63750,23800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &20
|
|
)
|
|
*45 (Wire
|
|
uid 3067,0
|
|
shape (OrthoPolyLine
|
|
uid 3068,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61750,22000,71000,40000"
|
|
pts [
|
|
"61750,22000"
|
|
"71000,22000"
|
|
"71000,40000"
|
|
]
|
|
)
|
|
start &30
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3071,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3072,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63750,20600,66950,22000"
|
|
st "SCL"
|
|
blo "63750,21800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &21
|
|
)
|
|
*46 (Wire
|
|
uid 3075,0
|
|
shape (OrthoPolyLine
|
|
uid 3076,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "61750,20000,73000,40000"
|
|
pts [
|
|
"61750,20000"
|
|
"73000,20000"
|
|
"73000,40000"
|
|
]
|
|
)
|
|
start &29
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3079,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3080,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63750,18600,65850,20000"
|
|
st "SI"
|
|
blo "63750,19800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &22
|
|
)
|
|
*47 (Wire
|
|
uid 3201,0
|
|
shape (OrthoPolyLine
|
|
uid 3202,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "35000,22000,44250,40000"
|
|
pts [
|
|
"44250,22000"
|
|
"35000,22000"
|
|
"35000,40000"
|
|
]
|
|
)
|
|
start &33
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3205,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3206,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "39250,20600,43150,22000"
|
|
st "send"
|
|
blo "39250,21800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &23
|
|
)
|
|
*48 (Wire
|
|
uid 3209,0
|
|
shape (OrthoPolyLine
|
|
uid 3210,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "33000,20000,44250,40000"
|
|
pts [
|
|
"44250,20000"
|
|
"33000,20000"
|
|
"33000,40000"
|
|
]
|
|
)
|
|
start &32
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3213,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3214,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "39250,18600,42750,20000"
|
|
st "ascii"
|
|
blo "39250,19800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &24
|
|
)
|
|
*49 (Wire
|
|
uid 3416,0
|
|
shape (OrthoPolyLine
|
|
uid 3417,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "37000,24000,44250,40000"
|
|
pts [
|
|
"44250,24000"
|
|
"37000,24000"
|
|
"37000,40000"
|
|
]
|
|
)
|
|
start &36
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 3420,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 3421,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "39250,22600,43050,24000"
|
|
st "busy"
|
|
blo "39250,23800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &25
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 1
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *50 (PackageList
|
|
uid 9,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*51 (Text
|
|
uid 10,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,0,6500,900"
|
|
st "Package List"
|
|
blo "0,700"
|
|
)
|
|
*52 (MLText
|
|
uid 11,0
|
|
va (VaSet
|
|
)
|
|
xt "0,1200,17500,4800"
|
|
st "LIBRARY ieee;
|
|
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|
|
USE ieee.numeric_std.all;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
compDirBlock (MlTextGroup
|
|
uid 12,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*53 (Text
|
|
uid 13,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,0,30000,900"
|
|
st "Compiler Directives"
|
|
blo "20000,700"
|
|
)
|
|
*54 (Text
|
|
uid 14,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,1000,31500,1900"
|
|
st "Pre-module directives:"
|
|
blo "20000,1700"
|
|
)
|
|
*55 (MLText
|
|
uid 15,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,2000,32100,4400"
|
|
st "`resetall
|
|
`timescale 1ns/10ps"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*56 (Text
|
|
uid 16,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,4000,32000,4900"
|
|
st "Post-module directives:"
|
|
blo "20000,4700"
|
|
)
|
|
*57 (MLText
|
|
uid 17,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,0,20000,0"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*58 (Text
|
|
uid 18,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,5000,31500,5900"
|
|
st "End-module directives:"
|
|
blo "20000,5700"
|
|
)
|
|
*59 (MLText
|
|
uid 19,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,6000,20000,6000"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
]
|
|
associable 1
|
|
)
|
|
windowSize "223,58,1277,917"
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|
viewArea "-1379,-1379,99073,68805"
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|
cachedDiagramExtent "0,0,97000,66000"
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|
pageSetupInfo (PageSetupInfo
|
|
ptrCmd ""
|
|
toPrinter 1
|
|
xMargin 48
|
|
yMargin 48
|
|
paperWidth 761
|
|
paperHeight 1077
|
|
unixPaperWidth 595
|
|
unixPaperHeight 842
|
|
windowsPaperWidth 761
|
|
windowsPaperHeight 1077
|
|
paperType "A4"
|
|
unixPaperName "A4 (210mm x 297mm)"
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|
windowsPaperName "A4"
|
|
windowsPaperType 9
|
|
scale 75
|
|
exportedDirectories [
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|
"$HDS_PROJECT_DIR/HTMLExport"
|
|
]
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|
boundaryWidth 0
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)
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hasePageBreakOrigin 1
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|
pageBreakOrigin "0,0"
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lastUid 3738,0
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defaultCommentText (CommentText
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shape (Rectangle
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va (VaSet
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tm "HdlTextMgr"
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visibleHeight 4600
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defaultBdJunction (BdJunction
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defaultPortIoIn (PortIoIn
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stc 0
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tg (WTG
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stg "STSignalDisplayStrategy"
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ju 2
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tm "WireNameMgr"
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defaultPortIoOut (PortIoOut
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stg "STSignalDisplayStrategy"
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blo "625,-1000"
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tm "WireNameMgr"
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defaultPortIoInOut (PortIoInOut
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tg (WTG
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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blo "0,-375"
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tm "WireNameMgr"
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defaultPortIoBuffer (PortIoBuffer
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shape (CompositeShape
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|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-400,3400,1000"
|
|
st "sig0"
|
|
blo "0,800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-400,4700,1000"
|
|
st "dbus0"
|
|
blo "0,800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineColor "32768,0,0"
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,-200,4700,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "-2950,-1200,15550,0"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1250,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "-50,150,1350,1350"
|
|
st "1"
|
|
blo "-50,1150"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*77 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "14100,20000,24900,21200"
|
|
st "Frame Declarations"
|
|
blo "14100,21000"
|
|
)
|
|
*78 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21200,14100,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "-1800,-1200,9200,0"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1250,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "-50,150,1350,1350"
|
|
st "1"
|
|
blo "-50,1150"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*79 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "14100,20000,24900,21200"
|
|
st "Frame Declarations"
|
|
blo "14100,21000"
|
|
)
|
|
*80 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21200,14100,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6000,6500,6900"
|
|
st "Declarations"
|
|
blo "0,6700"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6900,3000,7800"
|
|
st "Ports:"
|
|
blo "0,7600"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7800,4500,8700"
|
|
st "Pre User:"
|
|
blo "0,8500"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,8700,40600,13700"
|
|
st "constant clockFrequency: real := 66.0E6;
|
|
constant spiFrequency: real := 20.0E6;
|
|
constant baudRateDivide: positive := integer((clockFrequency/2.0)/spiFrequency + 1.0);
|
|
|
|
constant asciiBitNb: positive := 7;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,13700,8500,14600"
|
|
st "Diagram Signals:"
|
|
blo "0,14400"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6000,5500,6900"
|
|
st "Post User:"
|
|
blo "0,6700"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,6000,0,6000"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 55,0
|
|
usingSuid 1
|
|
emptyRow *81 (LEmptyRow
|
|
)
|
|
uid 22,0
|
|
optionalChildren [
|
|
*82 (RefLabelRowHdr
|
|
)
|
|
*83 (TitleRowHdr
|
|
)
|
|
*84 (FilterRowHdr
|
|
)
|
|
*85 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*86 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*87 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*88 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*89 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*90 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*91 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*92 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*93 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*94 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 37,0
|
|
)
|
|
)
|
|
uid 2392,0
|
|
)
|
|
*95 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 38,0
|
|
)
|
|
)
|
|
uid 2394,0
|
|
)
|
|
*96 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "CS1_n"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 47,0
|
|
)
|
|
)
|
|
uid 3081,0
|
|
)
|
|
*97 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "RST_n"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 48,0
|
|
)
|
|
)
|
|
uid 3083,0
|
|
)
|
|
*98 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "A0"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 49,0
|
|
)
|
|
)
|
|
uid 3085,0
|
|
)
|
|
*99 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "SCL"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 50,0
|
|
)
|
|
)
|
|
uid 3087,0
|
|
)
|
|
*100 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "SI"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 51,0
|
|
)
|
|
)
|
|
uid 3089,0
|
|
)
|
|
*101 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "send"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 53,0
|
|
)
|
|
)
|
|
uid 3217,0
|
|
)
|
|
*102 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "ascii"
|
|
t "std_ulogic_vector"
|
|
b "(asciiBitNb-1 downto 0)"
|
|
o 6
|
|
suid 54,0
|
|
)
|
|
)
|
|
uid 3219,0
|
|
)
|
|
*103 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "busy"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 55,0
|
|
)
|
|
)
|
|
uid 3422,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 35,0
|
|
optionalChildren [
|
|
*104 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *105 (MRCItem
|
|
litem &81
|
|
pos 10
|
|
dimension 20
|
|
)
|
|
uid 37,0
|
|
optionalChildren [
|
|
*106 (MRCItem
|
|
litem &82
|
|
pos 0
|
|
dimension 20
|
|
uid 38,0
|
|
)
|
|
*107 (MRCItem
|
|
litem &83
|
|
pos 1
|
|
dimension 23
|
|
uid 39,0
|
|
)
|
|
*108 (MRCItem
|
|
litem &84
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 40,0
|
|
)
|
|
*109 (MRCItem
|
|
litem &94
|
|
pos 0
|
|
dimension 20
|
|
uid 2393,0
|
|
)
|
|
*110 (MRCItem
|
|
litem &95
|
|
pos 1
|
|
dimension 20
|
|
uid 2395,0
|
|
)
|
|
*111 (MRCItem
|
|
litem &96
|
|
pos 2
|
|
dimension 20
|
|
uid 3082,0
|
|
)
|
|
*112 (MRCItem
|
|
litem &97
|
|
pos 3
|
|
dimension 20
|
|
uid 3084,0
|
|
)
|
|
*113 (MRCItem
|
|
litem &98
|
|
pos 4
|
|
dimension 20
|
|
uid 3086,0
|
|
)
|
|
*114 (MRCItem
|
|
litem &99
|
|
pos 5
|
|
dimension 20
|
|
uid 3088,0
|
|
)
|
|
*115 (MRCItem
|
|
litem &100
|
|
pos 6
|
|
dimension 20
|
|
uid 3090,0
|
|
)
|
|
*116 (MRCItem
|
|
litem &101
|
|
pos 7
|
|
dimension 20
|
|
uid 3218,0
|
|
)
|
|
*117 (MRCItem
|
|
litem &102
|
|
pos 8
|
|
dimension 20
|
|
uid 3220,0
|
|
)
|
|
*118 (MRCItem
|
|
litem &103
|
|
pos 9
|
|
dimension 20
|
|
uid 3423,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 41,0
|
|
optionalChildren [
|
|
*119 (MRCItem
|
|
litem &85
|
|
pos 0
|
|
dimension 20
|
|
uid 42,0
|
|
)
|
|
*120 (MRCItem
|
|
litem &87
|
|
pos 1
|
|
dimension 50
|
|
uid 43,0
|
|
)
|
|
*121 (MRCItem
|
|
litem &88
|
|
pos 2
|
|
dimension 100
|
|
uid 44,0
|
|
)
|
|
*122 (MRCItem
|
|
litem &89
|
|
pos 3
|
|
dimension 50
|
|
uid 45,0
|
|
)
|
|
*123 (MRCItem
|
|
litem &90
|
|
pos 4
|
|
dimension 100
|
|
uid 46,0
|
|
)
|
|
*124 (MRCItem
|
|
litem &91
|
|
pos 5
|
|
dimension 100
|
|
uid 47,0
|
|
)
|
|
*125 (MRCItem
|
|
litem &92
|
|
pos 6
|
|
dimension 50
|
|
uid 48,0
|
|
)
|
|
*126 (MRCItem
|
|
litem &93
|
|
pos 7
|
|
dimension 80
|
|
uid 49,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 36,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 21,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *127 (LEmptyRow
|
|
)
|
|
uid 51,0
|
|
optionalChildren [
|
|
*128 (RefLabelRowHdr
|
|
)
|
|
*129 (TitleRowHdr
|
|
)
|
|
*130 (FilterRowHdr
|
|
)
|
|
*131 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*132 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*133 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*134 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*135 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*136 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*137 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*138 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 63,0
|
|
optionalChildren [
|
|
*139 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *140 (MRCItem
|
|
litem &127
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 65,0
|
|
optionalChildren [
|
|
*141 (MRCItem
|
|
litem &128
|
|
pos 0
|
|
dimension 20
|
|
uid 66,0
|
|
)
|
|
*142 (MRCItem
|
|
litem &129
|
|
pos 1
|
|
dimension 23
|
|
uid 67,0
|
|
)
|
|
*143 (MRCItem
|
|
litem &130
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 68,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 69,0
|
|
optionalChildren [
|
|
*144 (MRCItem
|
|
litem &131
|
|
pos 0
|
|
dimension 20
|
|
uid 70,0
|
|
)
|
|
*145 (MRCItem
|
|
litem &133
|
|
pos 1
|
|
dimension 50
|
|
uid 71,0
|
|
)
|
|
*146 (MRCItem
|
|
litem &134
|
|
pos 2
|
|
dimension 100
|
|
uid 72,0
|
|
)
|
|
*147 (MRCItem
|
|
litem &135
|
|
pos 3
|
|
dimension 100
|
|
uid 73,0
|
|
)
|
|
*148 (MRCItem
|
|
litem &136
|
|
pos 4
|
|
dimension 50
|
|
uid 74,0
|
|
)
|
|
*149 (MRCItem
|
|
litem &137
|
|
pos 5
|
|
dimension 50
|
|
uid 75,0
|
|
)
|
|
*150 (MRCItem
|
|
litem &138
|
|
pos 6
|
|
dimension 80
|
|
uid 76,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 64,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 50,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|