mirror of
https://github.com/Klagarge/Cursor.git
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1811 lines
22 KiB
Plaintext
1811 lines
22 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 8,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 53,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
|
|
*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
|
|
*6 (RowExpandColHdr
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|
tm "RowExpandColHdrMgr"
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)
|
|
*7 (GroupColHdr
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|
tm "GroupColHdrMgr"
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|
)
|
|
*8 (NameColHdr
|
|
tm "NameColHdrMgr"
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)
|
|
*9 (ModeColHdr
|
|
tm "ModeColHdrMgr"
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|
)
|
|
*10 (TypeColHdr
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|
tm "TypeColHdrMgr"
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|
)
|
|
*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
|
|
*12 (InitColHdr
|
|
tm "InitColHdrMgr"
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)
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|
*13 (EolColHdr
|
|
tm "EolColHdrMgr"
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)
|
|
*14 (LogPort
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port (LogicalPort
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|
decl (Decl
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|
n "clock"
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t "std_ulogic"
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o 8
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suid 1,0
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)
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)
|
|
uid 148,0
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)
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*15 (LogPort
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port (LogicalPort
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|
m 1
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decl (Decl
|
|
n "dataTx"
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|
t "std_ulogic_vector"
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|
b "(dataBitNbTx-1 DOWNTO 0)"
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o 1
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suid 2,0
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)
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)
|
|
uid 150,0
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)
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*16 (LogPort
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port (LogicalPort
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|
decl (Decl
|
|
n "dataRx"
|
|
t "std_ulogic_vector"
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|
b "(dataBitNbRx-1 DOWNTO 0)"
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o 2
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suid 3,0
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)
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)
|
|
uid 152,0
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)
|
|
*17 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "emptyRx"
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t "std_ulogic"
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o 5
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suid 4,0
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)
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)
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uid 154,0
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|
)
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|
*18 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "fullTx"
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|
t "std_ulogic"
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|
o 3
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suid 5,0
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)
|
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)
|
|
uid 156,0
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|
)
|
|
*19 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "readRx"
|
|
t "std_ulogic"
|
|
o 7
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suid 6,0
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)
|
|
)
|
|
uid 158,0
|
|
)
|
|
*20 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_uLogic"
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|
o 6
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suid 7,0
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)
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)
|
|
uid 160,0
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|
)
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*21 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
|
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n "writeTx"
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|
t "std_ulogic"
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o 4
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suid 8,0
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)
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)
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uid 162,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 66,0
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optionalChildren [
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*22 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
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font "courier,10,0"
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)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
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font "courier,10,0"
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|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
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font "courier,10,0"
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|
)
|
|
emptyMRCItem *23 (MRCItem
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litem &1
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pos 8
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dimension 20
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)
|
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uid 68,0
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optionalChildren [
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*24 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 69,0
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)
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|
*25 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 70,0
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)
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*26 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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|
uid 71,0
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)
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*27 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 149,0
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)
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*28 (MRCItem
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litem &15
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|
pos 1
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|
dimension 20
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|
uid 151,0
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|
)
|
|
*29 (MRCItem
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|
litem &16
|
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pos 2
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|
dimension 20
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|
uid 153,0
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)
|
|
*30 (MRCItem
|
|
litem &17
|
|
pos 3
|
|
dimension 20
|
|
uid 155,0
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)
|
|
*31 (MRCItem
|
|
litem &18
|
|
pos 4
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dimension 20
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|
uid 157,0
|
|
)
|
|
*32 (MRCItem
|
|
litem &19
|
|
pos 5
|
|
dimension 20
|
|
uid 159,0
|
|
)
|
|
*33 (MRCItem
|
|
litem &20
|
|
pos 6
|
|
dimension 20
|
|
uid 161,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &21
|
|
pos 7
|
|
dimension 20
|
|
uid 163,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 72,0
|
|
optionalChildren [
|
|
*35 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 73,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 50
|
|
uid 74,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &8
|
|
pos 2
|
|
dimension 100
|
|
uid 75,0
|
|
)
|
|
*38 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 76,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 77,0
|
|
)
|
|
*40 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 78,0
|
|
)
|
|
*41 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 79,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 80,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 67,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 52,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *43 (LEmptyRow
|
|
)
|
|
uid 82,0
|
|
optionalChildren [
|
|
*44 (RefLabelRowHdr
|
|
)
|
|
*45 (TitleRowHdr
|
|
)
|
|
*46 (FilterRowHdr
|
|
)
|
|
*47 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*48 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*49 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*50 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*51 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*52 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*53 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*54 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*55 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNbRx"
|
|
type "positive"
|
|
value "1"
|
|
)
|
|
uid 188,0
|
|
)
|
|
*56 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNbTx"
|
|
type "positive"
|
|
value "1"
|
|
)
|
|
uid 190,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 94,0
|
|
optionalChildren [
|
|
*57 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *58 (MRCItem
|
|
litem &43
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 96,0
|
|
optionalChildren [
|
|
*59 (MRCItem
|
|
litem &44
|
|
pos 0
|
|
dimension 20
|
|
uid 97,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &45
|
|
pos 1
|
|
dimension 23
|
|
uid 98,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &46
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 99,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &55
|
|
pos 0
|
|
dimension 20
|
|
uid 189,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &56
|
|
pos 1
|
|
dimension 20
|
|
uid 191,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 100,0
|
|
optionalChildren [
|
|
*64 (MRCItem
|
|
litem &47
|
|
pos 0
|
|
dimension 20
|
|
uid 101,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &49
|
|
pos 1
|
|
dimension 50
|
|
uid 102,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &50
|
|
pos 2
|
|
dimension 100
|
|
uid 103,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &51
|
|
pos 3
|
|
dimension 100
|
|
uid 104,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &52
|
|
pos 4
|
|
dimension 50
|
|
uid 105,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &53
|
|
pos 5
|
|
dimension 50
|
|
uid 106,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &54
|
|
pos 6
|
|
dimension 80
|
|
uid 107,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 95,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 81,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@bus@width@adaption/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@bus@width@adaption/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@bus@width@adaption"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifoBridgeBusWidthAdaption"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "fifoBridgeBusWidthAdaption"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:45:15"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Memory"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Libs/Memory/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "08"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "fifoBridgeBusWidthAdaption"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Aug"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "August"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@bus@width@adaption/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifoBridgeBusWidthAdaption/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME\\win32"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "13:45:15"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "fifoBridgeBusWidthAdaption"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 51,0
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optionalChildren [
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uid 8,0
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optionalChildren [
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|
*72 (CptPort
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uid 108,0
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ps "OnEdgeStrategy"
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shape (Triangle
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xt "14250,21625,15000,22375"
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tg (CPTG
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uid 110,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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uid 111,0
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st "clock"
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blo "16000,22300"
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tm "CptPortNameMgr"
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dt (MLText
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st "clock : IN std_ulogic "
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)
|
|
thePort (LogicalPort
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decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
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|
|
suid 1,0
|
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)
|
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uid 113,0
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ps "OnEdgeStrategy"
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vasetType 1
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fg "0,65535,0"
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xt "23000,15625,23750,16375"
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tg (CPTG
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uid 115,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 116,0
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va (VaSet
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st "dataTx"
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blo "22000,16300"
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tm "CptPortNameMgr"
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thePort (LogicalPort
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m 1
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decl (Decl
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n "dataTx"
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b "(dataBitNbTx-1 DOWNTO 0)"
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suid 2,0
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tg (CPTG
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uid 121,0
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va (VaSet
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st "dataRx"
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blo "16000,16300"
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tm "CptPortNameMgr"
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dt (MLText
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font "courier,8,0"
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st "dataRx : IN std_ulogic_vector (dataBitNbRx-1 DOWNTO 0) ;"
|
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)
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thePort (LogicalPort
|
|
decl (Decl
|
|
n "dataRx"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNbRx-1 DOWNTO 0)"
|
|
o 2
|
|
suid 3,0
|
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*75 (CptPort
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|
uid 123,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 124,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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xt "14250,17625,15000,18375"
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tg (CPTG
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|
uid 125,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 126,0
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va (VaSet
|
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xt "16000,17500,19200,18500"
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st "emptyRx"
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blo "16000,18300"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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font "courier,8,0"
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)
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thePort (LogicalPort
|
|
decl (Decl
|
|
n "emptyRx"
|
|
t "std_ulogic"
|
|
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|
|
suid 4,0
|
|
)
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)
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)
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*76 (CptPort
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|
uid 128,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 129,0
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ro 270
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
|
|
uid 130,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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|
f (Text
|
|
uid 131,0
|
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va (VaSet
|
|
)
|
|
xt "19800,17500,22000,18500"
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|
st "fullTx"
|
|
ju 2
|
|
blo "22000,18300"
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tm "CptPortNameMgr"
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dt (MLText
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uid 132,0
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va (VaSet
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font "courier,8,0"
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xt "44000,3800,59500,4700"
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st "fullTx : IN std_ulogic ;"
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|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "fullTx"
|
|
t "std_ulogic"
|
|
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|
suid 5,0
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)
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*77 (CptPort
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uid 133,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 134,0
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ro 270
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "14250,19625,15000,20375"
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)
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tg (CPTG
|
|
uid 135,0
|
|
ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
|
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f (Text
|
|
uid 136,0
|
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va (VaSet
|
|
)
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xt "16000,19500,18800,20500"
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st "readRx"
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blo "16000,20300"
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tm "CptPortNameMgr"
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va (VaSet
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st "readRx : OUT std_ulogic ;"
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)
|
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thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "readRx"
|
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t "std_ulogic"
|
|
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|
|
suid 6,0
|
|
)
|
|
)
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|
)
|
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*78 (CptPort
|
|
uid 138,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
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uid 140,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 141,0
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va (VaSet
|
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)
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st "reset"
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blo "16000,24300"
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tm "CptPortNameMgr"
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va (VaSet
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font "courier,8,0"
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)
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thePort (LogicalPort
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decl (Decl
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n "reset"
|
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t "std_uLogic"
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|
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)
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)
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)
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*79 (CptPort
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uid 143,0
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ps "OnEdgeStrategy"
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uid 144,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
|
|
uid 145,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 146,0
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va (VaSet
|
|
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st "writeTx"
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ju 2
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blo "22000,20300"
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tm "CptPortNameMgr"
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thePort (LogicalPort
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suid 8,0
|
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|
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uid 187,0
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va (VaSet
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lineColor "0,32896,0"
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lineWidth 2
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biTextGroup (BiTextGroup
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uid 10,0
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first (Text
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va (VaSet
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second (Text
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|
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blo "15600,27600"
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gi *80 (GenericInterface
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uid 13,0
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va (VaSet
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|
|
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|
|
dataBitNbTx positive 1 "
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header "Generic Declarations"
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type "positive"
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|
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|
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portInstanceVisAsIs 1
|
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portInstanceVis (PortSigDisplay
|
|
sTC 0
|
|
sF 0
|
|
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portVis (PortSigDisplay
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sTC 0
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