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47 lines
1.5 KiB
VHDL
47 lines
1.5 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch)
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program IS distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License along with
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-- this program. If not, see <http://www.gnu.org/licenses/>
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--------------------------------------------------------------------------------
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-- Accumulator
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-- Accumulator with the step as signal and a synchronous clear signal.
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--
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-- Created on 2013-03-03
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--
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-- Version: 1.0
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-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch)
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--------------------------------------------------------------------------------
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--
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ARCHITECTURE RTL OF accumulator IS
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signal sum_s : unsigned(bitNb-1 downto 0);
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begin
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process (clock, reset)
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begin
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if reset = '1' then
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sum_s <= (OTHERS => '0');
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elsif rising_edge(clock) then
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if enable = '1' then
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sum_s <= unsigned(step) + sum_s;
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end if;
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if clear = '1' then
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sum_s <= (OTHERS => '0');
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end if;
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end if;
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end process;
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acc <= sum_s;
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END ARCHITECTURE RTL;
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