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30 lines
887 B
VHDL
30 lines
887 B
VHDL
ARCHITECTURE test OF pulseWidthModulator_tester IS
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constant clockPeriod: time := 50 ns;
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signal sClock: std_uLogic := '1';
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constant enPeriodNb: positive := 3;
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signal sEn: std_uLogic := '0';
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BEGIN
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------------------------------------------------------------------------------
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-- clock and reset
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--
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reset <= '1', '0' after clockPeriod/4;
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sClock <= not sClock after clockPeriod/2;
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clock <= sClock after clockPeriod/10;
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------------------------------------------------------------------------------
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-- control signals
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--
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amplitude <= to_unsigned( 64, amplitude'length),
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to_unsigned(128, amplitude'length) after 10*256*enPeriodNb*clockPeriod,
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to_unsigned(192, amplitude'length) after 20*256*enPeriodNb*clockPeriod;
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sEn <= '1' after (enPeriodNb-1)*clockPeriod when sEn = '0' else '0' after clockPeriod;
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en <= sEn;
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END test;
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