mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-23 09:53:29 +00:00
5 lines
76 B
VHDL
5 lines
76 B
VHDL
ARCHITECTURE sim OF zeroSigned IS
|
|
BEGIN
|
|
zero <= (others => '0');
|
|
END sim;
|