mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-30 04:43:26 +00:00
2771 lines
34 KiB
Plaintext
2771 lines
34 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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instances [
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(Instance
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name "I1"
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duLibraryName "Cursor_test"
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duName "divider_tester"
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elements [
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]
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mwi 0
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uid 1774,0
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)
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(Instance
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name "I0"
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duLibraryName "Cursor"
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duName "divider"
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elements [
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]
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mwi 0
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uid 2524,0
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
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)
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(vvPair
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|
variable "appl"
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value "HDL Designer"
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)
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|
(vvPair
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|
variable "arch_name"
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value "struct"
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)
|
|
(vvPair
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|
variable "concat_file"
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|
value "concatenated"
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)
|
|
(vvPair
|
|
variable "config"
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|
value "%(unit)_%(view)_config"
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)
|
|
(vvPair
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|
variable "d"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb"
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)
|
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(vvPair
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variable "d_logical"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb"
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)
|
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(vvPair
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variable "date"
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value "11.11.2019"
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)
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(vvPair
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variable "day"
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value "Mon"
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)
|
|
(vvPair
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variable "day_long"
|
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value "Monday"
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)
|
|
(vvPair
|
|
variable "dd"
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value "11"
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)
|
|
(vvPair
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variable "entity_name"
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value "divider_tb"
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)
|
|
(vvPair
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|
variable "ext"
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|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "f"
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|
value "struct.bd"
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)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "struct.bd"
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|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "struct"
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|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
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value "silvan.zahno"
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)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "11.11.2019"
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)
|
|
(vvPair
|
|
variable "graphical_source_group"
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|
value "UNKNOWN"
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)
|
|
(vvPair
|
|
variable "graphical_source_host"
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value "WE6996"
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)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
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value "08:13:22"
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)
|
|
(vvPair
|
|
variable "group"
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value "UNKNOWN"
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)
|
|
(vvPair
|
|
variable "host"
|
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value "WE6996"
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)
|
|
(vvPair
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|
variable "language"
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value "VHDL"
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)
|
|
(vvPair
|
|
variable "library"
|
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value "Cursor_test"
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)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
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value "D:\\Users\\ELN_labs\\VHDL_comp"
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|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
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value "$SCRATCH_DIR/Cursor_test/work"
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)
|
|
(vvPair
|
|
variable "mm"
|
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value "11"
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)
|
|
(vvPair
|
|
variable "module_name"
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value "divider_tb"
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)
|
|
(vvPair
|
|
variable "month"
|
|
value "Nov"
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|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "November"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd"
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)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd"
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)
|
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(vvPair
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variable "package_name"
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|
value "<Undefined Variable>"
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)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
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)
|
|
(vvPair
|
|
variable "series"
|
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value "HDL Designer Series"
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)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
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)
|
|
(vvPair
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|
variable "task_LeonardoPath"
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value "<TBD>"
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)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "C:\\EDA\\Modelsim\\win32"
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|
)
|
|
(vvPair
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|
variable "task_NC"
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value "<TBD>"
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)
|
|
(vvPair
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|
variable "task_PrecisionRTLPath"
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value "<TBD>"
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)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
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)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "08:13:22"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "divider_tb"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 198,0
|
|
optionalChildren [
|
|
*1 (Net
|
|
uid 1315,0
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 1,0
|
|
)
|
|
declText (MLText
|
|
uid 1316,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,9,0"
|
|
)
|
|
xt "-5000,34200,10500,35400"
|
|
st "SIGNAL reset : std_ulogic"
|
|
)
|
|
)
|
|
*2 (Net
|
|
uid 1325,0
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 2,0
|
|
)
|
|
declText (MLText
|
|
uid 1326,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,9,0"
|
|
)
|
|
xt "-5000,28200,10500,29400"
|
|
st "SIGNAL clock : std_ulogic"
|
|
)
|
|
)
|
|
*3 (Grouping
|
|
uid 1487,0
|
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optionalChildren [
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|
*4 (CommentText
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uid 1489,0
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shape (Rectangle
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uid 1490,0
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sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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)
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xt "47000,60000,66000,62000"
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)
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oxt "45000,22000,64000,24000"
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text (MLText
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uid 1491,0
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va (VaSet
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fg "0,0,32768"
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bg "0,0,32768"
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)
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xt "47200,60400,62600,61600"
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st "
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|
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"
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tm "CommentText"
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|
wrapOption 3
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|
visibleHeight 1600
|
|
visibleWidth 18600
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)
|
|
position 1
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|
ignorePrefs 1
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)
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*5 (CommentText
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uid 1492,0
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shape (Rectangle
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uid 1493,0
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sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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xt "15000,60000,41000,62000"
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oxt "13000,22000,39000,24000"
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text (MLText
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uid 1494,0
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va (VaSet
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fg "32768,0,0"
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font "Arial,12,1"
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)
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xt "22250,60250,33750,61750"
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st "
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<company name>
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|
"
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ju 0
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tm "CommentText"
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wrapOption 3
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visibleHeight 1600
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visibleWidth 25600
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)
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position 1
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ignorePrefs 1
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)
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*6 (CommentText
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uid 1495,0
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shape (Rectangle
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uid 1496,0
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sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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xt "20000,66000,41000,68000"
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oxt "18000,28000,39000,30000"
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text (MLText
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uid 1497,0
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va (VaSet
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fg "0,0,32768"
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bg "0,0,32768"
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)
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xt "20200,66400,38600,67600"
|
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st "
|
|
by %user on %dd %month %year
|
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"
|
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tm "CommentText"
|
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wrapOption 3
|
|
visibleHeight 1600
|
|
visibleWidth 20600
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)
|
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position 1
|
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ignorePrefs 1
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)
|
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*7 (CommentText
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uid 1498,0
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shape (Rectangle
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uid 1499,0
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sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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)
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oxt "39000,22000,45000,24000"
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text (MLText
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uid 1500,0
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va (VaSet
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fg "0,0,32768"
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bg "0,0,32768"
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st "
|
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Project:
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"
|
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tm "CommentText"
|
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wrapOption 3
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visibleHeight 1600
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visibleWidth 5600
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)
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position 1
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ignorePrefs 1
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)
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*8 (CommentText
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uid 1501,0
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shape (Rectangle
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uid 1502,0
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sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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)
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xt "20000,62000,41000,64000"
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)
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oxt "18000,24000,39000,26000"
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text (MLText
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uid 1503,0
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va (VaSet
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fg "0,0,32768"
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bg "0,0,32768"
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)
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xt "20200,62400,35400,63600"
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st "
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"
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tm "CommentText"
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wrapOption 3
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visibleHeight 1600
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visibleWidth 20600
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)
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position 1
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ignorePrefs 1
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uid 1504,0
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shape (Rectangle
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uid 1505,0
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sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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text (MLText
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va (VaSet
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fg "0,0,32768"
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bg "0,0,32768"
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st "
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tm "CommentText"
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wrapOption 3
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visibleHeight 1600
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visibleWidth 4600
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shape (Rectangle
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text (MLText
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tm "CommentText"
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shape (Rectangle
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text (MLText
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st "
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|
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|
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"
|
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tm "CommentText"
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wrapOption 3
|
|
visibleHeight 1600
|
|
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)
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position 1
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ignorePrefs 1
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)
|
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shape (Rectangle
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uid 1517,0
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sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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)
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oxt "13000,28000,18000,30000"
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text (MLText
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va (VaSet
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fg "0,0,32768"
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st "
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|
Edited:
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"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1600
|
|
visibleWidth 4600
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)
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position 1
|
|
ignorePrefs 1
|
|
)
|
|
]
|
|
shape (GroupingShape
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va (VaSet
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fg "65535,65535,65535"
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lineWidth 1
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)
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xt "15000,60000,66000,68000"
|
|
)
|
|
oxt "13000,22000,64000,30000"
|
|
)
|
|
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uid 1774,0
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shape (Rectangle
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uid 1775,0
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va (VaSet
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vasetType 1
|
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fg "39936,56832,65280"
|
|
lineColor "0,0,32768"
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lineWidth 2
|
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)
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|
xt "2000,49000,56000,57000"
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)
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oxt "0,0,8000,10000"
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ttg (MlTextGroup
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uid 1776,0
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ps "CenterOffsetStrategy"
|
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stg "VerticalLayoutStrategy"
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textVec [
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uid 1777,0
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va (VaSet
|
|
font "Verdana,12,1"
|
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)
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xt "8600,51900,18200,53300"
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|
st "Cursor_test"
|
|
blo "8600,53100"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*16 (Text
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|
uid 1778,0
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va (VaSet
|
|
font "Verdana,12,1"
|
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)
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xt "8600,53300,19800,54700"
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st "divider_tester"
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blo "8600,54500"
|
|
tm "BlkNameMgr"
|
|
)
|
|
*17 (Text
|
|
uid 1779,0
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va (VaSet
|
|
font "Verdana,12,1"
|
|
)
|
|
xt "8600,54700,11000,56100"
|
|
st "I1"
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|
blo "8600,55900"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
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)
|
|
ga (GenericAssociation
|
|
uid 1780,0
|
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ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
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uid 1781,0
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text (MLText
|
|
uid 1782,0
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va (VaSet
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isHidden 1
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font "Courier New,9,0"
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)
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xt "8600,61900,8600,61900"
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)
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header ""
|
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)
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elements [
|
|
]
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)
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)
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*18 (Net
|
|
uid 2116,0
|
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decl (Decl
|
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n "testMode"
|
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t "std_uLogic"
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o 5
|
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suid 3,0
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)
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declText (MLText
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uid 2117,0
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va (VaSet
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isHidden 1
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font "Courier New,8,0"
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)
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xt "0,0,15500,800"
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st "SIGNAL testMode : std_uLogic"
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)
|
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)
|
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*19 (Net
|
|
uid 2361,0
|
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decl (Decl
|
|
n "enPWM"
|
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t "std_uLogic"
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o 2
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|
suid 6,0
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)
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declText (MLText
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uid 2362,0
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va (VaSet
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isHidden 1
|
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font "Courier New,8,0"
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)
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xt "0,0,15500,800"
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st "SIGNAL enPWM : std_uLogic"
|
|
)
|
|
)
|
|
*20 (SaComponent
|
|
uid 2524,0
|
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optionalChildren [
|
|
*21 (CptPort
|
|
uid 2504,0
|
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ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2505,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "21250,32625,22000,33375"
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|
)
|
|
tg (CPTG
|
|
uid 2506,0
|
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 2507,0
|
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va (VaSet
|
|
)
|
|
xt "23000,32500,26400,33700"
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|
st "clock"
|
|
blo "23000,33500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*22 (CptPort
|
|
uid 2508,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2509,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "21250,34625,22000,35375"
|
|
)
|
|
tg (CPTG
|
|
uid 2510,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2511,0
|
|
va (VaSet
|
|
)
|
|
xt "23000,34500,26300,35700"
|
|
st "reset"
|
|
blo "23000,35500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*23 (CptPort
|
|
uid 2512,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2513,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "21250,30625,22000,31375"
|
|
)
|
|
tg (CPTG
|
|
uid 2514,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2515,0
|
|
va (VaSet
|
|
)
|
|
xt "23000,30300,28400,31500"
|
|
st "testMode"
|
|
blo "23000,31300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "testMode"
|
|
t "std_uLogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*24 (CptPort
|
|
uid 2516,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2517,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38000,30625,38750,31375"
|
|
)
|
|
tg (CPTG
|
|
uid 2518,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2519,0
|
|
va (VaSet
|
|
)
|
|
xt "32300,30400,37000,31600"
|
|
st "enRamp"
|
|
ju 2
|
|
blo "37000,31400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "enRamp"
|
|
t "std_uLogic"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*25 (CptPort
|
|
uid 2520,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2521,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38000,32625,38750,33375"
|
|
)
|
|
tg (CPTG
|
|
uid 2522,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2523,0
|
|
va (VaSet
|
|
)
|
|
xt "32600,32500,37000,33700"
|
|
st "enPWM"
|
|
ju 2
|
|
blo "37000,33500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "enPWM"
|
|
t "std_uLogic"
|
|
o 5
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 2525,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "22000,27000,38000,37000"
|
|
)
|
|
oxt "30000,16000,46000,26000"
|
|
ttg (MlTextGroup
|
|
uid 2526,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*26 (Text
|
|
uid 2527,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "22100,37000,25800,38200"
|
|
st "Cursor"
|
|
blo "22100,38000"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*27 (Text
|
|
uid 2528,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "22100,38200,26100,39400"
|
|
st "divider"
|
|
blo "22100,39200"
|
|
tm "CptNameMgr"
|
|
)
|
|
*28 (Text
|
|
uid 2529,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "22100,39400,23800,40600"
|
|
st "I0"
|
|
blo "22100,40400"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 2530,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 2531,0
|
|
text (MLText
|
|
uid 2532,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "9000,26800,9000,26800"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
portVis (PortSigDisplay
|
|
sIVOD 1
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*29 (Net
|
|
uid 2533,0
|
|
decl (Decl
|
|
n "enRamp"
|
|
t "std_uLogic"
|
|
o 3
|
|
suid 9,0
|
|
)
|
|
declText (MLText
|
|
uid 2534,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,9,0"
|
|
)
|
|
xt "0,0,15500,1200"
|
|
st "SIGNAL enRamp : std_uLogic"
|
|
)
|
|
)
|
|
*30 (Wire
|
|
uid 1317,0
|
|
shape (OrthoPolyLine
|
|
uid 1318,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "18000,35000,21250,49000"
|
|
pts [
|
|
"21250,35000"
|
|
"18000,35000"
|
|
"18000,49000"
|
|
]
|
|
)
|
|
start &22
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1321,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1322,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "18000,33600,22100,35000"
|
|
st "reset"
|
|
blo "18000,34800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &1
|
|
)
|
|
*31 (Wire
|
|
uid 1327,0
|
|
shape (OrthoPolyLine
|
|
uid 1328,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "16000,33000,21250,49000"
|
|
pts [
|
|
"21250,33000"
|
|
"16000,33000"
|
|
"16000,49000"
|
|
]
|
|
)
|
|
start &21
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1331,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1332,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "18000,31600,21800,33000"
|
|
st "clock"
|
|
blo "18000,32800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &2
|
|
)
|
|
*32 (Wire
|
|
uid 2118,0
|
|
shape (OrthoPolyLine
|
|
uid 2119,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "14000,31000,21250,49000"
|
|
pts [
|
|
"21250,31000"
|
|
"14000,31000"
|
|
"14000,49000"
|
|
]
|
|
)
|
|
start &23
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2122,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2123,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "14250,29600,20950,31000"
|
|
st "testMode"
|
|
blo "14250,30800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &18
|
|
)
|
|
*33 (Wire
|
|
uid 2363,0
|
|
shape (OrthoPolyLine
|
|
uid 2364,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "38750,33000,42000,49000"
|
|
pts [
|
|
"38750,33000"
|
|
"42000,33000"
|
|
"42000,49000"
|
|
]
|
|
)
|
|
start &25
|
|
end &14
|
|
sat 32
|
|
eat 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2367,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2368,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "39000,31600,44500,33000"
|
|
st "enPWM"
|
|
blo "39000,32800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*34 (Wire
|
|
uid 2535,0
|
|
shape (OrthoPolyLine
|
|
uid 2536,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "38750,31000,44000,49000"
|
|
pts [
|
|
"38750,31000"
|
|
"44000,31000"
|
|
"44000,49000"
|
|
]
|
|
)
|
|
start &24
|
|
end &14
|
|
sat 32
|
|
eat 1
|
|
st 0
|
|
sf 1
|
|
tg (WTG
|
|
uid 2539,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2540,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "40750,29600,46650,31000"
|
|
st "enRamp"
|
|
blo "40750,30800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &29
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 1
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "32768,32768,32768"
|
|
)
|
|
packageList *35 (PackageList
|
|
uid 187,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*36 (Text
|
|
uid 1297,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "-7000,19600,2500,21000"
|
|
st "Package List"
|
|
blo "-7000,20800"
|
|
)
|
|
*37 (MLText
|
|
uid 1298,0
|
|
va (VaSet
|
|
)
|
|
xt "-7000,21000,10500,24600"
|
|
st "LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
compDirBlock (MlTextGroup
|
|
uid 190,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*38 (Text
|
|
uid 191,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "arial,10,1"
|
|
)
|
|
xt "20000,0,31000,1200"
|
|
st "Compiler Directives"
|
|
blo "20000,1000"
|
|
)
|
|
*39 (Text
|
|
uid 192,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "arial,10,1"
|
|
)
|
|
xt "20000,1400,33000,2600"
|
|
st "Pre-module directives:"
|
|
blo "20000,2400"
|
|
)
|
|
*40 (MLText
|
|
uid 193,0
|
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)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "3000,500,3000,500"
|
|
blo "3000,500"
|
|
tm "WireNameMgr"
|
|
)
|
|
s (Text
|
|
va (VaSet
|
|
)
|
|
xt "3000,500,3000,500"
|
|
blo "3000,500"
|
|
tm "SignalTypeMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
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|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
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|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "3000,500,3000,500"
|
|
blo "3000,500"
|
|
tm "WireNameMgr"
|
|
)
|
|
s (Text
|
|
va (VaSet
|
|
)
|
|
xt "3000,500,3000,500"
|
|
blo "3000,500"
|
|
tm "SignalTypeMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
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)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineColor "32768,0,0"
|
|
lineStyle 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,5100,1400"
|
|
st "bundle0"
|
|
blo "0,1200"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,1400,1800,2800"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,5900,1400"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,1400,11800,2800"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 2
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1400,18500,-200"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1750"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "200,300,600,1300"
|
|
st "1"
|
|
blo "200,1100"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*62 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "11800,20000,22600,21200"
|
|
st "Frame Declarations"
|
|
blo "11800,21000"
|
|
)
|
|
*63 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11800,21200,11800,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 1
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1400,11000,-200"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1750"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "200,300,600,1300"
|
|
st "1"
|
|
blo "200,1100"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*64 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "11800,20000,22600,21200"
|
|
st "Frame Declarations"
|
|
blo "11800,21000"
|
|
)
|
|
*65 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11800,21200,11800,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,750,2600,2150"
|
|
st "Port"
|
|
blo "0,1950"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,750,2600,2150"
|
|
st "Port"
|
|
blo "0,1950"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,9,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,10,1"
|
|
)
|
|
xt "-7000,25800,1600,27000"
|
|
st "Declarations"
|
|
blo "-7000,26800"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,10,1"
|
|
)
|
|
xt "-7000,27000,-2800,28200"
|
|
st "Ports:"
|
|
blo "-7000,28000"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,10,1"
|
|
)
|
|
xt "-7000,27000,-1000,28200"
|
|
st "Pre User:"
|
|
blo "-7000,28000"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,10,0"
|
|
)
|
|
xt "-5000,29400,-5000,29400"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,10,1"
|
|
)
|
|
xt "-7000,27000,4000,28200"
|
|
st "Diagram Signals:"
|
|
blo "-7000,28000"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,10,1"
|
|
)
|
|
xt "-7000,27000,300,28200"
|
|
st "Post User:"
|
|
blo "-7000,28000"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,10,0"
|
|
)
|
|
xt "-5000,41400,-5000,41400"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 9,0
|
|
usingSuid 1
|
|
emptyRow *66 (LEmptyRow
|
|
)
|
|
uid 2382,0
|
|
optionalChildren [
|
|
*67 (RefLabelRowHdr
|
|
)
|
|
*68 (TitleRowHdr
|
|
)
|
|
*69 (FilterRowHdr
|
|
)
|
|
*70 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*71 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*72 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*73 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*74 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*75 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*76 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*77 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*78 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*79 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 2369,0
|
|
)
|
|
*80 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 2371,0
|
|
)
|
|
*81 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "testMode"
|
|
t "std_uLogic"
|
|
o 5
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 2373,0
|
|
)
|
|
*82 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "enPWM"
|
|
t "std_uLogic"
|
|
o 2
|
|
suid 6,0
|
|
)
|
|
)
|
|
uid 2379,0
|
|
)
|
|
*83 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "enRamp"
|
|
t "std_uLogic"
|
|
o 3
|
|
suid 9,0
|
|
)
|
|
)
|
|
uid 2541,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 2395,0
|
|
optionalChildren [
|
|
*84 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *85 (MRCItem
|
|
litem &66
|
|
pos 5
|
|
dimension 20
|
|
)
|
|
uid 2397,0
|
|
optionalChildren [
|
|
*86 (MRCItem
|
|
litem &67
|
|
pos 0
|
|
dimension 20
|
|
uid 2398,0
|
|
)
|
|
*87 (MRCItem
|
|
litem &68
|
|
pos 1
|
|
dimension 23
|
|
uid 2399,0
|
|
)
|
|
*88 (MRCItem
|
|
litem &69
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 2400,0
|
|
)
|
|
*89 (MRCItem
|
|
litem &79
|
|
pos 0
|
|
dimension 20
|
|
uid 2370,0
|
|
)
|
|
*90 (MRCItem
|
|
litem &80
|
|
pos 1
|
|
dimension 20
|
|
uid 2372,0
|
|
)
|
|
*91 (MRCItem
|
|
litem &81
|
|
pos 2
|
|
dimension 20
|
|
uid 2374,0
|
|
)
|
|
*92 (MRCItem
|
|
litem &82
|
|
pos 3
|
|
dimension 20
|
|
uid 2380,0
|
|
)
|
|
*93 (MRCItem
|
|
litem &83
|
|
pos 4
|
|
dimension 20
|
|
uid 2542,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 2401,0
|
|
optionalChildren [
|
|
*94 (MRCItem
|
|
litem &70
|
|
pos 0
|
|
dimension 20
|
|
uid 2402,0
|
|
)
|
|
*95 (MRCItem
|
|
litem &72
|
|
pos 1
|
|
dimension 50
|
|
uid 2403,0
|
|
)
|
|
*96 (MRCItem
|
|
litem &73
|
|
pos 2
|
|
dimension 100
|
|
uid 2404,0
|
|
)
|
|
*97 (MRCItem
|
|
litem &74
|
|
pos 3
|
|
dimension 50
|
|
uid 2405,0
|
|
)
|
|
*98 (MRCItem
|
|
litem &75
|
|
pos 4
|
|
dimension 100
|
|
uid 2406,0
|
|
)
|
|
*99 (MRCItem
|
|
litem &76
|
|
pos 5
|
|
dimension 100
|
|
uid 2407,0
|
|
)
|
|
*100 (MRCItem
|
|
litem &77
|
|
pos 6
|
|
dimension 50
|
|
uid 2408,0
|
|
)
|
|
*101 (MRCItem
|
|
litem &78
|
|
pos 7
|
|
dimension 80
|
|
uid 2409,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
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|
fixedRow 2
|
|
name "Ports"
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|
uid 2396,0
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vaOverrides [
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]
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)
|
|
]
|
|
)
|
|
uid 2381,0
|
|
)
|
|
genericsCommonDM (CommonDM
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ldm (LogicalDM
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|
emptyRow *102 (LEmptyRow
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)
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uid 2411,0
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optionalChildren [
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*103 (RefLabelRowHdr
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)
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|
*104 (TitleRowHdr
|
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)
|
|
*105 (FilterRowHdr
|
|
)
|
|
*106 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*107 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*108 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*109 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*110 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*111 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*112 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*113 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 2423,0
|
|
optionalChildren [
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|
*114 (Sheet
|
|
sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
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|
fontColor "0,0,0"
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font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *115 (MRCItem
|
|
litem &102
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 2425,0
|
|
optionalChildren [
|
|
*116 (MRCItem
|
|
litem &103
|
|
pos 0
|
|
dimension 20
|
|
uid 2426,0
|
|
)
|
|
*117 (MRCItem
|
|
litem &104
|
|
pos 1
|
|
dimension 23
|
|
uid 2427,0
|
|
)
|
|
*118 (MRCItem
|
|
litem &105
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 2428,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
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)
|
|
uid 2429,0
|
|
optionalChildren [
|
|
*119 (MRCItem
|
|
litem &106
|
|
pos 0
|
|
dimension 20
|
|
uid 2430,0
|
|
)
|
|
*120 (MRCItem
|
|
litem &108
|
|
pos 1
|
|
dimension 50
|
|
uid 2431,0
|
|
)
|
|
*121 (MRCItem
|
|
litem &109
|
|
pos 2
|
|
dimension 100
|
|
uid 2432,0
|
|
)
|
|
*122 (MRCItem
|
|
litem &110
|
|
pos 3
|
|
dimension 100
|
|
uid 2433,0
|
|
)
|
|
*123 (MRCItem
|
|
litem &111
|
|
pos 4
|
|
dimension 50
|
|
uid 2434,0
|
|
)
|
|
*124 (MRCItem
|
|
litem &112
|
|
pos 5
|
|
dimension 50
|
|
uid 2435,0
|
|
)
|
|
*125 (MRCItem
|
|
litem &113
|
|
pos 6
|
|
dimension 80
|
|
uid 2436,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 2424,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 2410,0
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|
type 1
|
|
)
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|
activeModelName "BlockDiag"
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)
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