mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-23 09:53:29 +00:00
14 lines
211 B
VHDL
14 lines
211 B
VHDL
ARCHITECTURE sim OF DFF_pre IS
|
|
BEGIN
|
|
|
|
process(clk, pre)
|
|
begin
|
|
if pre = '1' then
|
|
q <= '1' after delay;
|
|
elsif rising_edge(clk) then
|
|
q <= d after delay;
|
|
end if;
|
|
end process;
|
|
|
|
END sim;
|