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22 lines
483 B
VHDL
22 lines
483 B
VHDL
ARCHITECTURE test OF divider_tester IS
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constant clockPeriod: time := 50 ns;
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signal sClock: std_uLogic := '1';
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BEGIN
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reset <= '1', '0' after clockPeriod/4;
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sClock <= not sClock after clockPeriod/2;
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clock <= sClock after clockPeriod/10;
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testMode <= '1', '0' after 10000*clockPeriod;
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start <= '0',
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'1' after 210 us,
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'0' after 210 us + clockPeriod,
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'1' after 2.1 ms,
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'0' after 2.1 ms + clockPeriod;
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END test;
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