mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-23 18:03:27 +00:00
5 lines
107 B
VHDL
5 lines
107 B
VHDL
ARCHITECTURE sim OF and2inv2 IS
|
|
BEGIN
|
|
out1 <= (not in1) and (not in2) after delay;
|
|
END ARCHITECTURE sim;
|